VLSI design Chapter II

Chapter II
Programmable Logic Devices (PLD)
INTRODUCTION
An IC that contains large numbers of gates, flip-flops, etc. that can be configured by the user to
perform different functions is called a Programmable Logic Device (PLD).
The internal logic gates and/or connections of PLDs can be changed/configured by a programming
process. One of the simplest programming technologies is to use fuses. In the original state of the device, all
the fuses are intact.
Programming the device involves blowing those fuses along the paths that must be removed in order to
obtain the particular configuration of the desired logic function. PLDs are typically built with an array of AND
gates (AND-array) and an array of OR gates (OR-array).

Advantages of PLDs:
Problems of using standard ICs:
Problems of using standard ICs in logic design are that they require hundreds or thousands of these ICs,
considerable amount of circuit board space, a great deal of time and cost in inserting, soldering, and testing.
Also require keeping a significant inventory of ICs.
Advantages of using PLDs:
Advantages of using PLDs are less board space, faster, lower power requirements (i.e., smaller power
supplies), less costly assembly processes, higher reliability (fewer ICs and circuit connections means easier
troubleshooting), and availability of design software.
A typical PLD may have hundreds to millions of gates.
In order to show the internal logic diagram for such technologies in a concise form, it is necessary to have
special symbols for array logic. Fig 1 shows the conventional and array logic symbols for a multiple input
AND and a multiple input OR gate.

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VLSI design Chapter II
Fig 2 shown the generic structure of a PLD with two inputs and two outputs. As can be seen from the
diagram, there are programmable connections between the input lines and the product lines, as well as between
product lines and sum lines; such connections are known as crosspoints.

The PLA (Programmable Logic Array):

The PLA (Programmable Logic Array) has programmable connections for both AND and OR arrays.
So it is the most flexible type of PLD.

Each of the AND gates can be programmed to generate a product term of the input variables and does
not generate all the minterms. The AND and OR gates inside the PLA are initially fabricated with the links
(fuses) among them. The specific Boolean functions are implemented in sum of products form by opening
appropriate links and leaving the desired connections.
The PAL (Programmable Array Logic)

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VLSI design Chapter II
The PAL device is a PLD with a fixed OR array and a programmable AND array. As only AND gates
are programmable, the PAL device is easier to program but it is not as flexible as the PLA.

The device shown in the fig5 has 4 inputs and 4 outputs. Each input has a buffer-inverter gate, and each
output is generated by a fixed OR gate. The device has 4 sections, each composed of a 3-wide AND-OR array,
meaning that there are 3 programmable AND gates in each section.
Each AND gate has 10 programmable input connections indicating by 10 vertical lines intersecting
each horizontal line. The horizontal line symbolizes the multiple input configuration of an AND gate. One of
the outputs F1 is connected to a buffer-inverter gate and is fed back into the inputs of the AND gates through
programmed connections.

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Complex Programmable Logic Devices (CPLDs)

• CPLD is the complex programmable Logic

Device which is more complex than the SPLD.
• Built on SPLD architecture and creates a much
larger design.
• SPLD are used to integrate the functions of a
number of discrete digital ICs into a single
device
• CPLD can be used to integrate the functions
of a number of SPLDs into a single device.
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 Architecture of CPLD
• CPLD architecture is based on
– Logic blocks or Functional blocks
– Global programmable interconnect and
– I/O block

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 Architecture of CPLD
• CPLD consists of a number of logic blocks or
functional blocks, each of which contains a
macrocell and either PLA or PAL.
• Macrocell contains logic implementing
disjunctive normal form expressions and more
specialized logic operations.
• Macrocell also provides additional circuitry to
accommodate registered or nonregistered
outputs, along with signal polarity control.
– Polarity control provides an output that is a true signal
or a complement of the true signal. 3
Architecture of CPLD

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 Programmable Interconnect
• In center lies the global programmable
interconnect.
• This interconnect allows connections to the logic
block, macrocells and the I/O cell arrays (the digital
I/O cells of the CPLD connecting to the pins of the
CPLD package).
• The actual number of logic blocks within a CPLD
varies ,the more logic blocks available, the larger
the design that can be configured.
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 Programming Complex PLDs
• Some CPLDs are programmed using a PAL
programmer
– this method becomes inconvenient for devices with
hundreds of pins
• Instead of relying on a programming unit to
configure chip , it is advantageous to be able to
perform the programming while the chip is still
attached to its circuit board.
• This method of programming is known is called In-
System programming (ISP).
– It is not usually provided for PLAs (or) PALs , but it is
available for the more sophisticated chips such as
Complex programmable logic device.
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Examples of CPLDs

Examples of CPLDs and high pin count package types

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 Who makes the CPLDs?

Manufacturer CPLD Products

Altera MAX 5000, 7000 & 9000

Altmel ATF & ATV
Cypress FLASH370, Ultra37000
Lattice ispLSI 1000 to 8000
Philips XPLA
Vantis MACH 1 to 5
Xilinx XC9500

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 ASIC
• Application Specific Integrated Circuit
• An ASIC is an IC that is designed to perform a
particular, specialized function
• A complete system or product is integrated onto a
chip and virtually no other components are
required
• It is not software programmable
• It is not a memory chip, but may contain Memory
• Examples would include
– MPEG decoder
– Audio processor for Dolby noise reduction
– Image processor for MRI 9
 Types of ASICs
• Full-Custom ASICs
– Complete IC design and developments are customized
by the designer.
– Offers the highest performance and lowest part cost.
• Standard-Cell–Based ASICs
– Manufacturer creates functional blocks with known
electrical characteristics (propagation delay, capacitance
and inductance). Utilizing these functional blocks,
standard cell of very high gate density and good
electrical performance is designed.
– This gives a high degree of flexibility, provided that
standard functions are able to meet the requirements. 10
 Types of ASICs
• FPGA
– Fully predesigned silicon, logic functions and
interconnect
– Programmed with a ”bit file” to configure logic and
interconnect
– Medium performance, higher power consumption
– Very quick to implement, minutes
– Better for more limited volume applications

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 Advantages of ASIC
1. Small in size
– Size of an ASIC is always smaller as compared to other
programmable devices. Small size consequently leads to
advantages in speed and power consumption.
2. No routing Issues
– There is no issue of routing for the end user in ASIC once it is
designed.
3. No timing Issues
– Digital logic switching, analog effects and communication
between blocks in the chip is faster in ASIC.
– Longer wires between components may affect the timing.
Sometimes, over timing or under timing the new added
design may yield erroneous result. An ASIC doesn’t have this
problem. 12
 Advantages of ASIC
4. Less Power Consumption
– ASIC consumes less power because logic operations are
done within a chip; since smaller components have
much smaller parasitic resistance, capacitance and
inductance.
5. Fully developed and functional
– ASIC is designed from scratch to the fully functional
stage. After its manufacturing no other configuration is
required to be done.

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 Drawbacks
1. Not flexible
– ASIC are made for a specific purpose. So, they are not
flexible. But using PLDs, it is possible to achieve greater
functionality with a simpler hardware design.
2. Higher System Cost
– By eliminating the ASIC design, system cost on a low-volume
product can be lowered. Only for higher-volume products,
the production cost of ASIC is lower. Reconfigurable
computing systems are upgradeable and extend the useful
life of the system. This reduces lifetime costs.
3. Increased Time to Market
– Designing of an ASIC is very complex and time consuming.
Moreover before marketing, ASIC must be tested thoroughly
and if fault is detected the IC has to be redesigned.
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 FIELD PROGRAMMABLE GATE ARRAYS (FPGA)
• The “FPGA is an integrated circuit that contains
many (over 10,000) identical logic cells that can
be viewed as standard components.”
• The individual cells are interconnected by a matrix
of wires and programmable switches.
• Unlike CPLDs (Complex Programmable Logic
Devices) FPGAs contain neither AND nor OR
planes.

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FPGA-Architecture

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 Architecture of FPGA
• Every FPGA consists of
– Configurable logic blocks(CLBs)
– Configurable input output blocks(IOBs)
– Programmable Interconnects.
• Also, there will be clock circuitry for driving the
clock signals to each logic block, and additional
logic resources such as ALUs, memory, and
decoders may be available.

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 Configurable logic blocks (CLBs)
• A basic logic cell is based on Look Up Tables (LUT).
• Consists of registers (memory), Mux’s and
combinational functional unit.
• An array of CLBS are embedded within a set of
vertical and horizontal channels that contain
routing which can be personalized to interconnect
CLBs.

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• The following figure represents the architecture of a
single CLB.

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Configurable Input / Output logic locks (IOBs):
• CLBs and routing channels are surrounded by a set of
programmable I/Os
• Can be programmed as either Input/output/both

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 Programmable Interconnect/ Routing
• Three types of Routings are used
– Short lines
– Switch matrix
– Long lines
• Each CLB is connected with the immediately
neighboring CLBs and These connections are called
as short lines.
– For simplicity only the connections with CLB in the top
left are shown. In reality, all four CLBs have connections
to their nearest neighbors.
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Programmable Interconnect

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 Switch Matrix
• Other routing resources pass by a number of CLBs
before reaching switch matrices. These switch
matrices allow a signal to be routed from one
switch matrix to another, eventually connecting
CLBs that can be relatively far from each other.
• The disadvantage to this method is that each trip
through a switch matrix results in a significant
delay.

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 Long Lines
• Long lines are used to connect critical CLBs that
are physically far from each other on the chip
without inducing much delay.
• These lines usually go from one end of the die to
the other without connecting to a switch matrix.
• For critical paths, long lines ensure that there will
not be a significant delay.

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 Advantages
• Design cycle Is significantly reduced. A user can
program an FPGA design in a few minutes or
seconds rather than weeks or months required for
mask programmed parts.
• High gate density i.e, it offers large gate counts.
Compared with PLDs
• No custom masks tooling is required saving
thousands of dollars(Low cost).
• Low risk and highly flexible.
• Reprogram ability for some FPGAs(design can be
altered easily).
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 Limitations
• Speed is comparatively less.
• The circuit delay depends on the performance of
the design implementation tools.
• The mapping of the logic design into FPGA
architecture requires sophisticated design
implementation (CAD)tools than PLDs.

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 Different FPGA Vendors
• Though there are various FPGA vendors in the world market only
two or three manufacturers are well known in the industry. For
example :
– Xilinx : Founded by Ross Freeman, original
inventor of FPGAs in 1984.
Sparten II,IIE,Sparten III,Virtex …
– Altera: Altera cyclone II FPGA and
associated design, software Quartus II

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 FPGA PROGRAMMING TECHNOLOGIES
• Two basic types of programmable elements
for an FPGA are
– Static RAM and
– Anti-fuses.
• Each logic block in an FPGA has a small
number of inputs and one output.
• There are two types of FPGAs.(i) SRAM based
FPGAs and (ii) Anti-fuse technology
based(OTP).
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 Antifuse Technology
• Two terminal device which has a very high
resistance between the two terminals when its
un-programmed and when programmed, or
“blown”, creates a very low resistance or
permanent connection.
– Done by applying a high voltage from 11 V to 21 V which
will create the low resistive permanent connection.
• Antifuse technologies come in two types.
– oxide-nitride-oxide (ONO) dielectric based and
– amorphous silicon or metal-to-metal Antifuse structures.

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 Antifuse Technology

Amorphous silicon column Polysilicon via

Metal
Oxide
Metal
Substrate

(a) Before programming (b) After programming

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 SRAM-based Technology
• SRAM FPGA architecture consists of static RAM cells
to control pass gates or multiplexers
• SRAM cell can be programmed as either ‘0’ or ‘1’
– When it is ‘1’ the transistor creates a connection
between two lines
– When it is ‘0’ the connection is changed to open state

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 Adv. & Disadv. of Antifuse
• Antifuse programming technology is faster than
SRAM programming technology due to the RC
delays introduced by the interconnect structure.
• Antifuse technology has more silicon area per gate
and is easier to route than SRAM technology.
• A disadvantage of antifuse FPGA is that they require
more process layers and mask steps and also
contain high voltage programming transistors.

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 Adv. & Disadv. of SRAM
• SRAM based technology is very flexible with in-
system programmability and the ability to
reconfigure the design while antifuse technology is
one-time programmable (OTP). This ability reduces
overall cost of the design.
• A disadvantage of SRAM technology is that it is
volatile meaning it has to be reprogrammed every
time power is turned off and on again. The SRAM
usually require an extra memory element to
program the chip which occupies board space
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