MEL G623 Advanced VLSI Design Course Handout

SECOND SEMESTER 2021-2022

Course Handout Part II
Date: Tue 04 Jan 2022

In addition to part-I (General Handout for all courses appended to the time table) this portion gives further specific
details regarding the course.

Course No. : MEL G623

Course Title : ADVANCED VLSI DESIGN
Instructor-in-Charge : Surya Shankar Dan

Prerequisites of the Course:

• Physics and Modeling of Microelectronic Devices (MEL G631) or equivalent
• VLSI Design (MEL G621) or equivalent

Scope and Objective of the Course:

Deep submicron device behavior and models, Interconnect modeling for parasitic estimation, Clock signals and
system timing-Digital phase locked loop design, memory and array structures, Input/output circuits design, ASIC
technology, FPGA technology, High speed arithmetic circuits design,-Parallel prefix computation, Logical effort in
circuit design, Low power VLSI circuits-Adiabatic logic circuits, Multi threshold circuits, Digital BICMOS circuits,
Design of VLSI systems.

Textbooks:
1. Kaushik Roy & Sharat C. Prasad, “Low-Power CMOS VLSI Circuit Design”, Wiley
2. Yuan Taur & Tak H. Ning, “Fundamentals of Modern VLSI Devices”, Cambridge University Press

Evaluation Scheme:
# Component Duration Marks Weights Date & time Evaluation
1 Mid semester 90 min 70 35 % To be announced Open
2 Project presentation ~ 3 months 30 15 % Mid semester evaluation Open
3 Project report ~ 1 month 20 10 % End semester evaluation Open
4 End semester 120 min 80 40 % As per Timetable Closed
Total 200 100 %

Project: The assignments included in the projects will extensively use cadence® EDA tools, synopsys® TCAD
tools and python for scripting.

Chamber Consultation Hour: Will be announced in class.

Notices: All notices related to the course will be put on the CMS and shared through institute email.

Make-up Policy: Make up will be given only on genuine reasons. Applications for make-up should be given in
advance and prior permission should be obtained for Scheduled tests.

INSTRUCTOR-IN-CHARGE

Surya S. Dan Tue 4 Jan 2022 Page 1 / 1

 SECOND SEMESTER 2021-2022
Course Handout Part II
Date: Jan 03, 2022

In addition to Part-I (General Handout for all courses appended to the timetable) this
portion gives further specific details regarding the course.

Course No. : MEL G632

Course Title : Analog IC Design
Instructor-in-charge: Dr. Parikshit Sahatiya

1. COURSE DESCRIPTION:

Basic Analog IC Design Issues, Analog Layouts, MOS Switch-- Charge Injection,
Current And Voltage Biasing and Reference Generation Circuits, Common Mode
Feedback Circuit, Replica Bias, Design, Analysis and Synthesis of Single Stage
Amplifiers, Differential Amplifiers, Operational Amplifiers and Operational
Transconductance Amplifier Design, Low Power OPAMP , OPAMP/ OTA design in
Subthreshold Operation region, Frequency Compensation, Current Mode Analog
Circuit Design, Noise- Analysis and Estimation In Amplifiers, emerging trends.

MEL G632 Analog IC Design 325

The course describes both theoretical and practical aspects of Analog integrated
circuits. Starting from the basic concepts of MOSFET to major analog building blocks;
like operational amplifiers, trans-conductance amplifiers, advanced biasing circuits,
switched capacitor circuits including in depth understanding of linear building blocks
like differential amplifiers, current mirrors, references, comparators, cascode and
buffer amplifiers. The characterization and the performance of the linear integrated
circuits will be verified by powerful EDA tools like Cadence withstandard CMOS
foundry model files.

2. SCOPE AND OBJECTIVE:

This course deals with the analysis and design of analog CMOS integrated circuits,
emphasizing fundamentals and new paradigms that student need to master in today’s
industry. Analog design is art and science at the same time. It is art because it requires
creativity and science because a certain level of methodology requires to carry out a
design. The objective of this course is to develop both a solid foundation and methods
of analyzing analog circuits by inspection.

Page 1 of3 MEL G632Analog IC Design: Course Handout Part II

 3. TEXT BOOK:

T1: B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 1st ed., 2001.

4. REFERENCE BOOKS:

R1: Paul R. Gray & Robert G. Meyer. Analysis and Design of Analog Integrated
Circuits. Wiley, 4th ed., 2010.
R2: David Johns & Ken Martin, Analog Integrated Circuit Design, John Wiley & Sons
2nd ed., 2012.
R3: Phillip E. Allen &Dogulas R. Holberg, CMOS Analog Circuit Design, Oxford
University Press,3rd ed., 2013.
R4: Adel S. Sedra et. al., Microelectronic Circuits: Theory and Applications, Oxford
University Press,6th., 2013.
R5: R. Jacob Baker, CMOS: Mixed-Signal Circuit Design, Wiley,2008.

COURSE PLAN

Section Lecture # Topic Brief Reference

I 1-2 Introduction to Analog A brief overview of the course and the Lect notes/
Design role of Analog IC Design. Ch. 1, Razavi
II 3- 4 Integrated-Circuit Described both the operation and Lect
Devices and Modelling modelling of semiconductor devices notes/Ch. 2,
Razavi
III 5-6 Analog CMOS Understand the current sink and Lect notes/
Subcircuits source, and current mirrors circuits. Allen-Ch4
IV 7-8 Basic Single stage Varity of single stage amplifiers (CS, Lect notes/
Amplifiers CD, CG) with active load will be Ch. 3, Razavi
discussed.
V 9-10 Frequency response of Briefly discussed an introductory view Lect notes/R2
single stage amplifiers of the frequency response of electronic Ch. 4/ Ch. 6,
circuits. Razavi
VI 11-14 Negative feedback Explore how to model negative Lect notes/R2
system and stability feedback systems and how to analyze Ch. 5/ Ch. 6,
the negative feedback systems. Razavi
VII 15-20 CMOS operational Learn different amplifier topologies Ch. 9-10,
amplifier and how to design such a high gain Razavi/Ch. 6-
amplifiers. 7, R3
VIII 21-23 CMOS Comparators Explore different analog comparator Ch. 8 R3
topologies
IX 24-26 Output stages and Analysis and design of a variety of Ch. 11, R4
power amplifiers output-stage amplifiers

Page 2 of3 MEL G632Analog IC Design: Course Handout Part II

 X 27-29 Feedback Topologies Analysis and design of four basic Ch. 10, R4
feedback topologies.
XI 30-33 Bandgap and current Explore how a voltage and current Ch. 11, Razavi
reference circuits references can be realized, the absolute
value of which is highly accurate.
XII 34-37 Phase-locked loops The analysis and design of PLLs with Ch. 15, Razavi
particular attention to implementation
in VLSI topologies.
XIII 38-41 D-to-A and A- to-D Learn the data converter fundamentals Ch. 28-29, R5
converters and architectures

5. EVALUATIONSCHEME:
Weightage
Duration % Marks
Component Date &Time Remarks
(min)
Mid Term 90 25 75 As per Timetable CB
10
Quiz 30
OB
Lab 20 60 OB
Project 15 45 OB
Comprehensive Exam 120 30 90 As per Timetable CB
Total 100 300

6. CHAMBER CONSULTATION HOUR: To be announced in the class.

7. NOTICES:CMS

8. Makeup Policy: Make-up only to those who apply before start of test. Those
who apply after the start of test will not be granted any make-up. No
make-up for Comprehensive test.

9. Academic Honesty and Integrity Policy: Academic honesty and integrity

are to be maintained by all the students throughout the semester and
no type of academic dishonesty is acceptable.

Instructor-in-charge
MEL G632

Page 3 of3 MEL G632Analog IC Design: Course Handout Part II

 BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE,
PILANI

II SEMESTER, 2021-2022
Course Handout (Part -11)
Date: 01-01-2022
In addition to Part I (General Handout for all courses appended to the time table) this portion gives
further specific details regarding the course.
Course No. : MEL G641
Course Title : CAD for IC Design
Instructor-in-charge : Sumit K Cahtterjee

Course Description: Introduction to VLSI design methodologies and supporting CAD tool environment;
overview of `C', data structure, graphics and CIF; concepts, structures and algorithms of some of the
following CAD tools; schematic editors; layout editors; module generators; silicon compilers; placement
and routing tools; behavioural, functional, logic and circuit simulators; aids for test generation and testing.

1. Scope and Objective of the course:

To teach the basic concepts of CAD tools used for IC/VLSI Design process. To be conversant with the
use of existing CAD tools and algorithms for all the stages of the design cycle of a VLSI chip design,
To study modeling using HDL (VHDL/Verilog) and to study the design issues involved in the
development of CAD tools., Current trends in CAD tools for IC/VLSI design.
2. Text Book:
(i) Algorithm for VLSI Physical Automation, 3rd Edition Author: Naveed Sherwani
Publisher, Year: Kluwer Academic Press, 1998

3. Reference Books
(i) An Introduction to CAD for VLSI Author: Stephen M. Trimberger
Publisher, Year: Kluwer Academic Press 1987.

(ii) VLSI Physical Design Automation: Theory and practice Author: Sadiq M Sait and Habib
Youssef
Publisher, Year: World Scientific Press, 1999

(iii) Computer Aids for VLSI Design Author: Steven M. Rubin

Publisher, Year: Addison Wesley, 1987

(iv) Simulation in the Design of Digital systems Author: John B. Gosling

Publisher, Year: Cambridge University Press (CUP), 1993

(v) Introduction to VLSI Systems Author: Carver Mead and Lynn Conway Publisher, Year:
Addison-Wesley,1980
(vi) A VHDL Primer, 3rd Edition, Author: J. Bhaskar
Publisher, Year: Pearson /Prentice-Hall, 1999

(vii) Verilog HDL Author: Samir Palnitkar

Publisher, Year: Pearson Education Asia, 2007

(viii) Synthesis and Optimization of Digital Circuits Author: Giovanni De Micheli

Publisher, Year: Tata McGraw-Hill, 1994

4. Course Plan
Topics Lectures

An introduction to electronic system design and CAD for IC 1

Design

CAD: A general overview 1

Partitioning 4

Floor-planning and Placement 8

Routing 5

Schematic, Layout and Stick Editors 5

Overview of CIF 1

Simulation 4

(Behavioral , Functional, Logic, Mixed mode, and

Fault simulation)
High Level and logic Synthesis 4

Hardware Allocation and Assignment 3

Scheduling and Algorithms 2

Timing and Power Analysis 3

TOTAL 41
 5. Evaluation schedule:

EC No. Components Duration Weightage Date & Time Remarks

(%)

1. Midsem Test 90 min. 25% As per Timetable Closed Book

2. Comprehensive Examination 2 Hrs 35% As per timetable Closed Book

3. Project/Seminar/Lab Regular 40% Open Book

Assignments/Quiz

6. Chamber consultation hour: Will be announced in the class.

7. Notices: All notices related to the course will be put on the CMS.

8. Academic Honesty and Integrity Policy: Academic honesty and

integrity are to be maintained by all the students throughout
the semester and no type of academic dishonesty is
acceptable.

Instructor In-Charge
(MEL G641)