CBCS SGHEME

17EC53
USN

Fifth Semester B.E. Degree Examination, Aug./Sept.2020

Verilog HDL
Max. Marks: 100
Time: 3 hrs.

Note: Answer any FlVE full questions, choosing ONE full question from each module.

Module-11
a. Explain the typical design flow with verilog HDL for designing VLSI IC. (10 Marks)
b. What is Instance and Instantiation? Explain with suitable éxample. (10 Marks)

OR
2 a. Taking D_FF as an instance, write a verilog code for D-Flip flop for Synchronous Reset.
(05 Marks)
b. Compare top-down and bottom-up design methodology. (07 Marks)
c. Explain design hierarchy using 4-bit ripplecàrry counter. (08 Marks)
+

Module-2 (02 Marks)

3 a. Explain the lexical convention "X/Z values".
b. Explain how ports are connected to extemal signals. (08 Marks)
c. Define the following data type with example :
) Nets (ii) Registers iii) Vectors Gv)Array (v) Parameter. (10 Marks)

OR
a. Explain the usage of'define and include compiler directives. (05 Marks)
With a generalized example, explain the components of verilog module. (07 Marks)
C.
Write a verilog code to implement the sequential circuit shown below in Fig.Q4(c). Write
stimulus for the same.

Sbor(3
bar

Fig.04(c) (08 Marks)

Module-3
5 a. Design a gate level module according to the logic diagram given in Fig.Q5(a). Write
stimulus.

oust .5)+¢

Fig.Q5(a) (05 Marks)

b. Define the terms: Rise, Fall and Turn off delays. (05 Marks)
Write the blook diagram, gate level logic diagram of a 4:1 multiplexer. Write a verilog code
C.
for the same using gate level logic description. Write stimulus. (10 Marks)

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OR
6 a. What are the output for the following instructions
i) Y=1X;X =4'b1010
(i) Y = X<<1; X=4'b0101
(ii) Y ={B, C, 2'b11}; B=4'b0010 , C-4bl101

(iv) Y {4{A}, 3{B}}; A= 1'bl, B=2'b011

=

(v) Y = A+B; A =4'b1010, B=4'b1110 (05 Marks)

b. Write the truth table for all Bitwise operator. (05 Marks)
c. Develop a gate level verilog code for 4-bit ripple carry adder from 1-bit full adder. What is
the out if A=0110 B 1110 and Cin0 att = 0 (10 Marks)

Module-4
7 . Explain how the initialand always statements are declared and used in verilog code
(10 Marks)
b. Explain Non blocking statement. Mention one application example. (10 Marks)

OR
8 a. With an example and formal syntax definition. Explain conditional 'if 'else' statements.
(05 Marks)
b. Design a 4:2 priority encoder with i3, i2, ii and io as inputs and y1 yo are outputs. If is is 1
output shall be 11, iz is I output shall be 10, i is l output shall be 01 and io is 1 output shall
be 00; by default let output be 00 (05 Marks)
c. Explain the foliowing loops with example:
i) FOR LOOP (i) FOREVER LOOP(i) WHILE LOOP (10 Marks)

Module-55
9 a. Write a VHDL code to implement 4-bif equality comparator using Behavioral description.
(04 Marks)
b. Explain the integer type, physical type and aray data types in VHDL. (06 Marks)
c. With a neat tool flow diagram, explain design tool flow. (10 Marks)

OR
10 a. Explain the following modes of ports :
IN i) oUT i ) BUFFER v) INPUT. (08 Marks)
b Explain what are signals and constants. How are they declared and used in VHDL code?
(05 Marks)
Write a short note on Attributes in VHDL. (07 Marks)

*****

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