Fixing Double Patterning Violations

With Look-Ahead

Sambuddha Bhattacharya
Subramanian Rajagopalan
Shabbir Batterywala
21st January, 2014

© 2014 Synopsys. All rights reserved. 1

Introduction
Double Patterning Technology (DPT) must at 20nm
and below
• Shapes assigned to two masks
• Shapes on same mask must have large separation

Mask assignment can have conflicts (DPT conflicts)

• Conflicts expressed as odd cycles
• Need to resolve conflicts for manufacturing
• Resolve by decomposition or legalization

s3 s3 s3
s3 s3
s s1 s1
s31 s2 s2 s2

Decomposition < DPT spacing Legalization

 Fixing DPT Conflicts: Approaches
• Layout Decomposition
– optimal stitch insertion * s3

– Overlap problem s
s31 s2

• Layout Legalization Decomposition

– Increased spacing
– Apt during early layout creation s3

• Combined Decomposition and Legalization s

s31 s2

– Simultaneous stitching and spacing # Decomposition Issue

– Stitching followed by legalization @

• This work address some issues in legalization method
– Prevents new DRC creation
– Avoids new DPT conflict creation
* Tang et al, “Optimal layout decomposition for double patterning technology,” ICCAD 2011
# Yuan et al, “Wisdom: Wire-spreading enhanced decomposition of masks in double patterning lithography,” ICCAD 2010.
@ Ghaida et al, “Layout decomposition and legalization for double-patterning technology,” TCAD Feb 2013.
Challenges in Legalization Methods

S1 S3

s1 s2 s3
S2

< DPT spacing

s1 s2 s3 s1 s2 s3

Alt 1: Move s2 down Alt 2: Move s2 leftwards

Need to carefully select location for increasing spacing

Layout Legalization: Flow and Model

y7 y8 WSP
Input Layout y6 x6 x4 x7
x1 x2 y5
x3 s2 x5 WSP
s1 s3 GCX
y4
Constraint Generation y3 x7 x8 x6

y1 x4 y2 x7  x4  wSP , x7  x6  wsp
< spacing
Resolve Infeasibility in
Constraint Graph x7  x4  wSP , x7  x6  wSP

Solve LP min CT x
subject to : Ax  b
Output Layout with constraint of form: xi  x j  bk

Framework to modify layouts in a design-rule aware way

Layout Legalization in Presence of DPT
WDPT
Input Layout x4 x7
S1 S3
WDPT
GCX
Construct DPT Graph x6 S2

x7  x4  wDPT , x7  x6  wDPT

Constraint Generation y7 y8 x7  x4  wDPT , x7  x6  wDPT

y6 x6
x1 x2 y5 OR
Resolve Infeasibility in s1 x3 s2 x5
y4
s3 y6  y5  wDPT
Constraint Graph y3 x7 x8 OR
x4 y2
x7  x5  wDPT
y1
< DPT spacing
Solve LP
min CT x
subject to : Ax  b
Output Layout
with constraint of form: xi  x j  bij
And additional relation across rows
{ xi  xconstraints
Method to apply large spacing j  bij xk  break
OR and xl  bklodd
} cycles
Possible Iterative Approach

Input Layout
s1 s2 s3 s1 s3
s2
Construct DPT Graph

< DPT spacing Alt 1: Move s2 down Constraint Generation

Layout changes may create new conflicts

New DPTs
Constraint Resolution
considering DPT and DRC

Issues with this approach Solve LP

• Can hop across bad solutions Output Layout

• Longer runtimes

Need a way to up-front know ‘good’ and ‘bad’ modifications

 Look-Ahead Approach

Input Layout Add DPT edges

remove DPT edges

Construct DPT Graph

GC GD
Estimate spacing shrinkage
Constraint Generation Update DPT Graph

Check Feasibility
New DPTs
Constraint Resolution considering Has Odd
DPT and DRC Cycles?
Update Constraints No
Yes
Solve LP Additional constraints
Feasible constraint
set to Solver
Output Layout

Replaced external iterations. Predict spacing shrinkage

Graph Interactions
Feasibility Bicolorability

Constraint Graph DPT Graph

Edge to add
and remove

Where to apply
larger spacing

GC checks if constraints solvable GD Checks if bipartite

Many edges map to one in GD One edge maps to many in GC
Provides info on potential DPT edge Feeds back set of large spacings
Produces a virtual layout instance Checks if virtual instance is bi-colorable

Feedback scheme to tighten constraints to meet DPT requirements

Predicting Spacing Shrinkage
• Run modified Bellman-Ford UB
algorithm *
– Initialize constraint graph nodes with src
input layout locations
– In Forward run, update if ‘relaxed’ to
value above input layout position snk
LB
– Forward run produces upper bound
– In reverse run, update if ‘relaxed’ to a
Input position
value below input layout position
– Reverse run produces lower bound

LB1 UB1 LB2 UB2

• Potential DPT if :
∆𝑈𝐵 ≤ 𝐷𝑃𝑇 ∨ ∆𝐿𝐵 ≤ 𝐷𝑃𝑇 𝑎𝑛𝑑 ∆𝐿𝑌𝑇 ≥ 𝐷𝑃𝑇

* Salodkar et al, “Automatic Design Rule Correction in Presence of Multiple Grids and Track Patterns”, DAC 2013
Results
Expt. #Lyt obj #Nodes #Edges Input Input Output Output Runtime
DPT DRC DPT DRC
1 634 2513 14840 150 182 0 0 0.45 s
2 1354 5393 32257 330 370 0 0 1.49 s
3 1854 7173 41206 459 529 1 4 4.86 s
4 2654 9953 59594 635 750 40 100 5.87 s
5 3946 13749 80391 854 1066 40 19 12.83 s

Expt. Simple Legalization Look-ahead Legalization

Output DPT Output DRC Output DPT Output DRC
1 30 0 0 0
2 70 0 0 0
3 115 4 1 4
4 170 100 40 100
5 234 19 40 19

Look-ahead
In Simple helps
Legalization, fix new
many many more
DPTs DPT conflicts
conflicts got introduced
Conclusions

• Proposed a method to fix DPT conflicts

– Based on legalization

• Looks ahead to
– Avoid creating new DPT conflicts
– Avoid creating DRC violations

Thank You