Scribd
Upload
28 views

Pe Report: Power Report of Our Sdram Controller On Basys3 Fpga

The document discusses power calculations and timing parameters for DDR4 SDRAM controllers. It summarizes two papers on calculating power consumption and implementing low-power SDRAM controllers. It also provides details on implementing an SDRAM controller on a Basys3 FPGA, including timing analysis and area overhead. Future work mentioned includes integrating techniques from another paper to improve speed.

Uploaded by

jurair bhat
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
28 views

Pe Report: Power Report of Our Sdram Controller On Basys3 Fpga

The document discusses power calculations and timing parameters for DDR4 SDRAM controllers. It summarizes two papers on calculating power consumption and implementing low-power SDRAM controllers. It also provides details on implementing an SDRAM controller on a Basys3 FPGA, including timing analysis and area overhead. Future work mentioned includes integrating techniques from another paper to improve speed.

Uploaded by

jurair bhat
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 7

PE REPORT

POWER REPORT OF OUR SDRAM CONTROLLER ON BASYS3 FPGA:


When it comes modern day DDR4 SDRAMs, there are certain formulas or
calculators that are used to calculate power- both Standby power and Active
power. Since, there are a lot of formulas for calculation power consumption
depending upon the power supply. All memory systems have separate Power
Distribution System (Pds) and various models for it known as Power Distribution
System Planning (Pdsp) models. The following paper by Micron gives a detailed
explanation as to how to calculate power for a DDR4 memory system based on
different power supplies, active & standby modes and also based on different
modes of operation (Read/ Write).

https://www.micron.com/-/media/client/global/documents/products/technical-
note/dram/tn4007_ddr4_power_calculation.pdf

Another paper, which implements a SDRAM Controller, specially designed for


low-power consumption, on Cadence tool set, can be looked into if in future the
focus is towards reducing power consumption. Various low power techniques
such as Clock Gating and Multi-level Vdd have been used in this design. These low
power techniques can be used with less difficulty in ASIC flow rather than FPGA
flow.

https://www.researchgate.net/publication/311417552_A_Low_Power_DDR_SDR
AM_Controller_Design
STA (STATIC TIMING ANALYSIS) INFORMATION OF OUR DESIGN AFTER
IMPLEMENTATION:

As it can be seen from above snapshot of Xilinx Vivado’s timing summary after the
Implementation step, there is only Negative Slack and that means there is no
timing violation in our SDRAM Controller design.
SCHEMATIC OF OUR SDRAM CONTROLLER DESIGN ON FPGA AFTER
IMPLEMENTATION:
AREA OVERHEAD OF IMPLEMENTED SDRAM CONTROLLER:

Not a lot of information is available when it comes to area overhead of a SDRAM


Controller as most of the online documents give information regarding ASIC
application of a SDRAM Controller and not FPGA application.

Timing Parameter of SDRAM :

CAS Latency (CL) : CAS Latency (Column Access Strobe Latency), also known as
“Access Time”, is the most important memory parameter and is the first of the
series of numbers. It is the delay time between the moment a memory controller
tells the memory module to access a particular memory column on a RAM
memory module, and the moment the data from given array location is available
on the module's output pins. In DDR SDRAM it is specified in clock cycles, while in
asynchronous DRAM it is specified in nanoseconds.

RAS to CAS Delay (tRCD): ‘tRCD’ stands for row address to column address delay
time. Inside the memory, the process of accessing the stored data is accomplished
by first activating the row then the column where it is located. tRCD is the time
required between the memory controller asserting a row address strobe (RAS),
and then asserting a column address strobe (CAS) during the subsequent read or
rite command. The lesser this time, the better it is, as the data will be read
sooner.
RAS Precharge (tRP): Whenever a new row is to be activated for the purpose of
accessing a data bit, a command called “Precharge” needs to be issued to close
the already activated row. RAS Precharge time, tRP is the number of clock cycles
needed to terminate access to an open row of memory, and open access to the
next row.

Active to Precharge Delay (tRAS): After an “Active” command is issued, another


“Precharge” command cannot be issued until tRAS has elapsed. So, tRAS is the
minimum

Memory I/O bus Data CAS


Standard Timings
clock clock rate latency
name CL-tRCD-tRP
(MHz) (MHz) (MT/s)[c] (ns)

DDR4-1600J* 10-10-10 12.5


DDR4-1600K 200 800 1600 11-11-11 13.75
DDR4-1600L 12-12-12 15

DDR4-1866L* 12-12-12 12.857


DDR4-1866M 233.33 933.33 1866.67 13-13-13 13.929
DDR4-1866N 14-14-14 15

DDR4-2133N* 14-14-14 13.125


DDR4-2133P 266.67 1066.67 2133.33 15-15-15 14.063
DDR4-2133R 16-16-16 15

DDR4-2400P* 15-15-15 12.5


DDR4-2400R 16-16-16 13.32
300 1200 2400
DDR4-2400T 17-17-17 14.16
DDR4-2400U 18-18-18 15

DDR4-2666T 17-17-17 12.75


DDR4-2666U 18-18-18 13.50
333.33 1333.33 2666.67
DDR4-2666V 19-19-19 14.25
DDR4-2666W 20-20-20 15

DDR4-2933V 19-19-19 12.96


DDR4-2933W 20-20-20 13.64
366.67 1466.67 2933.33
DDR4-2933Y 21-21-21 14.32
DDR4-2933AA 22-22-22 15

DDR4-3200W 20-20-20 12.5


DDR4-3200AA 400 1600 3200 22-22-22 13.75
DDR4-3200AC 24-24-24 15
FUTURE WORK:

This paper implements a more advanced and improved SDRAM Controller on


FPGA with improved read/write latencies and the area overhead is also quite
reasonable. The SDRAM Controller described in the paper can be taken up as
future work and some of the design ideas could be integrated with our design for
better speed.

https://www.researchgate.net/publication/269711137_Design_and_Implementa
tion_of_SDRAM_Controller_in_FPGAs

You might also like