ENEE 359a

Lecture/s 3-5
Transistors &
CMOS Inverter

Bruce Jacob ENEE 359a

University of
Maryland
Digital VLSI Circuits
ECE Dept.

SLIDE 1

P/N Junction, MOS Transistors,

CMOS Inverter
Prof. Bruce Jacob
[email protected]

Credit where credit is due:

Slides contain original artwork (© Jacob 2004) as well as material taken liberally
from Irwin & Vijay’s CSE477 slides (PSU), Schmit & Strojwas’s 18-322 slides
(CMU), Wolf’s slides for Modern VLSI Design, and/or Rabaey’s slides (UCB).
Device physics: http://hyperphysics.phy-astr.gsu.edu/hbase/solids/sselcn.html
UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Overview
Bruce Jacob

University of
• Electrons & holes, bands & band gaps,
Maryland
ECE Dept.
insulators, conductors, semiconductors
SLIDE 2 • Silicon crystal lattice & doping
• P/N junction & parasitic capacitance
• n-type/n-channel MOSFET
• Timing analysis of MOSFET, capacitance
• Body effect, series-connected FETs
• CMOS inverter: timing, switching
threshold, transistor sizing
• Dynamic behavior (preview)

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter What Is Conductivity?
Bruce Jacob

University of
Perspective from Band Theory of Solids:
Maryland
ECE Dept. Large band gap (not “Gap Band”) between
valence and conduction bands in insulator
SLIDE 3 material suggests that, at ordinary
temperatures, no electrons can reach
Energy of electrons conduction band (i.e. material won’t conduct)

In semiconductors, the band gap is small

enough that thermal energy can bridge gap for
Conduction Band small fraction of electrons.
In conductors, there is no band gap
(conduction and valence bands overlap).

INSULATOR SEMICONDUCTOR CONDUCTOR

Fermi level
Fermi level

Conduction Band

Conduction Band
Valence Band Valence Band Valence Band

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Silicon, Specifically
Bruce Jacob

University of
Maryland
ECE Dept.

SLIDE 4

Si

14 protons in nucleus
4 valence electrons

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Silicon, Specifically
Bruce Jacob

University of
Maryland
ECE Dept.
Si
SLIDE 5

Si Si Si

Shared electrons
of covalent bonds Si

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Silicon, Specifically
Bruce Jacob

University of
Silicon Lattice (artistic license exploited)
Maryland
ECE Dept.
Si Si Si Si Si
SLIDE 6

Si Si Si Si Si

Si Si Si Si Si

Si Si Si Si Si

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Silicon, Specifically
Bruce Jacob

University of
Silicon Lattice — It is a semiconductor
Maryland
ECE Dept.
Si Si Si Si Si
SLIDE 7

Si Si Si Si Si

Si Si Si Si Si

Hole

Si Si Si SiFree Si
electron

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Silicon, Specifically
Bruce Jacob

University of
Semiconductor current: electron/hole flow
Maryland
ECE Dept.

SLIDE 8

Si Si Si Si

Si Si Si Si

Si Si Si Si

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Silicon, Specifically
Bruce Jacob

University of
Perspective from Band Theory of Solids:
Maryland
ECE Dept.

SLIDE 9 Energy of electrons

0K 300K
(no electrons in conduction band)

Conduction Band Free Conduction Band

electrons
Fermi level
1.09 eV

Valence Band Holes Valence Band

• Conductivity is non-zero; mobile electrons/holes in

conduction/valence band; can be increased w/ doping
UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Silicon, Specifically
Bruce Jacob

University of
Doping: small % of foreign atoms in lattice
Maryland
ECE Dept.

SLIDE 10

P B

Breaks up regular lattice, produces

dramatic changes in electrical properties
• Donors: pentavalent impurities (5 valence electrons)
produce n-type semiconductors by adding electrons.
E.g. antimony, arsenic, phosphorus
• Acceptors: trivalent impurities (3 valence electrons)
produce p-type semiconductors by adding electron
deficiencies (“holes”). E.g. boron, aluminum, gallium
UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter P-Type Semiconductor
Bruce Jacob

University of Acceptor impurity

Maryland Si creates a hole
ECE Dept.

SLIDE 11

Si B Si

Conduction Band
Si
Extra hole energy levels

Valence Band

Addition of acceptor impurities contributes hole energy levels low in the semiconductor band
gap so that electrons can be easily excited from the valence band into these levels, leaving
mobile holes in the valence band. This shifts the effective Fermi level to a point about halfway
between the acceptor levels and the valence band. Electrons can be elevated from the
valence band to the holes in the band gap with the energy provided by an applied voltage.
Since electrons can be exchanged between the holes, the holes are said to be mobile. Holes
are said to be the “majority carriers” for current flow in a p-type semiconductor.
UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter N-Type Semiconductor
Bruce Jacob

University of
Maryland Si
ECE Dept. Donor impurity
creates free electron
SLIDE 12

Si P Si

Conduction Band
Si

Extra electron energy levels

Valence Band

Addition of donor impurities contributes electron energy levels high in the semiconductor band
gap so that electrons can be easily excited into the conduction band. This shifts the Fermi
level to a point about halfway between the donor levels and the conduction band. Electrons
can be elevated to the conduction band with the energy provided by an applied voltage and
move through the material. Electrons are said to be the “majority carriers” for current flow in an
n-type semiconductor.

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter One Way to Think About It
Bruce Jacob
Acceptor side Donor side
University of
Maryland
ECE Dept.
Conduction Band Conduction Band
SLIDE 13
Extra hole energy levels
Extra electron energy levels

Valence Band Valence Band

P-type N-type

• P-type: Conduction band is pulled down close to the

valence band by the creation of available holes (willing
acceptors of free electrons)
• N-type: Valence band is pushed up close to the
conduction band by the addition of mobile electrons

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter The P/N Junction
Bruce Jacob
Acceptor side Donor side
University of
Maryland
ECE Dept.
Conduction Band Conduction Band
SLIDE 14
Extra hole energy levels
Extra electron energy levels

Valence Band Valence Band

P-type N-type

• P-type: extra holes in band gap allow excitation of

valence-band electrons, leaving mobile holes in
valence band
• N-type: electron energy levels near the top of the band
gap allow easy excitation of electrons into conduction
band

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter The P/N Junction
Bruce Jacob
Acceptor side
University of
Maryland
ECE Dept.
Conduction Band
Donor side
SLIDE 15
Extra hole energy levels
Conduction Band

Extra electron energy levels

Valence Band

Valence Band

Diode

P-type N-type
silicon silicon

p-n junction

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter The P/N Junction
Bruce Jacob

University of
DEPLETION REGION
Maryland
ECE Dept.

SLIDE 16

If not touching, nothing happens

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter The P/N Junction
Bruce Jacob

University of
DEPLETION REGION
Maryland
ECE Dept.

SLIDE 17

With a connection, electrons from n-region

in conduction band diffuse across junction
and combine with holes in p-region

(why doesn’t this continue indefinitely?)

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter The P/N Junction
Bruce Jacob

University of
DEPLETION REGION
Maryland Negative Positive
ECE Dept. ion ion
SLIDE 18

Mobile Mobile
hole electron
depletion region

Ions are formed on both sides of junction

(negative ion from filled hole; positive ion
from removed electron). This forms a space
charge that impedes further electron flow.
UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter The P/N Junction
Bruce Jacob

University of
DEPLETION REGION
Maryland
ECE Dept.

SLIDE 19

two plates of
a capacitor
Cj
Parasitic capacitance: Built-in junction potential:
C j0  N A N D
C j = ------------------------
- φ 0 = φ T ⋅ ln ----------------
Vd m  n2 
i
1 – ------
φ0
UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter The P/N Junction
Bruce Jacob

University of
BIAS EFFECT on DEPLETION REGION
Maryland
ECE Dept.

SLIDE 20
Equilibrium

P N
depletion region

Conduction Band
Extra hole energy levels
Conduction Band

Valence Band Extra electron energy levels

Valence Band

• Upward = increased electron energy (must supply

energy to make electron go up or hole to go down)
• Drift-diffusion equilibrium (current is flowing)
UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter The P/N Junction
Bruce Jacob

University of
BIAS EFFECT on DEPLETION REGION
Maryland
ECE Dept.

SLIDE 21
Forward Bias

P N
depletion region still exists

Conduction Band
Conduction Band
Extra hole energy levels

Extra electron energy levels

Valence Band
Valence Band

P-side is made more positive relative to N-side, making it “downhill” to move an electron
across the junction. Electron on N-side can fill a vacancy (“hole”) on P-side & move from
hole to hole to the left to positive terminal (hole “moves” right).

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter The P/N Junction
Bruce Jacob

University of
BIAS EFFECT on DEPLETION REGION
Maryland
ECE Dept.

SLIDE 22
Reverse Bias

P N
depletion region increases in size
until new potential = applied bias

Conduction Band
Extra hole energy levels

Valence Band
Conduction Band
P-side is made more negative relative
to N-side, making it “uphill” to move an
electron across the junction. Applied
voltage impedes the flow of N-region Extra electron energy levels
electrons across the p/n junction. Initial
transient electron flow is left to right; it
stops when potential (widening depletion Valence Band
region) equals the applied voltage.
UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter MOS Transistors
Bruce Jacob
MOS Transistor, reverse-biased:
University of
Maryland
ECE Dept.

SLIDE 23

PN N-Doped
Junction Region
[mobile electrons]

P-Doped
Region
n [mobile holes]

p-doped semiconductor substrate

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter MOS Transistors
Bruce Jacob
MOS Transistor, reverse-biased:
University of
Maryland
ECE Dept.

SLIDE 24
VDD VDD
N-Doped
P-Doped
Regions
Region
[donor electrons]
[acceptor holes]

VSS
n n

p-doped semiconductor substrate

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter MOS Transistors
Bruce Jacob
MOS Transistor, reverse-biased:
University of
Maryland
ECE Dept.

SLIDE 25
VDD VDD
Insulator
(gate oxide)

VSS
n n

p-doped semiconductor substrate

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter MOS Transistors
Bruce Jacob
NMOS Transistor with gate:
University of
Maryland
ECE Dept.
0
SLIDE 26
+ +
Conductor

Insulator
(gate oxide)

0
n n

p-doped semiconductor substrate

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter MOS Transistors
Bruce Jacob
NMOS Transistor with bias voltages:
University of
Maryland
ECE Dept.
0
SLIDE 27
0 +
Conductor

Insulator
(gate oxide)

0
n n

p-doped semiconductor substrate

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter MOS Transistors
Bruce Jacob
NMOS Transistor with bias voltages:
University of
Maryland
ECE Dept.
+
SLIDE 28
0 +
Gate
(conductor)
Insulator
(gate oxide)

0
n n
CURRENT

p-doped semiconductor substrate

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter MOS Transistors
Bruce Jacob
NMOS Transistor, two views:
University of
Maryland
ECE Dept. Length
SLIDE 29

Width

TOP
VIEW

Gate Gate oxide

FOX FOX
n n
SIDE
VIEW p-doped semiconductor substrate
UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter MOS Transistors
Bruce Jacob
NMOS Transistor with bias voltages:
University of Gate
Maryland
ECE Dept. Source Drain

SLIDE 30

VSS
n channel n

p-doped semiconductor substrate

Gate Gate
Source Drain Source Drain
0 0 0 V>0
V>0 V>0

Electron Flow

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter MOS Transistors
Bruce Jacob
PMOS Transistor with bias voltages:
University of Gate
Maryland
ECE Dept. Drain Source

SLIDE 31

VDD
p channel p

n-doped semiconductor substrate

Gate Gate
Drain Source Drain Source
0 VDD 0 V<VDD
V>0 V>0

Electron Flow

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter MOS Transistors
Bruce Jacob
MOS Transistors:
University of Gate Gate
Maryland
ECE Dept. Source Drain Source Drain

SLIDE 32

VSS VDD
n channel n p channel p

p-doped semiconductor substrate n-doped semiconductor substrate

NMOS PMOS
Gate Gate

Source Drain Source Drain

Substrate Substrate

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter 0.25 µm transistor (Bell Labs)
Bruce Jacob

University of
Maryland
ECE Dept.

SLIDE 33 Silicide

Poly
Gate
oxide

Source & Drain

Poly+silicide = “polycide gate” (lower R)

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter MOS Behavior
Bruce Jacob VSource VGate VDrain

University of Gate
Maryland
ECE Dept.

SLIDE 34
n+ n+

p (bulk) Depletion Regions

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter MOS Behavior
Bruce Jacob VSource VGate VDrain

University of Gate
Maryland
ECE Dept.

SLIDE 35
n+ n+

p (bulk) Depletion Regions

VS = 0V VG = 0.5V VD = 0V
Charge Density
Gate

Oxide

Substrate Depletion layer

(p-type)
x (depth)
UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter MOS Behavior
Bruce Jacob VSource Channel VGate VDrain
Free electrons
University of Gate
Maryland
ECE Dept.

SLIDE 36
n+ n+

Depletion Inversion Layer

Regions Assume VT = 0.75V
forms when
p (bulk) (threshold voltage)
VGS > VT

VS = 0V VG = 1V VD = 0V
Charge Density
Gate

Oxide Inversion layer

Substrate Depletion layer

(p-type)
x (depth)
UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter MOS Behavior: linear region
Bruce Jacob VSource VGate VDrain

University of Gate
Maryland
ECE Dept.

SLIDE 37
n+ n+

Inversion Layer Assume VT = 0.75V

existence requires
p (bulk) VGS – VT > V(y) (threshold voltage)

VS = 0V VG = 1V VD = 0.001V
ε ox  W 
dielectric constant
electron mobility
I DS = µ n ------- ----- ( V GS – V T )V DS
t ox  L 
oxide thickness
V(y) VGS – V(y)
1V

0.75V
VDS
y (channel) y (channel)

True when VGS > VT & VDS << VGS – VT

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter MOS Behavior: ‘linear’ region
Bruce Jacob VSource VGate VDrain

University of Gate
Maryland
ECE Dept.

SLIDE 38
n+ n+

Inversion Layer Assume VT = 0.75V

existence requires
p (bulk) VGS – VT > V(y) (threshold voltage)

VS = 0V VG = 1V VD = 0.15V
electron mobility ε ox W
dielectric constant

I DS = µ n -------  ----- ( V GS – V T )V DS – --- V DS

1 2
t ox  L  2
oxide thickness
V(y) VGS – V(y)
VDS 1V
0.85V
0.75V
y (channel) y (channel)

True when VGS > VT & VDS ≤ VGS – VT

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter MOS Behavior: saturation
Bruce Jacob VSource VGate VDrain

University of Gate
Maryland
ECE Dept.

SLIDE 39
n+ n+

Inversion Layer Assume VT = 0.75V

“pinched off” when
(threshold voltage)
p (bulk) VDS = VGS – VT

VS = 0V VG = 1V VD = 0.25V
1  ε ox  W   2
I DS = --- µ n ------- ----- ( V GS – V T )
2  t ox  L  
V(y) VGS – V(y)
VDS 1V

0.75V
y (channel) y (channel)

True when VGS > VT & VDS = VGS – VT

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter MOS Behavior: modulation
Bruce Jacob VSource VGate VDrain

University of Gate
Maryland
ECE Dept.

SLIDE 40
n+ n+

Inversion Layer Assume VT = 0.75V

does not exist here (threshold voltage)
p (bulk) VDS ≥ VGS – VT

VS = 0V VG = 1V VD = 0.35V
1  ε ox  W   2
I DS = --
- µ ------
- ----
- ( V – V T ) ( 1 + λ V DS )
2  n t ox  L   GS
length modulation factor
V(y) VGS – V(y)
effective channel length decreases over this range, effective gate potential
VDS 1V is not sufficient to create inversion layer

0.75V
0.65V
y (channel) y (channel)

True when VGS > VT & VDS ≥ VGS – VT

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Example of Drain Current
Bruce Jacob

University of
Values for generic 0.5 µm process:
Maryland
ECE Dept. ε ox
k’ (transconductance) = µ n ------- VT
SLIDE 41 t ox

n-type k’n = 73 µA/V2 0.7V

p-type k’p = 21 µA/V2 -0.8V

Assume W/L = 3/2, VGS = 2V, find IDS for

NMOS device at saturation point:

I DS = ---  k' ----- ( V GS – V T )

1 W 2
2 L 
µA 3
I DS = ---  73 -------2   --- ( 2V – 0.7V ) = 93µA
1 2
2  V   2
UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter NMOS I-V Plot
Bruce Jacob

University of X 10-4
Maryland 2.5
ECE Dept. VGS = 2.5V
SLIDE 42 2

Linear dependence
VGS = 2.0V
1.5
ID (A)
1 VGS = 1.5V

0.5 VGS = 1.0V

0
0 0.5 1 1.5 2 2.5
VDS (V)
NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter PMOS I-V Plot
Bruce Jacob l All polarities of all voltages and currents are reversed
University of -2 VDS (V) -1 0
Maryland
ECE Dept. 0

SLIDE 43
VGS = -1.0V -0.2

VGS = -1.5V -0.4

ID (A)
-0.6
VGS = -2.0V
-0.8

VGS = -2.5V
-1 X 10-4

PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V

Note y-axis scale (because W/Lp = W/Ln)

(drive current: ID when VGS = VDS = VDD)
UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Review: RC Circuits
Bruce Jacob
VC = ?
University of
Maryland R vc(t)
ECE Dept.

SLIDE 44
V C

–t ⁄ τ
v out(t) = ( 1 – e )V τ = RC

RC time-constant: dictates how rapidly the

output voltage reacts to the voltage rise on
input (step function).
Larger RC, slower response

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Capacitances
Bruce Jacob VSource VGate VDrain

University of Gate
Maryland
ECE Dept.

SLIDE 45
n+ n+
Gate is
capacitor
p (bulk)
Depletion Regions are capacitors
WLε ox Aε si I ⋅ τc
C gate = ----------------- C SC = ---------- C diff = -----------
t ox t si V th

Yes, there are others …

Result: parasitic capacitances hinder

switching speeds

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Body Effect
Bruce Jacob VSource > 0 VGate VDrain

University of Gate
Maryland
ECE Dept.

SLIDE 46
n+ n+

p (bulk/body)

• Suppose source and body are not in equilibrium:

reverse bias increases size of depletion region around
that diode (and changes its parasitic capacitance)
• Called “body effect” … it changes the threshold
voltage for that device
2qε si N A
∆V t = ------------------------- ( φ S + V SB – φ S )
C ox

But can it happen?

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Body Effect
Bruce Jacob
NAND gate
University of
Maryland
ECE Dept. VDD
SLIDE 47
A B

output
A #A
GNDeffective for #A
B #B

• If #B propagates signal in non-zero time, the effective

source voltage for #A can go positive (higher than
ground)
• Perspective: Things start to get interesting
when you start connecting these things together …
UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter CMOS Inverter Layout I
Bruce Jacob

University of
Maryland
ECE Dept.

SLIDE 48

N-regions for Gate P-regions and gate

source, drain (poly) for PMOS device

input

GND VDD
NMOS output PMOS

N-Well

Cut line

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter CMOS Inverter Layout II
Bruce Jacob

University of VDD
Maryland
ECE Dept. +
SLIDE 49

tub ties
a out transistors
a out

GND

Another view (note: wells/tubs not shown)

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter CMOS Inverter: Analysis
VDD
Bruce Jacob

University of Rp
Maryland
ECE Dept.

SLIDE 50
VDD Vin = 0
CL
Rp
Vout
VDD

CL (load)
Rn
Vin = VDD
CL
Rn

• Gate response time is determined by the time to

charge CL through Rp or discharge CL through Rn
UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter CMOS Inverter: Transfer Plot
Bruce Jacob NMOS off
PMOS res
University of 2.5
Maryland NMOS sat
ECE Dept. PMOS res
SLIDE 51 2

Vout (V) 1.5 NMOS sat

PMOS sat
1

0.5 NMOS res

PMOS sat NMOS res
PMOS off
0
0 0.5 1 1.5 2 2.5

Vin (V)

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter CMOS Inverter: Current
Bruce Jacob NMOS off
PMOS res
University of 2.5
Maryland NMOS sat
ECE Dept. PMOS res
SLIDE 52 2

Vout (V) 1.5 NMOS sat

PMOS sat
1

0.5 NMOS res

PMOS sat NMOS res
PMOS off
0
0 0.5 1 1.5 2 2.5

Vin (V)

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Properties of CMOS
Bruce Jacob

University of
• Full rail-to-rail swing -> high noise
Maryland
ECE Dept.
margins
SLIDE 53
• Logic levels not dependent upon the relative device
sizes -> transistors can be minimum size -> ratioless
• Always a path to Vdd or GND in steady state -> low
output impedance (output resistance in kΩ Ω range) ->
large fan-out (albeit with degraded performance)
• Extremely high input resistance (gate of MOS
transistor is near perfect insulator) -> nearly zero
steady-state input current

• No direct path steady-state between

power and ground -> no static power
dissipation
• Propagation delay function of load
capacitance and resistance of
UNIVERSITY OF MARYLAND
transistors
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Capacitive Load, etc.
Bruce Jacob

University of
Maryland
ECE Dept.

SLIDE 54

Fan-out
Fan-in

Fan-out: number of gates connected to the

output of the driving date
• Gates with large fan-out are slower

Fan-in: the number of inuts to the gate

• Gates with large fan-in are bigger and slower

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Aside:is capacitance all bad?
Bruce Jacob
Slows down output … Bigger capacitor,
University of more charge to
Maryland change voltage
ECE Dept. => SLOWER
SLIDE 55

… but stabilizes power supply

Bigger capacitor,
more charge to
change voltage
=> more stable
power-supply
voltage levels

Capacitors are de facto frequency filters …

can be a good thing (“bypass caps”)
UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Transistor Sizing I
Bruce Jacob

University of W 2W
Maryland
ECE Dept.
L L
SLIDE 56 Source
Drain

L/Wmin (R1,C1) (R2,C2)

The electrical characteristics of transistors

determine the switching speed of a circuit
• Need to select the aspect ratios (W/L)n and (W/L)p of
every FET in the circuit

Define Unit Transistor (R1, C1)

• L/Wmin-> highest resistance
• R2= R1 ÷ 2 and C2= 2 • C1
• Separate nFET and pFET unit transistors

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Long MOSFETs
Bruce Jacob poly Short S Long S
University of metal
Maryland
ECE Dept.
active
SLIDE 57
G G
n-well

via D
D
S

G
Really Long
D
UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Wide MOSFETs
Bruce Jacob poly Narrow S Wide S

University of metal
Maryland
ECE Dept.
active G G
SLIDE 58

n-well

via G D D

Really Wide D
UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Transistor Sizing II
Bruce Jacob

University of
Resistance of MOSFET:
Maryland
ECE Dept.
1  L
R n = ---------------------------------------------- -----
µ n C ox ( V GS – V Tn )  W 
SLIDE 59

• Increasing W decreases the resistance;

allows more current to flow

Oxide capacitance C ox = ε ox ⁄ t ox [F/cm2]

Gate capacitance C G = C ox WL [F]

Transconductance β n = µ n C ox  ----- = k' n  -----

W W
 L  L

(units [A/V2])

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Transistor Sizing II
Bruce Jacob

University of
nFET vs. pFET
Maryland
ECE Dept.
1
R n = -------------------------------------  W
β n = µ n C ox -----
SLIDE 60
β n ( V DD – V Tn )  Ln

β p = µ p C ox  -----
1 W
R p = ----------------------------------------
β p ( V DD – V Tp )  Lp

µn
----- = r Typically
µp (2 .. 3)

(µ is the carrier mobility through device)

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Inverter Switching Point
Bruce Jacob

University of
Where Vin = Vout
Maryland
ECE Dept. NMOS off
PMOS res
SLIDE 61 2.5 NMOS sat
PMOS res
2

1.5
Vout (V)

NMOS sat
PMOS sat
1

0.5 NMOS res

PMOS sat NMOS res
PMOS off
0
0 0.5 1 1.5 2 2.5

Vin (V)
UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Inverter Switching Point
Bruce Jacob

University of
At all points IDSn = IDSp (drain currents)
Maryland
ECE Dept.
At switching point, Vin = Vout = Vsp
SLIDE 62

βn 2 βp 2
------ ( V SP – V Tn ) = ------ ( V DD – V SP – V Tp )
2 2
βn
------ ⋅ V Tn + ( V DD – V Tp )
βp
V SP = -------------------------------------------------------------
βn
1 + ------
βp

For Vsp = Vdd/2, assuming VTn= VTp,

ßn = ßp => Wp ≈ 2–3Wn
(equal drive currents, equal Reff: Rn = Rp)
UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter The Result (Wp = 2Wn, .25µm)
Bruce Jacob
In
University of
Maryland metal1-poly via
ECE Dept. metal1
polysilicon
SLIDE 63

metal2
VDD

pdiff
PMOS (4/.24 = 16/1)
NMOS (2/.24 = 8/1)
metal1-diff via

ndiff
GND
metal2-metal1 via

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter The Result II (Wp = 3Wn)
Bruce Jacob
VDD
University of
Maryland PMOS
ECE Dept.
1.125/0.25
SLIDE 64

1.2µm
=2λλ
Out
In
Metal1

Polysilicon

NMOS
0.375/0.25 GND

PMOS devices 3x larger than NMOS devices

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Delay Definitions
Bruce Jacob
Vin Vout
University of
Maryland Vin
ECE Dept. Propagation Delay
SLIDE 65
tp = (tpHL + tpLH) / 2

50%

Input
Waveform time
tpHL tpLH
Vout

90%

50%
Signal slopes

10%
Output
Waveform tf tr time
UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Inverter Switching Delay
Bruce Jacob
VDD VDD
University of
Maryland
ECE Dept. Rp
SLIDE 66 CL VOUT VOUT

CL CL
Rn

Charging: Vout rising Discharging: Vout falling

If (W/L)p = r(W/L)n then ßn = ßp

(and Rn = Rp)
… symmetric inverter
Make pFET bigger (wider) by factor of r

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Inverter Switching Delay
Bruce Jacob
VDD VDD
University of
Maryland
ECE Dept. Rp
SLIDE 67 CL VOUT VOUT

CL CL
Rn

Charging: Vout rising Discharging: Vout falling

tpLH = ln(2) Rp CL = 0.69 Rp CL

tpHL = ln(2) Rn CL = 0.69 Rn CL
tp = (tpHL + tpLH)/2 = 0.69 CL(Rn + Rp)/2
(note: the ln(2)RC term comes from first-order analysis of simple
RC circuit’s respose to step input ... time for output to reach 50% value)

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Inverter Pair
Bruce Jacob
VDD
University of
Maryland PMOS
ECE Dept.
1.125/0.25
SLIDE 68

1.2µm
=2λλ
Out
In
Metal1

Polysilicon

NMOS
0.375/0.25 GND

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Inverter Pair
Bruce Jacob
Vout
University of
Maryland
ECE Dept. Vout
SLIDE 69 2.5V
Vh
Vth

Vtl
Vl

Output
Waveform

UNIVERSITY OF MARYLAND
 ENEE 359a
Lecture/s 3-5
Transistors &
CMOS Inverter Dynamic Power Dissipation
Bruce Jacob

University of
VDD VDD
Maryland
ECE Dept. Rp
SLIDE 70 Ctot VOUT VOUT

CL CL
Rn

T Charging: Vout rising Discharging: Vout falling

Q Ctot V DD ⋅ C tot
I avg = ------------ = ------------------------
T T
2
C tot ⋅ V DD 2
P avg = V DD ⋅ I avg = ------------------------ = C tot ⋅ V DD ⋅ f CLK
T

UNIVERSITY OF MARYLAND