AN-948 (v.

Int)

Linear Power Amplifier Using Complementary HEXFETs®

(HEXFET is the trademark for International Rectifier Power MOSFETs)

Topics covered:
A description of the circuit
Performance
Power supply requirements
Set-up and troubleshooting
Performance summary
Related topics

The class AB amplifier described in this application note uses a complementary pair of HEXFET Power MOSFET devices as the
output stage. This feature offers performance improvements over the equivalent bipolar output stage and allows a reduction in the
complexity of the driver circuit, the output devices being driven by a single class A driver. At the time the work was done, logil
level HEXFET Power MOSFETs were not available and standard devices were used. The use of low-threshold devices would
simplify the bias circuit and reduce the quiescent power dissipation The design described will deliver 60W rms into a 4 ohm load
when working from +30V supplies. The bandwidth is in, excess of l00kHz, but may be tailored to the user requirements by
making component value changes.

1. CIRCUIT DESCRIPTION
The amplifier circuit diagram is shown in Figure 1, and the components listing in Table 1. Split power supply rails (±VDD) are
used, giving improved rejection of power supply ripple and allowing the load, Rload, to be direct coupled. The output devices Q5,
Q6 , operate in source follower configuration. This offers a twofold advantage; a) the possibility of oscillation in the power output
stage is reduced as the voltage gain is less than unity and b) signal feedback through the heatsink on which the devices are
assembled is eliminated as the drain terminal, which is electrically connected to the tab on the TO220 package, is at dc voltage.

Symmetrical output is achieved by providing "bootstrapped" drive to the gate of the n-channel device, Q5, from the output. The
use of the bootstrap circuit, C4, R8, R9 also allows the driver transistor, Q4, to operate at near constant current which improves
the linearity of the driver stage. The diode D1 acts as a clamp for the bootstrap circuit, restricting the positive voltage at the gate
of Q5 to +VDD. This allows symmetry to be maintained under overload conditions.

+ R4 + - VDD
C3 D1 C5
R8

C4
R3

+
Q5 L1
R9

R15

R11 R10
INPUT Q1 Q2
R1 R6 C7 RLOAD

C1
R12
R2

R7

Q3

+ C2 +
R13 C6
Q6
R14 Q4
R5

- VDD

Figure 1. Class AB Amplifier Circuit Diagram

 AN-948 (v.Int)

Transistor Q3 and resistors R11, R12, R13 provide gate-source offset voltage for the output devices. R12 is variable, allowing
adjustment of the output quiescent current for variation in HEXFET Power MOSFET threshold voltage. A degree of temperature
compensation is built into the circuit as both the bipolar transistor, Q3, emitter base voltage and the combined threshold voltages
of the HEXFET Power MOSFETs, Q5, Q6 have a temperature coefficient of -0.3%/°C.

Components List
R1 4.7KΩ R9 2.7KΩ C1 220 pF Q1 , Q2 , 2N4356, 2N5086
R2 47KΩ R10 680Ω C2 100 µF 10V or equivalent
R3 15KΩ R11 10KΩ C3 47 µF 40V Q3 , Q4 , 2N4410, 2N5088
R4 1.2KΩ R12 1KΩ Pot. C4 47 µF 40V or equivalent
R5 560Ω R13 820Ω C5 2200 µF 40V Q5 IRF532
R6 47KΩ R14 4.7KΩ C6 2200 µF 40V Q6 IRF9532
R7 4.70Ω R15 10 Ω 1 W C7 68 nF D1 IN4002
R8 2.7KΩ Rload 8/4 Ω L1 3 µΗ aircored
Table 1. Components List

The class A driver transistor, Q4, operates at a bias current determined by resistors R8, R9, nominally 5mA. Q4 is driven by a PNP differential
input pair, Q1, Q2. The bias current in
the input stage is set to 2mA by
resistor R3. Negative feedback from
the output of the amplifier is fed to
the base of Q2 by resistor R6. Com-
ponents R7, C2 set the closed loop
gain of the amplifier (R6 /R7) and
provide low frequency gain
boosting. The additional
components R15, C7 connected
between the output node and ground
suppress the high frequency
response of the output stage,
allowing the h.f. performance of the
amplifier to be determined by the
input circuit. Components R1, R2,
C1 at the input of the amplifier
define the input impedance
(47Kohm) and suppress noise. Q5 Q6
D1
R10

The amplifier input stage requires R8

additional power supply ripple sup-
pression which is provided by com- R9
C4 Q4
R6

ponents R4, C3. Q3

R14
C7
R11

R13

Additional circuit components have R12

R4

R5
been added to ensure high fre- C5 C6
quency stability of the complete R3 Q3
amplifier. Placement of the compo- Q2
nents and component values will
depend to some extent on the
C3 C2
C1

printed circuit board layout. The

R2

R1

R15
following rules should be followed
R7

when designing the printed circuit

board:

(a) A 'common ground'

principle should be Figure 2. Amplifier Printed Circuit Board Layout
 AN-948 (v.Int)
adopted, i.e., power supply decoupling capacitors, load and input stage biasing components should all be taken to
ground in close proximity, eliminating the effects of common node ground current. Similarly, a "common output
node" should be used, the load, feedback resistor and h.f. suppression components being taken from a common
point on the pcb.

(b) The length of connecting lead to the gate terminals of HEXFET Power MOSFETs Q5, Q6 should be an absolute
minimum to avoid oscillation of the power output stage. A series gate resistor, R10, may be used to suppress
oscillation, but too high a resistor value will limit the slew rate. Oscillation of the amplifier caused by capacitive
coupling to the base of the driver transistor, Q4, is suppressed by the addition of a series resistor, R14.

(c) Phase shift in the amplifier when driving a reactive load can lead to high frequency instability. With a capacitive
load, the addition of a small, air-cored choke (3µH with an 8 ohm, 2µF load) will restore stability. The final value
of the choke is defined by experiment.

Figure 2 shows a printed circuit layout which can be used for the circuit shown in Figure 1. The preceding design rules have been
followed.

2. AMPLIFIER PERFORMANCE
(a) Output Power: To achieve 60W rms into a 4 ohm load, the current in the load is 3.9A rms or 5.5A pk. This information is
derived from equations (1) and (2):

PO = I
2
rms R load

2 (1)
V rms
=
R load

I pk
I rms = (2)
2

Vpk
Vrms = (3)
2

Also from equation (1), the voltage developed across the load
at 60W output is 15.5V rms or 22V pk. To sustain a source
current of 5.5A, the n-channel HEXFET Power MOSFET,
IRF530, requires a gate-source voltage of 5V. One can
conclude that the gate bias voltage to achieve peak power in
the positive sense is Vpk + Vp = 27V. A similar calculation
for the negative peak, using the P channel HEXFET Power
MOSFET IRF9530, shows that a negative gate bias supply of
-28V is required.

Consequently, a ±30V supply will be adequate for a 60W

output, provided that the supply voltage does not fall below
±28V when loaded, i.e., the power supply impedance should
be better than 1 ohm. The relationship between the power
delivered to the load and the power absorbed from the supply
is shown in Figure 3, assuming a sinusoidal waveform and a
±30V supply. The curve representing the power delivered to
the load can be easily plotted with the help of equation (1)
for different values of load current.

Figure 3. Power Curves for the Amplifier with 4 and 8 Ohm

Loads and + 30V Power Suuplies
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The power absorbed from the supply has been plotted with the help of the following relationship:

( )( )
PS = Vavg I avg

 2  (4)
(
= 2 VDC  I rms  )
 π 

The difference between the two is the power dissipated in the HEXFET Power MOSFETs and as it can be seen from Figure 3, it
has a peak of approximately 46W. Assuming a maximum ambient temperature of 55°C, the total thermal resistance between the
junction of the two HEXFET Power MOSFETs and the ambient will have to be less than 2°C/W. Considering that the IRF530
and IRF9530 have a thermal resistance between junction and case of 1.7°C/W each, the maximum case temperature will have to
be less than 110°C and the thermal resistance of the heatsink will have to be less than 1.15°C/W to ambient.

(b) Frequency Response: Open shown in Figure 4. The open loop gain, measured with gate and source connections
to the HEXFET Power MOSFETs broken, is 30db, -3db points occurring at 15 Hz and 60kHz. Closed loop curves are shown for
amplifier gains of 100 (R7 = 470 ohm) and 20 (R7 = 2.2K ohm). In both instances the curves remain flat to within +1db between
15 Hz and 100kHz with an 8 ohm load. The slew rate of the amplifier, measured with a 2V pk-pk square wave input is 13V/µs
positive going and 16V/µs negative going. The discrepancy could be balanced out by addition of a series gate resistor for Q6.

40

OPEN
LOOP
30

R7 = 100

R6
20
VOLTAGE GAIN (dB)

R7 = 100

R6

10

VDD= = 30V

RL= 8OHM

0
101 4 102 4 103 4 104 4 105 4 106
FREQUENCY (Hz)
Figure 4. Amplifier Open and Closed Loop Frequency Response Curves

(c) Total Harmonic Distortion: The fidelity of the amplifier is shown in the distortion curves, Figure 5, and is limited by the loop
gain. Reduction of the closed loop gain from 100 to 20 produces a significant improvement in distortion figure. The output stage
quiescent current was adjusted to 100mA and can influence the distortion measurement significantly if allowed to fall below
50mA.

(d) Quiescent Operating: The dependence of the quiescent current in the output stage and of the offset voltage on power supply
voltage are illustrated in Table 2. The quiescent current is set by first adjusting the potentiometer, R12 , for minimum offset
voltage-turned fully anticlockwise if the pcb layout in Figure 2 is used - and applying the power supply voltage, the positive
 AN-948 (v.Int)

supply passing through an ammeter with 1A f.s.d. R12 is then adjusted until the meter reading is 100mA with ±30V supplies.
The meter should be removed from circuit before applying an input signal to the amplifier.
3. POWER SUPPLY REGULATION REQUIREMENTS
A simple line derived power suitable for the class AB amplifier is illustrated in Figure 6. The ±30V supplies are
taken from the centertapped secondary of the line transformer. The 2200µF decoupling capacitors, (Figure 1) which
should be mounted as close as possible to the amplifier output stage, reduce the supply frequency ripple to 5.5V pk-pk at full
load.

4. SET-UP PROCEDURE AND TROUBLESHOOTING

101
It is unlikely that any experienced
VDD + 30V
experimenter will have difficulty in
achieving satisfactory results when F = 1 KHz
building an amplifier to this design. 4
The printed circuit board shown in
TOTAL HARMONIC DISTORTION %

Figure 2 is intended to assist in this

respect. The major problems antici-
pated are those associated with the
100
faulty assembly of components and GAIN = 100 RL=4 OHM
damage to the HEXFET Power
MOSFETs through handling or
4
circuit oscillation.
RL= 8 OHM
GAIN=100
The following troubleshooting
checklist is offered as a guide to the
GAIN = 20 RL= 4 OHM
experimenter: 10-1

1. When assembling the printed RL= 8 OHM

GAIN = 20
circuit board, mount the passive 4
components first, ensuring the cor-
rect polarity of electrolytic capaci-
tors. Then solder in the transistors
Q1 - Q4 checking for correct pin
identification. Finally, mount the 10-2
HEXFET Power MOSFETs, 0 10 20 30 40 50 60
avoiding static discharge by OUTPUT POWER (WATTS)
shorting the pins together to ground Figure 5. Amplifier Total Harmonic Distortion Curves
and using a grounded soldering
iron. Check the assembled board for correct component placement. A component side overlay as shown in Figure 2 is useful for
this purpose. Check the copper side of the
board for solder bridges between tracks,
and remove them. Check for dry solder
joints visually and electrically using a
resistance meter and rework, if necessary.

2. Power can now be applied to the

amplifier and the output stage quiescent
current set to between 50 and 100mA.
The potentiometer, R12 is first adjusted
for minimum offset (fully anticlockwise
on the pcb layout in Figure 2). An
ammeter is connected in series with the
positive supply and selected to read 1A
f.s.d R12 is adjusted until the ammeter
reads between 50mA and 100mA.

Figure 6. Off-line power supply

 AN-948 (v.Int)
Quiescent current setting can be performed without the load connected.
If, however, a loudspeaker load is connected in circuit, it can be protected by a fuse from dc overload. With the quiescent current
set, the output offset voltage can be confirmed to be less than 100mV. Excessive and erratic variation in quiescent current as R 12
is adjusted are indicative of circuit oscillation or faulty wiring. The solutions described in "Circuit Description" (series gate res-
istors, minimized gate wiring and common earthing) should be adopted. Also, supply decoupling capacitors should be mounted
in close proximity to the amplifier output stage and load ground point. Quiescent current setting should be performed with the
HEXFET Power MOSFETs mounted on their heatsink to avoid overdissipation.

3. With the quiescent current set, the ammeter should be removed from the positive supply and a signal can be applied to the
amplifier input. Signal requirements for full rated output are:

gain = 100:
RL = 4 Ω, Vin = 150mV rms
RL = 8 Ω, Vin = 160mV rms

gain = 20:
RL = 4 Ω, Vin = 770mV rms
RL = 8 Ω, Vin = 800mV rms

Variation in Output Offset Voltage and Output Quiescent Current with Supply Voltage
Supply Voltage Output Offset Output Quiescent Current
+ VDD V VOS mV Iq mA
35 -40 135
30 -20 100
25 +4 75
20 +30 54
Table 2. Variation in Output offset voltage and Output quiescent current with supply voltage

"Clipping" of the output waveform when operating at rated power indicates poor supply regulation and can be remedied by
reducing the input signal amplitude and derating the amplifier. Alternatively, a lower impedance supply should be used. The
frequency response of the amplifier can be checked over the frequency range 15 Hz - 100kHz with the aid of an audio test set or
signal generator and oscilloscope. Distortion of the output waveform at high frequency is indicative of a reactive load and
adjustment of the output choke will be required to restore the waveform. The high frequency response may be tailored with a
compensation capacitor in parallel with R6. The low frequency response is controlled by components R7, C2.

4. Hum pickup will be more likely to occur in a high gain circuit. Pickup at the high impedance input is minimized by use of a
shielded cable, grounded at the signal source. Supply frequency ripple injected through the supply to the input stage of the
amplifier can be detected across capacitor, C3. This is attenuated by the common mode rejection ratio of Q 1, Q2 before being
amplified. However, if this is the source of hum, adjustment to the values of C3, R5 can be made to suppress the signal amplitude.

5. In the event of the output stage being destroyed, either through short circuit load or h.f. oscillation, both HEXFET Power
MOSFETs should be replaced. It is unlikely, however, that other circuit components will have been affected. The setup procedure
should, of course, be repeated with the new devices in circuit.

5. PERFORMANCE SUMMARY
Using a complementary pair of HEXFET Power MOSFETs, IRF530 and IRF9530 and with a ±30V supply, the following
performance can be achieved:

Maximum rms output power:

60W into 4Ω
32W into 8Ω
 AN-948 (v.Int)

Bandwidth:

15 Hz to 100kHz ±1db

Total harmonic distortion (1kHz):

0.15% at 60W into 4Ω

0.08% at 32W into 8Ω

Voltage gain:

Adjustable, X100 to X20

Input impedance: 47KΩ

1 KHz 100 KHz

1V 200 µS 1V µS
2µ

INPUT

OUTPUT

10V 10V

Figure 7a: Sinewave Frequency Response

1 KHz 25 KHz

2V 200 µS 2V µS
10µ

INPUT

OUTPUT

10V 10V

Figure 7b: Square Wave Response

Figure 7a & 7b: Amplifier Waveforms illustrating Frequency Response

Figure 7 illustrates the amplifier response to 1kHz and 100kHz sinewave input signals and also the square wave response at 1kHz
and 25kHz.

Related topics:
P-Channel HEXFET Power MOSFETs
Gate drive requirements
 AN-948 (v.Int)
Thermal design

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 AN-948 (v.Int)
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