Freescale Semiconductor, Inc.

DOCUMENT NUMBER
9S12C32DGV1/D

MC9S12C32
Device User Guide
V01.14
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Original Release Date: 25 JUL 2001

Revised: 07 FEBRUARY 2003

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 Freescale Semiconductor, Inc.
Device User Guide — 9S12C32DGV1/D V01.14

Revision History

Version Revision Effective Author Description of Changes

Number Date Date
0.1 25.JUL.01 25.JUL.01 Original Version
Corrected subscripted pin names.
Corrected MOD to MODC in pin list table
Corrected TIM Module address range
V00.02 01 AUG 01 01 AUG 01 Removed detailed XTAL, EXTAL pin descriptions (part of CRG)
Moved TPM Module base address
Moved TPM vector addresses
Various minor corrections
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Updated device name.

Updated 80-pin package pinout as of Prod. Prop. Rev. 0.7
07 AUG 07 AUG Added non_cust tags.
V00.03
2001 2001 Added App. A eletricals: ATD, NVM, CRG, CAN, SPI, EXT.
Added App. B.
Minor cleanup.
19 SEP 19 SEP Replaced TPM with PWM
V00.04
2001 2001 Minor corrections
Reset pin description, Reset interrupt description.
Added PWM emergency shutdown to DUG features list
24SEP 11 OCT
V00.05 Modified recommended PCB Layout for 52 LQFP
2001 2001
Added PWM shutdown vector, deleted 2 incorrect vector sources
Changed "STAR12" references to "HCS12"
Changed MSCAN interrupt enable names.
Added mechanical package informationor 48LQFP and 52LQFP
24SEP 09 NOV Updated user guide version references in Preface
V00.06
2001 2001 Added ROMONE pin description
Moved non bonded pin initialization info from PIM to user guide.
Corrected typos
08 JAN 08 JAN Added power domain map to I/O pin list
V00.07
2002 2002 Changed PortP KWU interrupt vector to $FF8E
24 JAN 24 JAN Enhanced PortP6, ROMON signal description
V00.08
2002 2002 Corrected revision date
Updated block user guide version references
08 MAR 08 MAR Included 3V ATD range electricals
V01.00
2002 2002 Revised output driver strengths.
Updated power consumption/dissipation and thermal properties
22 MAR 22 MAR
V01.01 Updated Flash electricals, removed NDA labels
2002 2002
13 MAY 13 MAY
V01.02 Updated Flash W/E spec.
2002 2002
10 JUN 10 JUN
V01.03 Added 3.3V range I/O parameters
2002 2002
14 JUN 15 JUN
V01.04 Preface Section Table corrections
2002 2002
Changed 5V range to 5V+/-10% in electrical parameter tables
21 JUN 21 JUN
V01.05 Added ATD 8-bit resolution accuracy parameters
2002 2002
Added general comment for range 3.6V to 4.5V

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 Freescale Semiconductor, Inc.
Device User Guide — 9S12C32DGV1/D V01.14

Version Revision Effective Author Description of Changes

Number Date Date
09 JULY 09 JULY Updated SPI electrical parameters
V01.06
2002 2002 Corrected interrupt enable register/bit names
Included register map listing in overview.
25JULY 25JULY
V01.07 Added parameter classification column to electrical parameter
2002 2002
tables.
01 AUG. 01 AUG. Created new Printed Circuit Board Section.
V01.08
2002 2002 Updated formats
24 SEP 24 SEP.
V01.09 Corrected register name errors in memory map summary
2002 2002
10 OCT 10 OCT Corrected PK7 reference to PP6
V01.10
2002 2002 Included OSC user guide reference
Removed incorrect reference to RESET pin pullup.
04 NOV 04 NOV
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V01.11 Corrected 3V+/- 10% to 3.3V +/- 10% in exp.bus timing table.
2002 2002
Added VREG electricals to appendix.
Corrected INITEE register contents
19 DEC 19 DEC
V01.12 Corrected WAIT current in electrical parameters
2002 2002
Changed recommended VREG capacitor values
Changed ROMONE pin references to ROMCTL
Preface Table 0-2 updates
Added BDM alternate clock clarification
23 JAN 23 JAN
V01.13 Corrected footnote in PLL electrical parameter table
2003 2003
Corrections to detailed register map.
Enhanced section 4.3.3 "Unsecuring the microcontroller"
Updated Part ID Table
07 FEB 07 FEB Corrected PE[1:0] Pull specification in signal property table
V01.14
2003 2003 Enhanced description of Partnumber encoding in preface

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 Freescale Semiconductor, Inc.
Device User Guide — 9S12C32DGV1/D V01.14
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Device User Guide — 9S12C32DGV1/D V01.14

Table of Contents

Section 1 Introduction
1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.6 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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1.7 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Section 2 Signal Description

2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.2.1 Pin Initialization for 48 & 52 Pin LQFP bond-out versions . . . . . . . . . . . . . . . . . . 44
2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.3.1 EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.3.2 RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.3.3 TEST / VPP — Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.3.4 XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High & Mode Pin . . . . . . . 45
2.3.6 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . 46
2.3.7 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . 46
2.3.8 PE7 / NOACC / XCLKS — Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.3.9 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.3.10 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.3.11 PE4 / ECLK— Port E I/O Pin [4] / E-Clock Output . . . . . . . . . . . . . . . . . . . . . . . . 48
2.3.12 PE3 / LSTRB — Port E I/O Pin [3] / Low-Byte Strobe (LSTRB). . . . . . . . . . . . . . 48
2.3.13 PE2 / R/W — Port E I/O Pin [2] / Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.3.14 PE1 / IRQ — Port E input Pin [1] / Maskable Interrupt Pin . . . . . . . . . . . . . . . . . 48
2.3.15 PE0 / XIRQ — Port E input Pin [0] / Non Maskable Interrupt Pin . . . . . . . . . . . . 49
2.3.16 PAD[7:0] / AN[7:0] — Port AD I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.3.17 PP[7] / KWP[7] — Port P I/O Pin [7]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.3.18 PP[6] / KWP[6]/ROMCTL — Port P I/O Pin [6] . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.3.19 PP[5:0] / KWP[5:0] / PW[5:0] — Port P I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . 49

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2.3.20 PJ[7:6] / KWJ[7:6] — Port J I/O Pins [7:6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

2.3.21 PM5 / SCK — Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.3.22 PM4 / MOSI — Port M I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.3.23 PM3 / SS — Port M I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.3.24 PM2 / MISO — Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.3.25 PM1 / TXCAN — Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.3.26 PM0 / RXCAN — Port M I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.3.27 PS[3:2] — Port S I/O Pins [3:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.3.28 PS1 / TXD — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.3.29 PS0 / RXD — Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.3.30 PPT[7:5] / IOC[7:5] — Port T I/O Pins [7:5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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2.3.31 PT[4:0] / IOC[4:0] / PW[4:0]— Port T I/O Pins [4:0] . . . . . . . . . . . . . . . . . . . . . . . 51

2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers . . . . . . . . . . . . . . . . . . . . . 51
2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator
51
2.4.3 VDD1, VDD2, VSS1, VSS2 — Core Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . 51
2.4.5 VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . 51
2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . 51

Section 3 System Clock Description

Section 4 Modes of Operation

4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.2 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.3 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.3.1 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.3.2 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.3.3 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.4.1 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.4.2 Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.4.3 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.4.4 Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Section 5 Resets and Interrupts

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5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3.1 Reset Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.3.2 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Section 6 HCS12 Core Block Description

6.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.1.1 PPAGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.1.2 BDM alternate clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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Section 7 Voltage Regulator (VREG) Block Description

7.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.1.1 VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.1.2 VDD1, VDD2, VSS1, VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Section 8 Recommended Printed Circuit Board Layout

Section 9 Clock Reset Generator (CRG) Block Description

9.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.1.1 XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Section 10 Oscillator (OSC) Block Description

Section 11 Timer (TIM) Block Description

Section 12 Analog to Digital Converter (ATD) Block Description

12.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
12.1.1 VRL (voltage reference low). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Section 13 Serial Communications Interface (SCI) Block Description

Section 14 Serial Peripheral Interface (SPI) Block Description

Section 15 Flash EEPROM 32K Block Description

Section 16 RAM Block Description

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Section 17 Pulse Width Modulator (PWM) Block Description

Section 18 MSCAN Block Description

Section 19 Port Integration Module (PIM) Block Description

Appendix A Electrical Characteristics

A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 73
A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Appendix B Electrical Specifications

B.1 Voltage Regulator Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
B.2 Chip Power-up and LVI/LVR graphical explanation . . . . . . . . . . . . . . . . . . . . . . . . . 82
B.3 Output Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
B.3.1 Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
B.3.2 Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
B.4 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
B.4.1 ATD Operating Characteristics In 5V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
B.4.2 ATD Operating Characteristics In 3.3V Range . . . . . . . . . . . . . . . . . . . . . . . . . . 85
B.4.3 Factors influencing accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
B.4.4 ATD accuracy (5V Range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
B.4.5 ATD accuracy (3.3V Range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
B.5 NVM, Flash and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
B.5.1 NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
B.5.2 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
B.6 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
B.6.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

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B.6.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
B.6.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
B.7 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
B.8 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Appendix C Electrical Specifications

C.1 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
C.2 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
C.3 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
C.3.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Appendix D Package Information

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D.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

D.2 80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
D.3 52-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
D.4 48-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

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List of Figures

Figure 0-1 Order Partnumber Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 1-1 MC9S12C32 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 1-2 MC9S12C32 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 2-1 Pin Assignments in 80 QFP for MC9S12C32 . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 2-2 Pin assignments in 52 LQFP for MC9S12C32 . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 2-3 Pin Assignments in 48 LQFP for MC9S12C32 . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 2-4 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 2-5 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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Figure 2-6 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 2-7 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 3-1 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 8-1 Recommended PCB Layout (48 LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 8-2 Recommended PCB Layout (52 LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 8-3 Recommended PCB Layout (80 QFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure B-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled) . . . . . 82
Figure B-2 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure B-3 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure B-4 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure B-5 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure C-1 SPI Master Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure C-2 SPI Master Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure C-3 SPI Slave Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure C-4 SPI Slave Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure C-5 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure D-1 80-pin QFP Mechanical Dimensions (case no. 841B) . . . . . . . . . . . . . . . . 112
Figure D-2 52-pin LQFP Mechanical Dimensions (case no. 848D-03) . . . . . . . . . . . . 113
Figure D-3 48-pin LQFP Mechanical Dimensions (case no.932-03 ISSUE F) . . . . . . 114

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List of Tables

Table 0-1 Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 0-2 Partnumber Coding Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 0-3 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 1-1 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
$0000 - $000F MEBI map 1 of 3 (Core User Guide) 23
$0010 - $0014 MMC map 1 of 4 (Core User Guide) 23
$0018 - $0018 Miscellaneous Peripherals (Device User Guide) 24
$0019 - $0019 VREG3V3 (Voltage Regulator) 24
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$0015 - $0016 INT map 1 of 2 (Core User Guide) 24

$0017 - $0017MMC map 2 of 4 (Core User Guide) 24
$001A - $001B Miscellaneous Peripherals (Device User Guide) 24
$001C - $001D MMC map 3 of 4 (Core User Guide, Device User Guide) 25
$001E - $001E MEBI map 2 of 3 (Core User Guide) 25
$001F - $001F INT map 2 of 2 (Core User Guide) 25
$0020 - $002F DBG (including BKP) map 1 of 1 (Core User Guide) 25
$0030 - $0031 MMC map 4 of 4 (Core User Guide) 26
$0032 - $0033 MEBI map 3 of 3 (Core User Guide) 26
$0034 - $003F CRG (Clock and Reset Generator) 26
$0040 - $006F TIM (Timer 16 Bit 8 Channels) 27
$0070 - $007F Reserved 29
$0080 - $009F ATD (Analog to Digital Converter 10 Bit 8 Channel) 29
$00A0 - $00C7 Reserved 30
$00D0 - $00D7 Reserved 31
$00C8 - $00CF SCI (Asynchronous Serial Interface) 31
$00D8 - $00DF SPI (Serial Peripheral Interface) 31
$00E0 - $00FF PWM (Pulse Width Modulator) 32
$0100 - $010F Flash Control Register (fts32k) 33
$0110 - $013F Reserved 34
$0140 - $017F CAN (Motorola Scalable CAN - MSCAN) 34
Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . 35
$0180 - $023F Reserved 36
$0240 - $027F PIM (Port Interface Module) 36
$0280 - $03FF Reserved space 39

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Table 1-3 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 1-4 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 2-2 MC9S12C32 Power and Ground Connection Summary . . . . . . . . . . . . . . . . . 52
Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 5-2 Reset Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 8-1 Recommended External Component Values. . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table A-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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Table A-3 ESD and Latch-Up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table A-4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table A-7 3.3V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table A-8 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table B-1 -Voltage Regulator Electrical Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table B-2 Voltage Regulator - Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table B-3 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table B-4 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table B-5 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table B-6 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table B-7 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table B-8 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table B-9 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table B-10 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table B-11 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table B-12 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table B-13 MSCAN Wake-up Pulse Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table C-1 Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table C-2 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table C-3 SPI Slave Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table C-4 Expanded Bus Timing Characteristics (5V Range). . . . . . . . . . . . . . . . . . . . 108
Table C-5 Expanded Bus Timing Characteristics (3.3V Range) . . . . . . . . . . . . . . . . . . 109

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Preface

The Device User Guide provides information about the MC9S12C32 device made up of standard HCS12
blocks and the HCS12 processor core. This document is part of the customer documentation. A complete
set of device manuals also includes the HCS12 Core User Guide and all the individual Block User Guides
of the implemented modules. In a effort to reduce redundancy all module specific information is located
only in the respective Block User Guide. If applicable, special implementation details of the module are
given in the block description sections of this document
Table 0-1 Derivative Differences
Generic device MC9S12C32 MC9S12C32 MC9S12C32
Part Numbers MC9S12C32 MC9S12C32 MC9S12C32
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Package 80QFP 52LQFP 48LQFP

Mask set L45J L45J L45J
Temp. Options M, V, C M, V, C M, V, C
Notes: C: TA = 85¯C, f = 25MHz. V: TA=105¯C, f = 25MHz. M: TA= 125¯C, f = 25MHz

MC9S12 C32 (P) C FU 25 Temperature Options

C = -40˚C to 85˚C
Speed Option V = -40˚C to 105˚C
M = -40˚C to 125˚C
Package Option
Package Options
Temperature Option FU = 80QFP
PB = 52LQFP
Preliminary Option FA = 48LQFP
Speed Options
Device Title 25 = 25MHz bus
16 = 16MHz bus
Controller Family

Figure 0-1 Order Partnumber Coding

Table 0-2 Partnumber Coding Example

48LQFP MC9S12C32CFA25 1L45J Temp. option "C", package option "48LQFP" , speed option "25MHz"
52LQFP MC9S12C32MPB25 1L45J Temp. option "M", package option "52LQFP", speed option "25MHz"
80QFP MC9S12C32CFU25 1L45J Temp. option "C", package option "80QFP" , speed option "25MHz"

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Table 0-3 Document References

User Guide Version Document Order Number
HCS12 Core User Guide (CPU, Interrupt, Mapping , Exp.Bus, BDM, Debug) 1.5 HCS12COREUG/D
Analog To Digital Converter: 10 Bit 8 Channel (ATD_10B8C) Block User Guide V02 S12ATD10B8CV2
Clock and Reset Generator (CRG) Block User Guide V04 S12CRGV4
Serial Communications Interface (SCI) Block User Guide V02 S12SCIV2
Serial Peripheral Interface (SPI) Block User Guide V03 S12SPIV3
Motorola Scalable CAN (MSCAN) Block User Guide V02 S12MSCANV2
Voltage Regulator (VREG_3V3) Block User Guide V02 S12VREG3V3V1
(Port Integration Module) PIM_9C32 Block User Guide V01 S12C32PIMV1
32Kbyte Flash EEPROM (FTS32K) Block User Guide V01 S12FTS32KV1
Pulse Width Modulator: 8 bit, 6 channel (PWM_8B6C) Block User Guide V01 S12PWM8B6V1
Timer : 16 bit, 8 channel (TIM_16B8C) Block User Guide V01 S12TIM16B8CV1
Oscillator (OSC) Block User Guide V02 S12OSCV2/D
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Terminology
Acronyms and Abbreviations

New or invented terms, symbols, and notations

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Device User Guide — 9S12C32DGV1/D V01.14

Section 1 Introduction

1.1 Overview
The MC9S12C32 is a 48/52/80 pin Flash-based Industrial/Automotive network control MCU, comprised
of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), 32K bytes of
Flash EEPROM, 2K bytes of RAM, an asynchronous serial communications interface (SCI), a serial
peripheral interface (SPI), an 8-channel 16-bit timer module (TIM), a 6-channel 8-bit Pulse Width
Modulator (PWM), an 8-channel, 10-bit analog-to-digital converter (ADC) and a CAN 2.0 A, B software
compatible module (MSCAN). Furthermore, an on chip bandgap based voltage regulator (VREG)
generates the internal digital supply voltage (VDD) for a 3 V to 5.5V external supply range. The
MC9S12C32 has full 16-bit data paths throughout. The inclusion of a PLL circuit allows power
consumption and performance to be adjusted to suit operational requirements. A total of 50 I/O port pins
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and 2 input pins are available in the 80 pin package version. Furthermore, up to 12 I/O port bits are
available with Wake-Up capability from STOP or WAIT mode.

1.2 Features
• 16-bit HCS12 CORE
– HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to M68HC11
iii. Instruction queue
iv. Enhanced indexed addressing
– MMC (memory map and interface)
– INT (interrupt control)
– BDM (background debug mode)
– DBG12 (enhanced debug12 module, backwardly compatible with BKP breakpoint module)
– MEBI : Multiplexed Expansion Bus Interface (available only in 80 pin package version)
• Wake-up interrupt inputs
– Up to 12-port bits available for wake up interrupt function with digital filtering
• Memory
– 32K Byte Flash EEPROM (erasable in 512-byte sectors)
– 2K Byte RAM
• Analog-to-Digital Converters
– One 8-channel module with 10-bit resolution.
– External conversion trigger capability

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• One 1M bit per second, CAN 2.0 A, B software compatible modules

– Five receive and three transmit buffers
– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
– Low-pass filter wake-up function
– Loop-back for self test operation
• Timer Module (TIM)
– 8-Channel Timer
– Each Channel Configurable as either Input Capture or Output Compare
– Simple PWM Mode
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– Modulo Reset of Timer Counter

– 16-Bit Pulse Accumulator
– External Event Counting
– Gated Time Accumulation
• 6 PWM channels
– Programmable period and duty cycle
– 8-bit 6-channel or 16-bit 3-channel
– Separate control for each pulse width and duty cycle
– Center-aligned or left-aligned outputs
– Programmable clock select logic with a wide range of frequencies
– Fast emergency shutdown input
• Serial interfaces
– One asynchronous serial communications interface (SCI)
– One synchronous serial peripheral interface (SPI)
• CRG (Clock Reset Generator Module)
– Windowed COP watchdog,
– Real time interrupt,
– Clock monitor,
– Pierce or low current Colpitts oscillator
– Phase-locked loop clock frequency multiplier
– Limp home mode in absence of external clock
– Low power 0.5 to 16 MHz crystal oscillator reference clock

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• Operating frequency
– 25MHz Bus Speed
• Internal 2.5V Regulator
– Supports an input voltage range from 2.97V to 5.5V
– Low power mode capability
– Includes low voltage reset (LVR) circuitry
– Includes low voltage interrupt (LVI) circuitry
• 48-Pin LQFP, 52-Pin LQFP or 80-Pin QFP package
– Up to 58 I/O lines with 5V input and drive capability (80 pin package)
– Up to 2 dedicated 5V input only lines (IRQ, XIRQ)
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– 5V 8 A/D converter inputs and 5V I/O

• Development support
– Single-wire background debug™ mode (BDM)
– On-chip hardware breakpoints
– Enhanced DBG12 debug features

1.3 Modes of Operation

User modes (Expanded modes are only available in the 80 pin package version).
• Mormal and Emulation Operating Modes
– Normal Single-Chip Mode
– Normal Expanded Wide Mode
– Normal Expanded Narrow Mode
– Emulation Expanded Wide Mode
– Emulation Expanded Narrow Mode
• Special Operating Modes
– Special Single-Chip Mode with active Background Debug Mode
– Special Test Mode (Motorola use only)
– Special Peripheral Mode (Motorola use only)
Low power modes
• Stop Mode
• Pseudo Stop Mode
• Wait Mode

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1.4 Block Diagram

Figure 1-1 MC9S12C32 Block Diagram
VSSR VDDA VDDA
VDDR ATD VSSA VSSA
VDDX VRH VRH
VSSX Voltage Regulator VRL VRL
AN0 PAD0
AN1 PAD1
AN2 PAD2

DDRAD
PTAD
AN3 PAD3
VDD2 32K Byte Flash EEPROM AN4 PAD4
VSS2 AN5 PAD5
VDD1 AN6 PAD6
2K Byte RAM
VSS1 AN7 PAD7

BKGD MODC Background IOC0 PT0

Debug12 Module HCS12
IOC1 PT1
CPU MUX
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XFC IOC2 PT2

DDRT
VDDPLL IOC3

PTT
Clock and Timer PT3
VSSPLL Reset Module IOC4 PT4
PLL Generation IOC5
EXTAL COP Watchdog PT5
Module IOC6
XTAL Clock Monitor PT6
RESET Periodic Interrupt IOC7 PT7
PE0 XIRQ PW0 PP0

Key Int Keypad Interrupt

PE1 IRQ PW1 PP1
System PW2
PE2 R/W PWM PP2
Integration
DDRE

DDRP
PTE

PTP
PE3 LSTRB/TAGLO Module Module PW3 PP3
PE4 ECLK (SIM) PW4 PP4
PE5 MODA/IPIPE0 PW5 PP5
PE6 MODB/IPIPE1 PP6
PE7 NOACC/XCLKS PP7
TEST/VPP

DDRJ
PJ6

PTJ
PJ7

Multiplexed Address/Data Bus RXD PS0

SCI
DDRS
PTS
TXD PS1
PS2
DDRA DDRB PS3
PTA PTB RXCAN PM0
MSCAN
TXCAN PM1
DDRM
PTM

MISO PM2
PB7
PB6
PB5

PB3
PB2
PB1
PB0
PB4
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0

SPI SS PM3
MOSI PM4
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10

SCK
ADDR9

ADDR7
ADDR6
ADDR5

ADDR3
ADDR2
ADDR1
ADDR0
ADDR8

ADDR4

PM5
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9

DATA7
DATA6
DATA5

DATA3
DATA2
DATA1
DATA0
DATA8

DATA4

Multiplexed
Wide Bus Signals shown in Bold are not available on the 52 or 48 Pin Package
Signals shown in Bold Italic are available in the 52, but not the 48 Pin Package

Internal Logic 2.5V I/O Driver 5V

VDD1,2 VDDX
VSS1,2 VSSX

PLL 2.5V A/D Converter 5V VRL is bonded internally to VSSA

VDDPLL VDDA for 52 and 48 Pin packages
VSSPLL VSSA

Voltage Regulator 5V & I/O

VDDR
VSSR

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1.5 Device Memory Map

and Figure 1-2 show the device memory map of the MC9S12C32 after reset.
Table 1-1 Device Memory Map
Address Module Size
$000 - $017 CORE (Ports A, B, E,Modes, Inits, Test) 24
$018 Reserved 1
$019 Voltage Regulator (VREG) 1
$01A - $01B Device ID register 2
$01C - $01F CORE (MEMSIZ, IRQ, HPRIO) 4
$020 - $02F CORE (DBG) 16
$030 - $033 CORE (PPAGE1) 4
$034 - $03F Clock and Reset Generator (CRG) 12
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$040 - $06F Standard Timer Module16-bit 8-channels (TIM) 48

$070 - $07F Reserved 16
$080 - $09F Analog to Digital Convert (ATD) 32
$0A0 - $0C7 Reserved 40
$0C8 - $0CF Serial Communications Interface (SCI) 8
$0D0 - $0D7 Reserved 8
$0D8 - $0DF Serial Peripheral Interface (SPI) 8
$0E0 - $0FF Pulse Width Modulator 8-bit 6 channels (PWM) 32
$100 - $10F Flash Control Register 16
$110 - $13F Reserved 48
$140 - $17F Motorola Scalable CAN (MSCAN) 64
$180 - $23F Reserved 192
$240 - $27F Port Integration Module (PIM) 64
$280 - $3FF Reserved 384
$0800 - $0FFF 2K RAM Array 2048
$8000 - $FFFF 32K Fixed Flash EEPROM Array 32768
NOTES:
1. External memory paging is not supported on this device (6.1.1 PPAGE).

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Device User Guide — 9S12C32DGV1/D V01.14

Figure 1-2 MC9S12C32 Memory Map

$0000
$0000
$0400 1K Register Space
$0800 $03FF (Mappable to any 2k Block
within the first 32K)
$1000 $0800
2K BytesRAM
$0FFF (Mappable to any 2K boundary)
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$4000

16K Fixed Flash EEPROM block 1

For reset state (ROMHM=0)

$7FFF
$8000

EXTERNAL

$8000
16K Page Window
Fixed Flash EEPROM block 1
visible at reset
$BFFF
$C000 $C000

16K Fixed Flash EEPROM block 2

$FFFF 2K, 4K, 8K or 16K Protected Boot Sector

$FF00
VECTORS VECTORS VECTORS
$FFFF
EXPANDED NORMAL SPECIAL
SINGLE CHIP SINGLE CHIP

NOTE: The same Flash block is visible at reset in both $4000-$7FFF and $8000-$BFFF ranges
NOTE: Expanded Modes are only available in the 80 pin QFP package version

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Device User Guide — 9S12C32DGV1/D V01.14

1.6 Detailed Register Map

through show the detailed register map of the MC9S12C32

$0000 - $000F MEBI map 1 of 3 (Core User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$0000 PORTA Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0001 PORTB Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0002 DDRA Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0003 DDRB Bit 7 6 5 4 3 2 1 Bit 0
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Write:
Read: 0 0 0 0 0 0 0 0
$0004 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0005 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0006 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0007 Reserved
Write:
Read: Bit 1 Bit 0
$0008 PORTE Bit 7 6 5 4 3 2
Write:
Read: 0 0
$0009 DDRE Bit 7 6 5 4 3 Bit 2
Write:
Read: 0 0 0
$000A PEAR NOACCE PIPOE NECLK LSTRE RDWE
Write:
Read: 0 0
$000B MODE MODC MODB MODA IVIS EMK EME
Write:
Read: 0 0 0 0
$000C PUCR PUPKE PUPEE PUPBE PUPAE
Write:
Read: 0 0 0 0
$000D RDRIV RDPK RDPE RDPB RDPA
Write:
Read: 0 0 0 0 0 0 0
$000E EBICTL ESTR
Write:
Read: 0 0 0 0 0 0 0 0
$000F Reserved
Write:

$0010 - $0014 MMC map 1 of 4 (Core User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0
$0010 INITRM RAM15 RAM14 RAM13 RAM12 RAM11 RAMHAL
Write:
Read: 0 0 0 0
$0011 INITRG REG14 REG13 REG12 REG11
Write:
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

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Device User Guide — 9S12C32DGV1/D V01.14

$0010 - $0014 MMC map 1 of 4 (Core User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0
$0012 INITEE EE15 EE14 EE13 EE12 EE11 EEON
Write:
Read: 0 0 0 0
$0013 MISC EXSTR1 EXSTR0 ROMHM ROMON
Write:
Read: 0 0 0 0 0 0 0 0
$0014 Reserved
Write:

$0015 - $0016 INT map 1 of 2 (Core User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0
$0015 ITCR WRINT ADR3 ADR2 ADR1 ADR0
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Write:
Read:
$0016 ITEST INTE INTC INTA INT8 INT6 INT4 INT2 INT0
Write:

$0017 - $0017 MMC map 2 of 4 (Core User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0 0 0 0 0 0
$0017 Reserved
Write:

$0018 - $0018 Miscellaneous Peripherals (Device User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0 0 0 0 0 0
$0018 Reserved
Write:

$0019 - $0019 VREG3V3 (Voltage Regulator)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0 0 0 LVDS
$0019 VREGCTRL LVIE LVIF
Write:

$001A - $001B Miscellaneous Peripherals (Device User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8
$001A PARTIDH
Write:
Read: ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
$001B PARTIDL
Write:

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Device User Guide — 9S12C32DGV1/D V01.14

$001C - $001D MMC map 3 of 4 (Core User Guide, Device User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: reg_sw0 0 eep_sw1 eep_sw0 0 ram_sw2 ram_sw1 ram_sw0
$001C MEMSIZ0
Write:
Read: rom_sw1 rom_sw0 0 0 0 0 pag_sw1 pag_sw0
$001D MEMSIZ1
Write:

$001E - $001E MEBI map 2 of 3 (Core User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0 0 0 0
$001E INTCR IRQE IRQEN
Write:
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$001F - $001F INT map 2 of 2 (Core User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0
$001F HPRIO PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1
Write:

$0020 - $002F DBG (including BKP) map 1 of 1 (Core User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DBGC1 read 0
$0020 DBGEN ARM TRGSEL BEGIN DBGBRK CAPMOD
- write
DBGSC read AF BF CF 0
$0021 TRG
- write
DBGTBH read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
$0022
- write
DBGTBL read Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0023
- write
DBGCNT read TBF 0 CNT
$0024
- write
DBGCCX read
$0025 PAGSEL EXTCMP
- write
DBGCCH read
$0026 Bit 15 14 13 12 11 10 9 Bit 8
write
DBGCCL read
$0027 Bit 7 6 5 4 3 2 1 Bit 0
- write
DBGC2 read
$0028 BKABEN FULL BDM TAGAB BKCEN TAGC RWCEN RWC
BKPCT0 write
DBGC3 read
$0029 BKAMBH BKAMBL BKBMBH BKBMBL RWAEN RWA RWBEN RWB
BKPCT1 write
DBGCAX read
$002A PAGSEL EXTCMP
BKP0X write
DBGCAH read
$002B Bit 15 14 13 12 11 10 9 Bit 8
BKP0H write

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Device User Guide — 9S12C32DGV1/D V01.14

$0020 - $002F DBG (including BKP) map 1 of 1 (Core User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DBGCAL read
$002C Bit 7 6 5 4 3 2 1 Bit 0
BKP0L write
DBGCBX read
$002D PAGSEL EXTCMP
BKP1X write
DBGCBH read
$002E Bit 15 14 13 12 11 10 9 Bit 8
BKP1H write
DBGCBL read
$002F Bit 7 6 5 4 3 2 1 Bit 0
BKP1L write

$0030 - $0031 MMC map 4 of 4 (Core User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
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Read: 0 0
$0030 PPAGE PIX5 PIX4 PIX3 PIX2 PIX1 PIX0
Write:
Read: 0 0 0 0 0 0 0 0
$0031 Reserved
Write:

$0032 - $0033 MEBI map 3 of 3 (Core User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0 0 0 0 0 0
$0032 Reserved
Write:
$0033 Reserved Read: 0 0 0 0 0 0 0 0

$0034 - $003F CRG (Clock and Reset Generator)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0
$0034 SYNR SYN5 SYN4 SYN3 SYN2 SYN1 SYN0
Write:
Read: 0 0 0 0
$0035 REFDV REFDV3 REFDV2 REFDV1 REFDV0
Write:
CTFLG Read: TOUT7 TOUT6 TOUT5 TOUT4 TOUT3 TOUT2 TOUT1 TOUT0
$0036
TEST ONLY Write:
Read: 0 LOCK TRACK SCM
$0037 CRGFLG RTIF PROF LOCKIF SCMIF
Write:
Read: 0 0 0 0 0
$0038 CRGINT RTIE LOCKIE SCMIE
Write:
Read:
$0039 CLKSEL PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI
Write:
Read: 0
$003A PLLCTL CME PLLON AUTO ACQ PRE PCE SCME
Write:
Read: 0
$003B RTICTL RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
Write:
Read: 0 0 0
$003C COPCTL WCOP RSBCK CR2 CR1 CR0
Write:

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Device User Guide — 9S12C32DGV1/D V01.14

$0034 - $003F CRG (Clock and Reset Generator)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FORBYP Read: 0 0 0 0
$003D RTIBYP COPBYP PLLBYP FCM
TEST ONLY Write:
CTCTL Read: TCTL7 TCTL6 TCTL5 TCTL4 TCLT3 TCTL2 TCTL1 TCTL0
$003E
TEST ONLY Write:
Read: 0 0 0 0 0 0 0 0
$003F ARMCOP
Write: Bit 7 6 5 4 3 2 1 Bit 0

$0040 - $006F TIM (Timer 16 Bit 8 Channels)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$0040 TIOS IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0
Write:
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Read: 0 0 0 0 0 0 0 0
$0041 CFORC
Write: FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0
Read:
$0042 OC7M OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0
Write:
Read:
$0043 OC7D OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0
Write:
Read: Bit 15 14 13 12 11 10 9 Bit 8
$0044 TCNT (hi)
Write:
Read: Bit 7 6 5 4 3 2 1 Bit 0
$0045 TCNT (lo)
Write:
Read: 0 0 0 0
$0046 TSCR1 TEN TSWAI TSFRZ TFFCA
Write:
Read:
$0047 TTOV TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0
Write:
Read:
$0048 TCTL1 OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4
Write:
Read:
$0049 TCTL2 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0
Write:
Read:
$004A TCTL3 EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
Write:
Read:
$004B TCTL4 EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
Write:
Read:
$004C TIE C7I C6I C5I C4I C3I C2I C1I C0I
Write:
Read: 0 0 0
$004D TSCR2 TOI TCRE PR2 PR1 PR0
Write:
Read:
$004E TFLG1 C7F C6F C5F C4F C3F C2F C1F C0F
Write:
Read: 0 0 0 0 0 0 0
$004F TFLG2 TOF
Write:
Read:
$0050 TC0 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$0051 TC0 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:

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Device User Guide — 9S12C32DGV1/D V01.14

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$0052 TC1 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$0053 TC1 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0054 TC2 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$0055 TC2 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0056 TC3 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$0057 TC3 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0058 TC4 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
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Read:
$0059 TC4 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$005A TC5 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$005B TC5 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$005C TC6 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$005D TC6 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$005E TC7 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$005F TC7 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read: 0
$0060 PACTL PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI
Write:
Read: 0 0 0 0 0 0
$0061 PAFLG PAOVF PAIF
Write:
Read:
$0062 PACNT (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$0063 PACNT (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read: 0 0 0 0 0 0 0 0
$0064 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0065 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0066 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0067 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0068 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0069 Reserved
Write:

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Device User Guide — 9S12C32DGV1/D V01.14

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0 0 0 0 0 0
$006A Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$006B Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$006C Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$006D Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$006E Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$006F Reserved
Write:
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$0070 - $007F Reserved

$0070 Read: 0 0 0 0 0 0 0 0
Reserved
- $007F Write:

$0080 - $009F ATD (Analog to Digital Converter 10 Bit 8 Channel)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0 0 0 0 0 0
$0080 ATDCTL0
Write:
Read: 0 0 0 0 0 0 0 0
$0081 ATDCTL1
Write:
Read: ASCIF
$0082 ATDCTL2 ADPU AFFC AWAI ETRIGLE ETRIGP ETRIG ASCIE
Write:
Read: 0
$0083 ATDCTL3 S8C S4C S2C S1C FIFO FRZ1 FRZ0
Write:
Read:
$0084 ATDCTL4 SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0
Write:
Read: 0
$0085 ATDCTL5 DJM DSGN SCAN MULT CC CB CA
Write:
Read: 0 0 CC2 CC1 CC0
$0086 ATDSTAT0 SCF ETORF FIFOR
Write:
Read: 0 0 0 0 0 0 0 0
$008B Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0088 ATDTEST0
Write:
Read: 0 0 0 0 0 0 0
$0089 ATDTEST1 SC
Write:
Read: 0 0 0 0 0 0 0 0
$008A Reserved
Write:
Read: CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0
$008B ATDSTAT1
Write:
Read: 0 0 0 0 0 0 0 0
$008C Reserved
Write:

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Device User Guide — 9S12C32DGV1/D V01.14

$0080 - $009F ATD (Analog to Digital Converter 10 Bit 8 Channel)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$008D ATDDIEN Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read: 0 0 0 0 0 0 0 0
$008E Reserved
Write:
Read: Bit7 6 5 4 3 2 1 BIT 0
$008F PORTAD0
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$0090 ATDDR0H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$0091 ATDDR0L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$0092 ATDDR1H
Write:
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Read: Bit7 Bit6 0 0 0 0 0 0

$0093 ATDDR1L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$0094 ATDDR2H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$0095 ATDDR2L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$0096 ATDDR3H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$0097 ATDDR3L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$0098 ATDDR4H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$0099 ATDDR4L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$009A ATDDR5H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$009B ATDDR5L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$009C ATDDR6H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$009D ATDDR6L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$009E ATDDR7H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$009F ATDDR7L
Write:

$00A0 - $00C7 Reserved

$00A0 Read: 0 0 0 0 0 0 0 0
Reserved
- $00C7 Write:

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Device User Guide — 9S12C32DGV1/D V01.14

$00C8 - $00CF SCI (Asynchronous Serial Interface)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0
$00C8 SCIBDH SBR12 SBR11 SBR10 SBR9 SBR8
Write:
Read:
$00C9 SCIBDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
Write:
Read:
$00CA SCICR1 LOOPS SCISWAI RSRC M WAKE ILT PE PT
Write:
Read:
$00CB SCICR2 TIE TCIE RIE ILIE TE RE RWU SBK
Write:
Read: TDRE TC RDRF IDLE OR NF FE PF
$00CC SCISR1
Write:
Read: 0 0 0 0 0 RAF
$00CD SCISR2 BRK13 TXDIR
Write:
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Read: R8 0 0 0 0 0 0
$00CE SCIDRH T8
Write:
Read: R7 R6 R5 R4 R3 R2 R1 R0
$00CF SCIDRL
Write: T7 T6 T5 T4 T3 T2 T1 T0

$00D0 - $00D7 Reserved

$00D0 Read: 0 0 0 0 0 0 0 0
Reserved
- $00D7 Write:

$00D8 - $00DF SPI (Serial Peripheral Interface)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$00D8 SPICR1 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
Write:
Read: 0 0 0 0
$00D9 SPICR2 MODFEN BIDIROE SPISWAI SPC0
Write:
Read: 0 0
$00DA SPIBR SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0
Write:
Read: SPIF 0 SPTEF MODF 0 0 0 0
$00DB SPISR
Write:
Read: 0 0 0 0 0 0 0 0
$00DC Reserved
Write:
Read:
$00DD SPIDR Bit7 6 5 4 3 2 1 Bit0
Write:
Read: 0 0 0 0 0 0 0 0
$00DE Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$00DF Reserved
Write:

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Device User Guide — 9S12C32DGV1/D V01.14

$00E0 - $00FF PWM (Pulse Width Modulator)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0
$00E0 PWME PWME5 PWME4 PWME3 PWME2 PWME1 PWME0
Write:
Read: 0 0
$00E1 PWMPOL PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0
Write:
Read: 0 0
$00E2 PWMCLK PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0
Write:
Read: 0 0
$00E3 PWMPRCLK PCKB2 PCKB1 PCKB0 PCKA2 PCKA1 PCKA0
Write:
Read: 0 0
$00E4 PWMCAE CAE5 CAE4 CAE3 CAE2 CAE1 CAE0
Write:
Read: 0 0 0
$00E5 PWMCTL CON45 CON23 CON01 PSWAI PFRZ
Write:
PWMTST Read: 0 0 0 0 0 0 0 0
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$00E6
Test Only Write:
Read: 0 0 0 0 0 0 0 0
$00E7 PWMPRSC
Write:
Read:
$00E8 PWMSCLA Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$00E9 PWMSCLB Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read: 0 0 0 0 0 0 0 0
$00EA PWMSCNTA
Write:
Read: 0 0 0 0 0 0 0 0
$00EB PWMSCNTB
Write:
Read: Bit 7 6 5 4 3 2 1 Bit 0
$00EC PWMCNT0
Write: 0 0 0 0 0 0 0 0
Read: Bit 7 6 5 4 3 2 1 Bit 0
$00ED PWMCNT1
Write: 0 0 0 0 0 0 0 0
Read: Bit 7 6 5 4 3 2 1 Bit 0
$00EE PWMCNT2
Write: 0 0 0 0 0 0 0 0
Read: Bit 7 6 5 4 3 2 1 Bit 0
$00EF PWMCNT3
Write: 0 0 0 0 0 0 0 0
Read: Bit 7 6 5 4 3 2 1 Bit 0
$00F0 PWMCNT4
Write: 0 0 0 0 0 0 0 0
Read: Bit 7 6 5 4 3 2 1 Bit 0
$00F1 PWMCNT5
Write: 0 0 0 0 0 0 0 0
Read:
$00F2 PWMPER0 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$00F3 PWMPER1 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$00F4 PWMPER2 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$00F5 PWMPER3 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$00F6 PWMPER4 Bit 7 6 5 4 3 2 1 Bit 0
Write:

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Device User Guide — 9S12C32DGV1/D V01.14

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$00F7 PWMPER5 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$00F8 PWMDTY0 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$00F9 PWMDTY1 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$00FA PWMDTY2 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$00FB PWMDTY3 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$00FC PWMDTY4 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$00FD PWMDTY5 Bit 7 6 5 4 3 2 1 Bit 0
Write:
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Read: 0 0 0 0 0 0 0 0
$00FE Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$00FF Reserved
Write:

$0100 - $010F Flash Control Register (fts32k)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: FDIVLD
$0100 FCLKDIV PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0
Write:
Read: KEYEN1 KEYEN0 NV5 NV4 NV3 NV2 SEC1 SEC0
$0101 FSEC
Write:
Read: 0 0 0
$0102 FTSTMOD 0 0 0 WRALL 0
Write:
Read: 0 0 0
$0103 FCNFG CBEIE CCIE KEYACC BKSEL1 BKSEL0
Write:
Read:
$0104 FPROT FPOPEN NV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0
Write:
Read: CCIF 0 0 0
$0105 FSTAT CBEIF PVIOL ACCERR BLANK
Write:
Read: 0 0 0 0
$0106 FCMD CMDB6 CMDB5 CMDB2 CMDB0
Write:
Reserved for Read: 0 0 0 0 0 0 0 0
$0107
Factory Test Write:
Reserved for Read: 0 0 0 0 0 0 0 0
$0108
Factory Test Write:
Reserved for Read: 0 0 0 0 0 0 0 0
$0109
Factory Test Write:
Reserved for Read: 0 0 0 0 0 0 0 0
$010A
Factory Test Write:
Reserved for Read: 0 0 0 0 0 0 0 0
$010B
Factory Test Write:

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$0100 - $010F Flash Control Register (fts32k)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0 0 0 0 0 0
$010C Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$010D Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$010E Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$010F Reserved
Write:

$0110 - $013F Reserved

$0110 Read: 0 0 0 0 0 0 0 0
Reserved
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- $003F Write:

$0140 - $017F CAN (Motorola Scalable CAN - MSCAN)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: RXACT SYNCH
$0140 CANCTL0 RXFRM CSWAI TIME WUPE SLPRQ INITRQ
Write:
Read: 0 SLPAK INITAK
$0141 CANCTL1 CANE CLKSRC LOOPB LISTEN WUPM
Write:
Read:
$0142 CANBTR0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
Write:
Read:
$0143 CANBTR1 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
Write:
Read: RSTAT1 RSTAT0 TSTAT1 TSTAT0
$0144 CANRFLG WUPIF CSCIF OVRIF RXF
Write:
Read:
$0145 CANRIER WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE
Write:
Read: 0 0 0 0 0
$0146 CANTFLG TXE2 TXE1 TXE0
Write:
Read: 0 0 0 0 0
$0147 CANTIER TXEIE2 TXEIE1 TXEIE0
Write:
Read: 0 0 0 0 0
$0148 CANTARQ ABTRQ2 ABTRQ1 ABTRQ0
Write:
Read: 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0
$0149 CANTAAK
Write:
Read: 0 0 0 0 0
$014A CANTBSEL TX2 TX1 TX0
Write:
Read: 0 0 0 IDHIT2 IDHIT1 IDHIT0
$014B CANIDAC IDAM1 IDAM0
Write:
Read: 0 0 0 0 0 0 0 0
$014C Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$014D Reserved
Write:

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$0140 - $017F CAN (Motorola Scalable CAN - MSCAN)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
$014E CANRXERR
Write:
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
$014F CANTXERR
Write:
$0150 - CANIDAR0 - Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
$0153 CANIDAR3 Write:
$0154 - CANIDMR0 - Read:
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
$0157 CANIDMR3 Write:
$0158 - CANIDAR4 - Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
$015B CANIDAR7 Write:
$015C - CANIDMR4 - Read:
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
$015F CANIDMR7 Write:
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$0160 - Read: FOREGROUND RECEIVE BUFFER see Table 1-2

CANRXFG
$016F Write:
$0170 - Read:
CANTXFG FOREGROUND TRANSMIT BUFFER see Table 1-2
$017F Write:

Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Extended IDRead: ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
$xxx0 Standard IDRead: ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3
CANxRIDR0 Write:
Extended IDRead: ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15
$xxx1 Standard IDRead: ID2 ID1 ID0 RTR IDE=0
CANxRIDR1 Write:
Extended IDRead: ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7
$xxx2 Standard IDRead:
CANxRIDR2 Write:
Extended IDRead: ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR
$xxx3 Standard IDRead:
CANxRIDR3 Write:
$xxx4- CANxRDSR0 - Read: DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
$xxxB CANxRDSR7 Write:
Read: DLC3 DLC2 DLC1 DLC0
$xxxC CANRxDLR
Write:
Read:
$xxxD Reserved
Write:
Read: TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8
$xxxE CANxRTSRH
Write:
Read: TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0
$xxxF CANxRTSRL
Write:
Extended ID Read:
ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
CANxTIDR0 Write:
$xx10
Standard ID Read:
ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3
Write:

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Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Extended ID Read:
ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15
CANxTIDR1 Write:
$xx11
Standard ID Read:
ID2 ID1 ID0 RTR IDE=0
Write:
Extended ID Read:
ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7
CANxTIDR2 Write:
$xx12
Standard ID Read:
Write:
Extended ID Read:
ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR
CANxTIDR3 Write:
$xx13
Standard ID Read:
Write:
$xx14- CANxTDSR0 - Read:
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
$xx1B CANxTDSR7 Write:
Read:
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$xx1C CANxTDLR DLC3 DLC2 DLC1 DLC0

Write:
Read:
$xx1D CONxTTBPR PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0
Write:
Read: TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8
$xx1E CANxTTSRH
Write:
Read: TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0
$xx1F CANxTTSRL
Write:

$0180 - $023F Reserved

$0180 Read: 0 0 0 0 0 0 0 0
Reserved
- $023F Write:

$0240 - $027F PIM (Port Interface Module)

Read:
$0240 PTT PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0
Write:
Read: PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0
$0241 PTIT
Write:
Read:
$0242 DDRT DDRT7 DDRT7 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
Write:
Read:
$0243 RDRT RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0
Write:
Read:
$0244 PERT PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0
Write:
Read:
$0245 PPST PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0
Write:
Read: 0 0 0 0 0 0 0 0
$0246 Reserved
Write:
Read: 0 0 0
$0247 MODRR MODRR4 MODRR3 MODRR2 MODRR1 MODRR0
Write:
Read: 0 0 0 0
$0248 PTS PTS3 PTS2 PTS1 PTS0
Write:

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Read: 0 0 0 0 PTIS3 PTIS2 PTIS1 PTIS0

$0249 PTIS
Write:
Read: 0 0 0 0
$024A DDRS DDRS3 DDRS2 DDRS1 DDRS0
Write:
Read: 0 0 0 0
$024B RDRS RDRS3 RDRS2 RDRS1 RDRS0
Write:
Read: 0 0 0 0
$024C PERS PERS3 PERS2 PERS1 PERS0
Write:
Read: 0 0 0 0
$024D PPSS PPSS3 PPSS2 PPSS1 PPSS0
Write:
Read: 0 0 0 0
$024E WOMS WOMS3 WOMS2 WOMS1 WOMS0
Write:
Read: 0 0 0 0 0 0 0 0
$024F Reserved
Write:
Read: 0 0
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$0250 PTM PTM5 PTM4 PTM3 PTM2 PTM1 PTM0

Write:
Read: 0 0 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0
$0251 PTIM
Write:
Read: 0 0
$0252 DDRM DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0
Write:
Read: 0 0
$0253 RDRM RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0
Write:
Read: 0 0
$0254 PERM PERM5 PERM4 PERM3 PERM2 PERM1 PERM0
Write:
Read: 0 0
$0255 PPSM PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0
Write:
Read: 0 0
$0256 WOMM WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0
Write:
Read: 0 0 0 0 0 0 0 0
$0257 Reserved
Write:
Read:
$0258 PTP PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
Write:
Read: PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0
$0259 PTIP
Write:
Read:
$025A DDRP DDRP7 DDRP7 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
Write:
Read:
$025B RDRP RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0
Write:
Read:
$025C PERP PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0
Write:
Read:
$025D PPSP PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSS0
Write:
Read:
$025E PIEP PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0
Write:
Read:
$025F PIFP PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0
Write:
Read: 0 0 0 0 0 0 0 0
$0260 Reserved
Write:

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Read: 0 0 0 0 0 0 0 0
$0261 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0262 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0263 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0264 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0265 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0266 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0267 Reserved
Write:
Read: 0 0 0 0 0 0
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$0268 PTJ PTJ7 PTJ6

Write:
Read: PTIJ7 PTIJ6 0 0 0 0 0 0
$0269 PTIJ
Write:
Read: 0 0 0 0 0 0
$026A DDRJ DDRJ7 DDRJ7
Write:
Read: 0 0 0 0 0 0
$026B RDRJ RDRJ7 RDRJ6
Write:
Read: 0 0 0 0 0 0
$026C PERJ PERJ7 PERJ6
Write:
Read: 0 0 0 0 0 0
$026D PPSJ PPSJ7 PPSJ6
Write:
Read: 0 0 0 0 0 0
$026E PIEJ PIEJ7 PIEJ6
Write:
Read: 0 0 0 0 0 0
$026F PIFJ PIFJ7 PIFJ6
Write:
Read:
$0270 PTAD PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
Write:
Read: PTIAD7 PTIAD6 PTIAD5 PTIAD4 PTIAD3 PTIAD2 PTIAD1 PTIJ7
$0271 PTIAD
Write:
Read:
$0272 DDRAD DDRAD7 DDRAD6 DDRAD5 DDRAD4 DDRAD3 DDRAD2 DDRAD1 DDRAD0
Write:
Read:
$0273 RDRAD RDRAD7 RDRAD6 RDRAD5 RDRAD4 RDRAD3 RDRAD2 RDRAD1 RDRAD0
Write:
Read:
$0274 PERAD PERAD7 PERAD6 PERAD5 PERAD4 PERAD3 PERAD2 PERAD1 PERAD0
Write:
Read:
$0275 PPSAD PPSAD7 PPSAD6 PPSAD5 PPSAD4 PPSAD3 PPSAD2 PPSAD1 PPSAD0
Write:
$0276- Read: 0 0 0 0 0 0 0 0
Reserved
$027F Write:

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Device User Guide — 9S12C32DGV1/D V01.14

$0280 - $03FF Reserved space

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0280 Read: 0 0 0 0 0 0 0 0
Reserved
- $2FF Write:
$0300 - Read: 0 0 0 0 0 0 0 0
Unimplemented
$03FF Write:

1.7 Part ID Assignments

The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after
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reset). The read-only value is a unique part ID for each revision of the chip. Table 1-3 shows the assigned
part ID number.

Table 1-3 Assigned Part ID Numbers

Device Mask Set Number Part ID1
MC9S12C32 0L45J $3300
MC9S12C32 1L45J2 $3300
NOTES:
1. The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-8: Minor family identifier
Bit 7-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor - non full - mask set revision
2. Both Masksets 0L45J and 1L45J use the same Part ID number.

The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C
and $001D after reset). Table 1-4 shows the read-only values of these registers. Refer to section Module
Mapping and Control (MMC) of HCS12 Core User Guide for further details.
Table 1-4 Memory size registers
Register name Value1
MEMSIZ0 $00
MEMSIZ1 $80
NOTES:
1. Since no paging is supported on the MC9S12C32, only
a 64K range is accessible.

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Device User Guide — 9S12C32DGV1/D V01.14

Section 2 Signal Description

2.1 Device Pinout

PP6/KWP6/ROMCTL
PP4/KWP4/PW4
PP5/KWP5/PW5

PM0/RXCAN
PM1/TXCAN
PP7/KWP7

PM2/MISO

PM4/MOSI

PJ6/KWJ6
PJ7/KWJ7
PM5/SCK

PS0/RXD
PS1/TXD
PM3/SS
VDDX
VSSX

VSSA
VRL
PS3
PS2
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80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PW3/KWP3/PP3 1 60 VRH
PW2/KWP2/PP2 2 59 VDDA
PW1/KWP1/PP1 3 58 PAD07/AN07
PW0/KWP0/PP0 4 57 PAD06/AN06
PW0/IOC0/PT0 5 56 PAD05/AN05
PW1/IOC1/PT1 6 55 PAD04/AN04
PW2/IOC2/PT2 7 54 PAD03/AN03
PW3/IOC3/PT3 8 53 PAD02/AN02
VDD1 9 52 PAD01/AN01
VSS1 10 MC9S12C32 51 PAD00/AN00
PW4/IOC4/PT4 11 80 QFP 50 VSS2
IOC5/PT5 12 49 VDD2
IOC6/PT6 13 48 PA7/ADDR15/DATA15
IOC7/PT7 14 47 PA6/ADDR14/DATA14
MODC/TAGHI/BKGD 15 46 PA5/ADDR13/DATA13
ADDR0/DATA0/PB0 16 45 PA4/ADDR12/DATA12
ADDR1/DATA1/PB1 17 44 PA3/ADDR11/DATA11
ADDR2/DATA2/PB2 18 43 PA2/ADDR10/DATA10
ADDR3/DATA3/PB3 19 42 PA1/ADDR9/DATA9
ADDR4/DATA4/PB4 20 41 PA0/ADDR8/DATA8
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
XCLKS/NOACC/PE7
ADDR5/DATA5/PB5
ADDR6/DATA6/PB6
ADDR7/DATA7/PB7

MODB/IPIPE1/PE6
MODA/IPIPE0/PE5
ECLK/PE4
VSSR
VDDR
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST/VPP
LSTRB/TAGLO/PE3
R/W/PE2
IRQ/PE1
XIRQ/PE0

Signals shown in Bold are not available on the 52 or 48 Pin Package

Signals shown in Bold Italic are available in the 52, but not the 48 Pin Package

Figure 2-1 Pin Assignments in 80 QFP for MC9S12C32

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PP4/KWP4/PW4
PP5/KWP5/PW5

PM0/RXCAN
PM1/TXCAN
PM2/MISO

PM4/MOSI
PM5/SCK

PS0/RXD
PS1/TXD
PM3/SS
VDDX
VSSX

VSSA
52
51
50
49
48
47
46
45
44
43
42
41
40
PW3/KWP3/PP3 1 39 VRH
PW0/IOC0/PT0 2 38 VDDA
PW1/IOC1/PT1 3 37 PAD07/AN07
PW2/IOC2/PT2 4 36 PAD06/AN06
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PW3/IOC3/PT3 5 35 PAD05/AN05
VDD1 6 34 PAD04/AN04
VSS1 7 MC9S12C32 33 PAD03/AN03
52 QFP
PW4/IOC4/PT4 8 32 PAD02/AN02
IOC5/PT5 9 31 PAD01/AN01
IOC6/PT6 10 30 PAD00/AN00
IOC7/PT7 11 29 PA2
MODC/BKGD 12 28 PA1
PB4 13 27 PA0
14
15
16
17
18
19
20
21
22
23
24
25
26
XCLKS/PE7
ECLK/PE4
VSSR
VDDR
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST/VPP
IRQ/PE1
XIRQ/PE0

* Signals shown in Bold italic are not available on the 48 Pin Package

Figure 2-2 Pin assignments in 52 LQFP for MC9S12C32

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PM0/RXCAN
PM1/TXCAN
PP5/KWP5

PM2/MISO

PM4/MOSI
PM5/SCK

PS0/RXD
PS1/TXD
PM3/SS
VDDX
VSSX

VSSA
48
47
46
45
44
43
42
41
40
39
38
37
PW0/IOC0/PT0 1 36 VRH
PW1/IOC1/PT1 2 35 VDDA
PW2/IOC2/PT2 3 34 PAD07/AN07
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PW3/IOC3/PT3 4 33 PAD06/AN06
VDD1 5 32 PAD05/AN05
VSS1 6 MC9S12C32 31 PAD04/AN04
48 LQFP
PW4/IOC4/PT4 7 30 PAD03/AN03
IOC5/PT5 8 29 PAD02/AN02
IOC6/PT6 9 28 PAD01/AN01
IOC7/PT7 10 27 PAD00/AN00
MODC/BKGD 11 26 PA0
PB4 12 25 XIRQ/PE0
13
14
15
16
17
18
19
20
21
22
23
24
XCLKS/PE7
ECLK/PE4
VSSR
VDDR
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST/VPP
IRQ/PE1

Figure 2-3 Pin Assignments in 48 LQFP for MC9S12C32

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2.2 Signal Properties Summary

Table 2-1 Signal Properties
Internal Pull
Pin Name Pin Name Pin Name Power Resistor
Description
Function 1 Function 2 Function 3 Domain Reset
CTRL
State
EXTAL — — VDDPLL NA NA
Oscillator pins
XTAL — — VDDPLL NA NA
RESET — — VDDX None None External reset pin
XFC — — VDDPLL NA NA PLL loop filter pin
TEST VPP — VSSX NA NA Test pin only
BKGD MODC TAGHI VDDX Up Up Background debug, mode pin, tag signal high
PE7 NOACC XCLKS VDDX PUCR Up Port E I/O pin, access, clock select
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While RESET
PE6 IPIPE1 MODB VDDX Port E I/O pin and pipe status
pin is low: Down
While RESET
PE5 IPIPE0 MODA VDDX Port E I/O pin and pipe status
pin is low: Down
PE4 ECLK — VDDX PUCR Up Port E I/O pin, bus clock output
PE3 LSTRB TAGLO VDDX PUCR Up Port E I/O pin, low strobe, tag signal low
PE2 R/W — VDDX PUCR Up Port E I/O pin, R/W in expanded modes
PE1 IRQ — VDDX PUCR Up Port E input, external interrupt pin
PE0 XIRQ — VDDX PUCR Up Port E input, non-maskable interrupt pin
ADDR[15:1/
PA[7:3] — VDDX PUCR Disabled Port A I/O pin & multiplexed address/data
DATA[15:1]
ADDR[10:9/
PA[2:1] — VDDX PUCR Disabled Port A I/O pin & multiplexed address/data
DATA[10:9]
ADDR[8]/
PA[0] — VDDX PUCR Disabled Port A I/O pin & multiplexed address/data
DATA[8]
ADDR[7:5]/
PB[7:5] — VDDX PUCR Disabled Port B I/O pin & multiplexed address/data
DATA[7:5]
ADDR[4]/
PB[4] — VDDX PUCR Disabled Port B I/O pin & multiplexed address/data
DATA[4]
ADDR[3:0]/
PB[3:0] — VDDX PUCR Disabled Port B I/O pin & multiplexed address/data
DATA[3:0]
PERAD/P
PAD[7:0] AN[7:0] — VDDA Disabled Port AD I/O pins and ATD inputs
PSAD
PERP/
PP[7] KWP[7] — VDDX Disabled Port P I/O Pins and keypad wake-up
PPSP
PERP/ Port P I/O Pins, keypad wake-up and ROMON
PP[6] KWP[6] ROMCTL VDDX Disabled
PPSP enable.
PERP/
PP[5] KWP[5] PW5 VDDX Disabled Port P I/O Pin, keypad wake-up, PW5 output
PPSP
PERP/
PP[4:3] KWP[4:3] PW[4:3] VDDX Disabled Port P I/O Pin, keypad wake-up, PWM output
PPSP
PERP/
PP[2:0] KWP[2:0] PW[2:0] VDDX Disabled Port P I/O Pins, keypad wake-up, PWM outputs
PPSP
PERJ/
PJ[7:6] KWJ[7:6] — VDDX Disabled Port J I/O Pins and keypad wake-up
PPSJ

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Internal Pull
Pin Name Pin Name Pin Name Power Resistor
Description
Function 1 Function 2 Function 3 Domain Reset
CTRL
State
PERM/
PM5 SCK — VDDX Disabled Port M I/O Pin and SPI SCK signal
PPSM
PERM/
PM4 MOSI — VDDX Disabled Port M I/O Pin and SPI MOSI signal
PPSM
PERM/
PM3 SS — VDDX Disabled Port M I/O Pin and SPI SS signal
PPSM
PERM/
PM2 MISO — VDDX Disabled Port M I/O Pin and SPI MISO signal
PPSM
PERM/
PM1 TXCAN — VDDX Disabled Port M I/O Pin and CAN transmit signal
PPSM
PERM/
PM0 RXCAN — VDDX Disabled Port M I/O Pin and CAN receive signal
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PPSM
PERS/
PS[3:2] — — VDDX Up Port S I/O Pins
PPSS
PERS/
PS1 TXD — VDDX Up Port S I/O Pin and SCI transmit signal
PPSS
PERS/
PS0 RXD — VDDX Up Port S I/O Pin and SCI receive signal
PPSS
PERT/
PT[7:5] IOC[7:5] — VDDX Disabled Port T I/O Pins shared with timer (TIM)
PPST
PERT/
PT[4:0] IOC[4:0] PW[4:0] VDDX Disabled Port T I/O Pins shared with timer and PWM
PPST

2.2.1 Pin Initialization for 48 & 52 Pin LQFP bond-out versions

Not Bonded Pins If the port pins are not bonded out in the chosen package the user should initialize the
registers to be inputs with enabled pull resistance to avoid excess current consumption. This applies to the
following pins:
(48LQFP): Port A[7:1], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[4:0], Port J[7:6],
PortS[3:2]
(52LQFP): Port A[7:3], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[2:0], Port J[7:6],
PortS[3:2]

2.3 Detailed Signal Descriptions

2.3.1 EXTAL, XTAL — Oscillator Pins

EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.

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2.3.2 RESET — External Reset Pin

RESET is an active low bidirectional control signal that acts as an input to initialize the MCU to a known
start-up state. It also acts as an open-drain output to indicate that an internal failure has been detected in
either the clock monitor or COP watchdog circuit. External circuitry connected to the RESET pin should
not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic one
within 32 ECLK cycles after the low drive is released. Upon detection of any reset, an internal circuit
drives the RESET pin low and a clocked reset sequence controls when the MCU can begin normal
processing.

2.3.3 TEST / VPP — Test Pin

This pin is reserved for test and must be tied to VSS in all applications.
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2.3.4 XFC — PLL Loop Filter Pin

Dedicated pin used to create the PLL loop filter. See CRG BUG for more detailed information.PLL loop
filter. Please ask your Motorola representative for the interactive application note to compute PLL loop
filter elements. Any current leakage on this pin must be avoided.

XFC

R0
CP
MCU
CS

VDDPLL VDDPLL

Figure 2-4 PLL Loop Filter Connections

2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High & Mode Pin

The BKGD / TAGHI / MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is also used as a MCU operating mode select pin at the rising edge during reset, when
the state of this pin is latched to the MODC bit.

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2.3.6 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins

PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus. PA[7:1] pins are not available in the 48 package
version. PA[7:3] are not available in the 52 pin package version.

2.3.7 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins

PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus. PB[7:5] and PB[3:0] pins are not available in the
48 nor 52 pin package version.

2.3.8 PE7 / NOACC / XCLKS — Port E I/O Pin 7

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PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC
signal, when enabled, is used to indicate that the current bus cycle is an unused or “free” cycle. This signal
will assert when the CPU is not using the bus.The XCLKS is an input signal which controls whether a
crystal in combination with the internal Colpitts (low power) oscillator is used or whether Pierce
oscillator/external clock circuitry is used. The state of thispin is latched at the rising edge of RESET. If the
input is a logic low the EXTAL pin is configured for an external clock drive or a Pierce Oscillator. If input
is a logic high a Colpitts oscillator circuit is configured on EXTAL and XTAL. Since this pin is an input
with a pull-up device during reset, if the pin is left floating, the default configuration is a Colpitts oscillator
circuit on EXTAL and XTAL.

EXTAL
CDC *
MCU C1 Crystal or
ceramic resonator

XTAL
C2

VSSPLL

* Due to the nature of a translated ground Colpitts oscillator a

DC voltage bias is applied to the crystal
.Please contact the crystal manufacturer for crystal DC

Figure 2-5 Colpitts Oscillator Connections (PE7=1)

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Figure 2-6 Pierce Oscillator Connections (PE7=0)

EXTAL
C1
MCU RB Crystal or
*
ceramic resonator
RS
XTAL
C2
VSSPLL
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* Rs can be zero (shorted) when use with higher frequency crystals.

Refer to manufacturer’s data.

Figure 2-7 External Clock Connections (PE7=0)

EXTAL CMOS-COMPATIBLE
EXTERNAL OSCILLATOR
(VDDPLL-Level)
MCU

XTAL not connected

2.3.9 PE6 / MODB / IPIPE1 — Port E I/O Pin 6

PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active
when RESET is low. PE[6] is not available in the 48 / 52 pin package versions.

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2.3.10 PE5 / MODA / IPIPE0 — Port E I/O Pin 5

PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active
when RESET is low. This pin is not available in the 48 / 52 pin package versions.

2.3.11 PE4 / ECLK— Port E I/O Pin [4] / E-Clock Output

ECLK is the output connection for the internal bus clock. It is used to demultiplex the address and data in
expanded modes and is used as a timing reference. ECLK frequency is equal to 1/2 the crystal frequency
out of reset. The ECLK pin is initially configured as ECLK output with stretch in all expanded modes. The
E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in
the MODE register and the ESTR bit in the EBICTL register. All clocks, including the E clock, are halted
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when the MCU is in STOP mode. It is possible to configure the MCU to interface to slow external
memory. ECLK can be stretched for such accesses. Reference the MISC register (EXSTR[1:0] bits) for
more information. In normal expanded narrow mode, the E clock is available for use in external select
decode logic or as a constant speed clock for use in the external application system.

2.3.12 PE3 / LSTRB — Port E I/O Pin [3] / Low-Byte Strobe (LSTRB)

In all modes this pin can be used as a general-purpose I/O and is an input with an active pull-up out of
reset. If the strobe function is required, it should be enabled by setting the LSTRE bit in the PEAR register.
This signal is used in write operations. Therefore external low byte writes will not be possible until this
function is enabled. This pin is also used as TAGLO in Special Expanded modes and is multiplexed with
the LSTRB function. This pin is not available in the 48 / 52 pin package versions.

2.3.13 PE2 / R/W — Port E I/O Pin [2] / Read/Write

In all modes this pin can be used as a general-purpose I/O and is an input with an active pull-up out of
reset. If the read/write function is required it should be enabled by setting the RDWE bit in the PEAR
register. External writes will not be possible until enabled. This pin is not available in the 48 / 52 pin
package versions.

2.3.14 PE1 / IRQ — Port E input Pin [1] / Maskable Interrupt Pin

The IRQ input provides a means of applying asynchronous interrupt requests to the MCU. Either falling
edge-sensitive triggering or level-sensitive triggering is program selectable (INTCR register). IRQ is
always enabled and configured to level-sensitive triggering out of reset. It can be disabled by clearing
IRQEN bit (INTCR register). When the MCU is reset the IRQ function is masked in the condition code
register. This pin is always an input and can always be read. There is an active pull-up on this pin while in
reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR register.

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2.3.15 PE0 / XIRQ — Port E input Pin [0] / Non Maskable Interrupt Pin

The XIRQ input provides a means of requesting a non maskable interrupt after reset initialization. During
reset, the X bit in the condition code register (CCR) is set and any interrupt is masked until MCU software
enables it. Because the XIRQ input is level sensitive, it can be connected to a multiple-source wired-OR
network. This pin is always an input and can always be read. There is an active pull-up on this pin while
in reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR
register.

2.3.16 PAD[7:0] / AN[7:0] — Port AD I/O Pins [7:0]

PAD7-PAD0 are general purpose I/O pins and also analog inputs for the analog to digital converter.

2.3.17 PP[7] / KWP[7] — Port P I/O Pin [7]

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PP7 is a general purpose input or output pin, shared with the keypad interrupt function. When configured
as an input, it can generate interrupts causing the MCU to exit STOP or WAIT mode. This pin is not
available in the 48 / 52 pin package versions.

2.3.18 PP[6] / KWP[6]/ROMCTL — Port P I/O Pin [6]

PP6 is a general purpose input or output pin, shared with the keypad interrupt function. When configured
as an input, it can generate interrupts causing the MCU to exit STOP or WAIT mode. This pin is not
available in the 48 / 52 pin package versions. During MCU expanded modes of operation, this pin is used
to enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the
state of this pin is latched to the ROMON bit.
PP6=1 in emulation modes equates to ROMON =0 (ROM space externally mapped)
PP6=0 in expanded modes equates to ROMON =0 (ROM space externally mapped)

2.3.19 PP[5:0] / KWP[5:0] / PW[5:0] — Port P I/O Pins [5:0]

PP[5:0] are general purpose input or output pins, shared with the keypad interrupt function. When
configured as inputs, they can generate interrupts causing the MCU to exit STOP or WAIT mode.
PP[5:0] are also shared with the PWM output signals, PW[5:0]. Pins PP[2:0] are only available in the 80
pin package version. Pins PP[4:3] are only available in the 52 and 80 pin package version.

2.3.20 PJ[7:6] / KWJ[7:6] — Port J I/O Pins [7:6]

PJ[7:6] are general purpose input or output pins, shared with the keypad interrupt function. When
configured as inputs, they can generate interrupts causing the MCU to exit STOP or WAIT mode. These
pins are not available in the 48 pin package version nor in the 52 pin package version.

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2.3.21 PM5 / SCK — Port M I/O Pin 5

PM5 is a general purpose input or output pin and also the serial clock pin SCK for the Serial Peripheral
Interface (SPI).

2.3.22 PM4 / MOSI — Port M I/O Pin 4

PM4 is a general purpose input or output pin and also the master output (during master mode) or slave
input (during slave mode) pin for the Serial Peripheral Interface (SPI).

2.3.23 PM3 / SS — Port M I/O Pin 3

PM3 is a general purpose input or output pin and also the slave select pin SS for the Serial Peripheral
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Interface (SPI).

2.3.24 PM2 / MISO — Port M I/O Pin 2

PM2 is a general purpose input or output pin and also the master input (during master mode) or slave
output (during slave mode) pin for the Serial Peripheral Interface (SPI).

2.3.25 PM1 / TXCAN — Port M I/O Pin 1

PM1 is a general purpose input or output pin and the transmit pin TXCAN of the CAN module.

2.3.26 PM0 / RXCAN — Port M I/O Pin 0

PM0 is a general purpose input or output pin and the receive pin RXCAN of the CAN module.

2.3.27 PS[3:2] — Port S I/O Pins [3:2]

PS3 and PS2 are general purpose input or output pins. These pins are not available in the 48 / 52 pin
package versions.

2.3.28 PS1 / TXD — Port S I/O Pin 1

PS1 is a general purpose input or output pin and the transmit pin TXD of Serial Communication Interface
(SCI).

2.3.29 PS0 / RXD — Port S I/O Pin 0

PS0 is a general purpose input or output pin and the receive pin RXD of Serial Communication Interface
(SCI).

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2.3.30 PPT[7:5] / IOC[7:5] — Port T I/O Pins [7:5]

PT7-PT5 are general purpose input or output pins. They can also be configured as the timer system input cap-
ture or output compare pins IOC7-IOC5.

2.3.31 PT[4:0] / IOC[4:0] / PW[4:0]— Port T I/O Pins [4:0]

PT4-PT0 are general purpose input or output pins. They can also be configured as the timer system input cap-
ture or output compare pins IOC4-IOC0 or as the PWM outputs PW[4:0]/

2.4 Power Supply Pins

2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers
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External power and ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins
are loaded.

2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal
Voltage Regulator

External power and ground for I/O drivers and input to the internal voltage regulator. Bypass requirements
depend on how heavily the MCU pins are loaded.

2.4.3 VDD1, VDD2, VSS1, VSS2 — Core Power Pins

Power is supplied to the MCU through VDD and VSS. This 2.5V supply is derived from the internal
voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned
off, if VDDR is tied to ground.

2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG

VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to
digital converter. .

2.4.5 VRH, VRL — ATD Reference Voltage Input Pins

VRH and VRL are the reference voltage input pins for the analog to digital converter.

2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL

Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the
supply voltage to the Oscillator and PLL to be bypassed independently.This 2.5V voltage is generated by
the internal voltage regulator.

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Table 2-2 MC9S12C32 Power and Ground Connection Summary

Nominal
Mnemonic Description
Voltage
VDD1 Internal power and ground generated by internal regulator. These also
2.5 V
VDD2 allow an external source to supply the core VDD/VSS voltages and bypass
VSS1 the internal voltage regulator.
0V In the 48 and 52 LQFP packages VDD2 and VSS2 are not available.
VSS2
VDDR 5.0 V External power and ground, supply to internal voltage regulator.
VSSR 0V
VDDX 5.0 V
External power and ground, supply to pin drivers.
VSSX 0V
VDDA 5.0 V Operating voltage and ground for the analog-to-digital converters and the
reference for the internal voltage regulator, allows the supply voltage to the
VSSA 0V A/D to be bypassed independently.
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VRH 5.0 V Reference voltage low for the ATD converter.

VRL 0V In the 48 and 52 LQFP packages VRL is bonded to VSSA.
VDDPLL 2.5 V Provides operating voltage and ground for the Phased-Locked Loop. This
allows the supply voltage to the PLL to be bypassed independently.
VSSPLL 0V Internal power and ground generated by internal regulator.

NOTE:All VSS pins must be connected together in the application. Because fast signal transitions
place high, short-duration current demands on the power supply, use bypass capacitors with
high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements
depend on MCU pin load.

Section 3 System Clock Description

The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block User
Guide for details on clock generation.

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S12_CORE
core clock

Flash

RAM

TIM

ATD

PIM
EXTAL
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SCI

bus clock SPI

CRG

oscillator clock MSCAN

XTAL
VREG

TPM

Figure 3-1 Clock Connections

Section 4 Modes of Operation

4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12C32. Each mode has an
associated default memory map and external bus configuration controlled by a further pin.
Three low power modes exist for the device.

4.2 Chip Configuration Summary

The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset. The MODC, MODB, and MODA bits in the MODE register show the current operating mode and
provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are
latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting of the
ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map.
ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched into
the ROMON bit in the MISC register on the rising edge of the reset signal.

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Table 4-1 Mode Selection

BKGD = PE6 = PE5 = PP6 = ROMON Mode Description
MODC MODB MODA ROMCTL Bit
Special Single Chip, BDM allowed and ACTIVE. BDM is
0 0 0 X 1 allowed in all other modes but a serial command is
required to make BDM active.
0 1
0 0 1 Emulation Expanded Narrow, BDM allowed
1 0
0 1 0 X 0 Special Test (Expanded Wide), BDM allowed
0 1
0 1 1 Emulation Expanded Wide, BDM allowed
1 0
1 0 0 X 1 Normal Single Chip, BDM allowed
0 0
1 0 1 Normal Expanded Narrow, BDM allowed
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1 1
Peripheral; BDM allowed but bus operations would cause
1 1 0 X 1
bus conflicts (must not be used)
0 0
1 1 1 Normal Expanded Wide, BDM allowed
1 1

For further explanation on the modes refer to the Core User Guide.

Table 4-2 Clock Selection Based on PE7

PE7 = XCLKS Description
1 Colpitts Oscillator selected
0 Pierce Oscillator/external clock selected

4.3 Security
The device will make available a security feature preventing the unauthorized read and write of the
memory contents. This feature allows:
• Protection of the contents of FLASH,
• Operation in single-chip mode,
• Operation from external memory with internal FLASH disabled.
The user must be reminded that part of the security must lie with the user’s code. An extreme example
would be user’s code that dumps the contents of the internal program. This code would defeat the purpose
of security. At the same time the user may also wish to put a back door in the user’s program. An example
of this is the user downloads a key through the SCI which allows access to a programming routine that
updates parameters.

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4.3.1 Securing the Microcontroller

Once the user has programmed the FLASH, the part can be secured by programming the security bits
located in the FLASH module. These non-volatile bits will keep the part secured through resetting the part
and through powering down the part.
The security byte resides in a portion of the Flash array.
Check the Flash Block User Guide for more details on the security configuration.

4.3.2 Operation of the Secured Microcontroller

4.3.2.1 Normal Single Chip Mode

This will be the most common usage of the secured part. Everything will appear the same as if the part was
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not secured with the exception of BDM operation. The BDM operation will be blocked.

4.3.2.2 Executing from External Memory

The user may wish to execute from external space with a secured microcontroller. This is accomplished
by resetting directly into expanded mode. The internal FLASH will be disabled. BDM operations will be
blocked.

4.3.3 Unsecuring the Microcontroller

In order to unsecure the microcontroller, the internal FLASH must be erased. This can be done through an
external program in expanded mode or via a sequence of BDM commands. Unsecuring is also possible via
the Backdoor Key Access. Refer to Flash Block Guide for details.
Once the user has erased the FLASH, the part can be reset into special single chip mode. This invokes a
program that verifies the erasure of the internal FLASH. Once this program completes, the user can erase
and program the FLASH security bits to the unsecured state. This is generally done through the BDM, but
the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to
an external program (again through BDM commands). Note that if the part goes through a reset before the
security bits are reprogrammed to the unsecure state, the part will be secured again.

4.4 Low Power Modes

The microcontroller features three main low power modes. Consult the respective Block User Guide for
information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of
information about the clock system is the Clock and Reset Generator User Guide (CRG).

4.4.1 Stop

Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static
mode. Wake up from this mode can be done via reset or external interrupts.

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4.4.2 Pseudo Stop

This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running
and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are
turned off. This mode consumes more current than the full STOP mode, but the wake up time from this
mode is significantly shorter.

4.4.3 Wait

This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute
instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active.
For further power consumption the peripherals can individually turn off their local clocks.

4.4.4 Run
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Although this is not a low power mode, unused peripheral modules should not be enabled in order to save
power.

Section 5 Resets and Interrupts

5.1 Overview
Consult the Exception Processing section of the HCS12 Core User Guide for information on resets and
interrupts.

5.2 Vectors
5.2.1 Vector Table

Table 5-1 lists interrupt sources and vectors in default order of priority.
Table 5-1 Interrupt Vector Locations
CCR HPRIO Value
Vector Address Interrupt Source Local Enable
Mask to Elevate
External Reset, Power On Reset or Low
$FFFE, $FFFF Voltage Reset (see CRG Flags Register None None –
to determine reset source)
$FFFC, $FFFD Clock Monitor fail reset None COPCTL (CME, FCME) –
$FFFA, $FFFB COP failure reset None COP rate select –
$FFF8, $FFF9 Unimplemented instruction trap None None –
$FFF6, $FFF7 SWI None None –
$FFF4, $FFF5 XIRQ X-Bit None –
$FFF2, $FFF3 IRQ I-Bit INTCR (IRQEN) $F2
$FFF0, $FFF1 Real Time Interrupt I-Bit CRGINT (RTIE) $F0

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$FFEE, $FFEF Standard Timer channel 0 I-Bit TIE (C0I) $EE

$FFEC, $FFED Standard Timer channel 1 I-Bit TIE (C1I) $EC
$FFEA, $FFEB Standard Timer channel 2 I-Bit TIE (C2I) $EA
$FFE8, $FFE9 Standard Timer channel 3 I-Bit TIE (C3I) $E8
$FFE6, $FFE7 Standard Timer channel 4 I-Bit TIE (C4I) $E6
$FFE4, $FFE5 Standard Timer channel 5 I-Bit TIE (C5I) $E4
$FFE2, $FFE3 Standard Timer channel 6 I-Bit TIE (C6I) $E2
$FFE0, $FFE1 Standard Timer channel 7 I-Bit TIE (C7I) $E0
$FFDE, $FFDF Standard Timer overflow I-Bit TMSK2 (TOI) $DE
$FFDC, $FFDD Pulse accumulator A overflow I-Bit PACTL (PAOVI) $DC
$FFDA, $FFDB Pulse accumulator input edge I-Bit PACTL (PAI) $DA
$FFD8, $FFD9 SPI I-Bit SPICR1 (SPIE, SPTIE) $D8
SCICR2
$FFD6, $FFD7 SCI I-Bit $D6
(TIE, TCIE, RIE, ILIE)
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$FFD4, $FFD5 Reserved

$FFD2, $FFD3 ATD I-Bit ATDCTL2 (ASCIE) $D2
$FFD0, $FFD1 Reserved
$FFCE, $FFCF Port J I-Bit PIEP (PIEP7-6) $CE
$FFCC, $FFCD Reserved
$FFCA, $FFCB Reserved
$FFC8, $FFC9 Reserved
$FFC6, $FFC7 CRG PLL lock I-Bit PLLCR (LOCKIE) $C6
$FFC4, $FFC5 CRG Self Clock Mode I-Bit PLLCR (SCMIE) $C4
$FFBA to $FFC3 Reserved
$FFB8, $FFB9 FLASH I-Bit FCNFG (CCIE, CBEIE) $B8
$FFB6, $FFB7 CAN wake-up I-Bit CANRIER (WUPIE) $B6
$FFB4, $FFB5 CAN errors I-Bit CANRIER (CSCIE, OVRIE) $B4
$FFB2, $FFB3 CAN receive I-Bit CANRIER (RXFIE) $B2
$FFB0, $FFB1 CAN transmit I-Bit CANTIER (TXEIE[2:0]) $B0
$FF90 to $FFAF Reserved
$FF8E, $FF8F Port P I-Bit PIEP (PIEP7-0) $8E
$FF8C, $FF8D PWM Emergency Shutdown I-Bit PWMSDN(PWMIE) $8C
$FF8A, $FF8B VREG LVI I-Bit CTRL0 (LVIE) $8A
$FF80 to $FF89 Reserved

5.3 Resets
Resets are a subset of the interrupts featured inTable 5-1. The different sources capable of generating a
system reset are summarized in Table 5-2. When a reset occurs, MCU registers and control bits are
changed to known start-up states. Refer to the respective module Block User Guides for register reset
states

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5.3.1 Reset Summary Table

Table 5-2 Reset Summary

Reset Priority Source Vector
Power-on Reset 1 CRG Module $FFFE, $FFFF
External Reset 1 RESET pin $FFFE, $FFFF
Low Voltage Reset 1 VREG Module $FFFE, $FFFF
Clock Monitor Reset 2 CRG Module $FFFC, $FFFD
COP Watchdog Reset 3 CRG Module $FFFA, $FFFB

5.3.2 Effects of Reset

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When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block User Guides for register reset states. Refer to the HCS12 Core User Guides for
mode dependent pin configuration of port A, B and E out of reset.
Refer to the PIM Block User Guide for reset configurations of all peripheral module ports.
Refer to for locations of the memories depending on the operating mode after reset.
The RAM array is not automatically initialized out of reset.
Refer to Table 1-1 for locations of the memories depending on the operating mode after reset.

NOTE: For devices assembled in 48-pin or 52-pin LQFP packages all non-bonded out pins
should be configured as outputs after reset in order to avoid current drawn from
floating inputs. Refer to Table 2-1 for affected pins.

Section 6 HCS12 Core Block Description

Consult the HCS12 Core User Guide for information about the HCS12 core modules, i.e. central
processing unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed
external bus interface (MEBI), debug12 module (DBG12) and background debug mode module (BDM).

6.1 Device-specific information

6.1.1 PPAGE

External paging is not supported on this device. In order to access the 16K Flash Block1 in the address
range $8000-$BFFF the PPAGE register must be loaded with a valid value for this range. Valid PPAGE
values for Flash Block1 visibility in the $8000-$BFFF range are PPAGE=$00, $02...$38, $3A, $3C, $3E.
Flash Block1 is also visible in the $4000-$7FFF range if ROMHM is cleared.
Flash Block2 is visible in the $8000-$BFFF range with PPAGE=$01,$03,$05,$07....$39,$3B,$3D,$3F.

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Flash Block2 is always visible in the range $C000-$FFFF if ROMON is set.

6.1.2 BDM alternate clock

The BDM section of S12 Core User Guide reference to alternate clock is equivalent to oscillator clock.

Section 7 Voltage Regulator (VREG) Block Description

Consult the VREG Block User Guide for information about the dual output linear voltage regulator.

7.1 Device-specific information

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The VREG is part of the IPBus domain.

7.1.1 VREGEN

VREGEN is connected internally to VDDR.

7.1.2 VDD1, VDD2, VSS1, VSS2

In the 80 pin QFP package version, both internal VDD and VSS of the 2.5V domain are bonded out on 2
sides of the device as two pin pairs (VDD1, VSS1 & VDD2, VSS2). VDD1 and VDD2 are connected
together internally. VSS1 and VSS2 are connected together internally.
The extra pin pair enables systems using the 80 pin package to employ better supply routing and further
decoupling.

Section 8 Recommended Printed Circuit Board Layout

The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:

• Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins (C1 - C6).
• Central point of the ground star should be the VSSR pin.
• Use low ohmic low inductance connections between VSS1, VSS2 and VSSR.
• VSSPLL must be directly connected to VSSR.
• Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7,
C8, C11 and Q1 as small as possible.

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• Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the
connection area to the MCU.
• Central power input should be fed in at the VDDA/VSSA pins.
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Table 8-1 Recommended External Component Values

Component Purpose Type Value

C1 VDD1 filter cap ceramic X7R 220nF, 1470nF

C2 VDD2 filter cap (80 QFP only) ceramic X7R 220nF

C3 VDDA filter cap ceramic X7R 100nF

C4 VDDR filter cap X7R/tantalum >=100nF

C5 VDDPLL filter cap ceramic X7R 100nF

C6 VDDX filter cap X7R/tantalum >=100nF

C7 OSC load cap

See PLL specification chapter
C8 OSC load cap
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C9 PLL loop filter cap

See PLL specification chapter
C10 PLL loop filter cap

Colpitts mode only, if recommended by

C11 DC cutoff cap
quartz manufacturer

R1 PLL loop filter res See PLL Specification chapter

Q1 Quartz

NOTES:
1. In 48LQFP and 52LQFP package versions, VDD2 is not available. Thus 470nF must be connect-
ed to VDD1.

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Figure 8-1 Recommended PCB Layout (48 LQFP)

VDDX

C6
VSSA C3
VSSX

VDDA
VDD1

C1
VSS1
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VSSR
C4

C5

VDDR
C8

C7
C11

Note : Q1
C9

C10

Oscillator in VSSPLL
VDDPLL
Colpitts mode. R1

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Figure 8-2 Recommended PCB Layout (52 LQFP)

NOTE : Oscillator in Colpitts mode.

VDDX

C6
VSSX VSSA C3
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VDDA

VDD1

C1
VSS1

VSSR
C4

C5

VDDR
C8

C7
C11

Q1
C9

C10

VSSPLL
VDDPLL
R1

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Figure 8-3 Recommended PCB Layout (80 QFP)

NOTE : Oscillator in Colpitts mode.

VSSA

C3
VDDX

C6

VSSX
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VDDA

VSS2
VDD1
C2
C1
VDD2
VSS1

VSSR
C4

C5

VDDR
C8

C7
C11

Q1
C9

C10

VSSPLL
VDDPLL
R1

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Section 9 Clock Reset Generator (CRG) Block Description

Consult the CRG Block User Guide for information about the Clock and Reset Generator module.

9.1 Device-specific information

The CRG is part of the IPBus domain.
The Low Voltage Reset feature uses the low voltage reset signal from the VREG module as an input to the
CRG module. When the regulator output voltage supply to the internal chip logic falls below a specified
threshold the LVR signal from the VREG module causes the CRG module to generate a reset. Consult the
VREG Block User Guide for voltage level specifications.
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9.1.1 XCLKS

The XCLKS input signal is active low (see 2.3.8 PE7 / NOACC / XCLKS — Port E I/O Pin 7).

Section 10 Oscillator (OSC) Block Description

Consult the OSC Block User Guide for information about the Oscillator module.

Section 11 Timer (TIM) Block Description

Consult the TIM_16B8C Block User Guide for information about the Timer module.
The TIM is part of the IPBus domain.

Section 12 Analog to Digital Converter (ATD) Block

Description

12.1 Device-specific information

The ATD is part of the IPBus domain.

12.1.1 VRL (voltage reference low)

In the 48 and 52 pin package versions, the VRL pad is bonded internally to the VSSA pin.
Consult the ATD_10B8C Block User Guide for further information about the A/D Converter module.

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Section 13 Serial Communications Interface (SCI) Block

Description

Consult the SCI Block User Guide for information about the Serial Communications Interface module.
The SCI is part of the IPBus domain.

Section 14 Serial Peripheral Interface (SPI) Block

Description

Consult the SPI Block User Guide for information about the Serial Peripheral Interface module.
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The SPI is part of the IPBus domain.

Section 15 Flash EEPROM 32K Block Description

Consult the FTS32K Block User Guide for information about the Flash module.
The Flash is part of the HCS12 Bus domain.

Section 16 RAM Block Description

This module supports single-cycle misaligned word accesses without wait states.
Consult the SRAM2K Block User Guide for information about the RAM Module
The RAM is part of the HCS12 Bus domain.

Section 17 Pulse Width Modulator (PWM) Block

Description

Only channels [5:0] of the PWM are implemented on the MC9S12C32.

Consult the PWM_8B6C Block User Guide for information about the Pulse Width Modulator Module.
The PWM is part of the IPBus domain.

Section 18 MSCAN Block Description

Consult the MSCAN Block User Guide for information about the Motorola Scalable CAN Module.

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The MSCAN is part of the IPBus domain.

Section 19 Port Integration Module (PIM) Block Description

Consult the PIM_9C32 Block User Guide for information about the Port Integration Module.
The PIM is part of the IPBus domain.
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Appendix A Electrical Characteristics

A.1 General
NOTE: The electrical characteristics given in this section are preliminary and should be
used as a guide only. Values cannot be guaranteed by Motorola and are subject to
change without notice.

NOTE: The part is specified and tested over the 5V and 3.3V ranges. For the intermediate
range, generally the electrical specifications for the 3.3V range apply, but the part
is not tested in production test in the intermediate range.

This supplement contains the most accurate electrical information for the MC9S12C32 microcontroller
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available at the time of publication. The information should be considered PRELIMINARY and is subject
to change.
This introduction is intended to give an overview on several common topics like power supply, current
injection etc.

A.1.1 Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate.

NOTE: This classification will be added at a later release of the specification

P: Those parameters are guaranteed during production testing on each individual device.
C: Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations. They are regularly verified by production monitors.
T: Those parameters are achieved by design characterization on a small sample size from typical devices.
All values shown in the typical column are within this category.
D: Those parameters are derived mainly from simulations.

A.1.2 Power Supply

The MC9S12C32 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator and PLL
as well as the digital core.
The VDDA, VSSA pair supplies the A/D converter.
The VDDX, VSSX pair supplies the I/O pins
The VDDR, VSSR pair supplies the internal voltage regulator.
VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic.
VDDPLL, VSSPLL supply the oscillator and the PLL.

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VSS1 and VSS2 are internally connected by metal.

VDD1 and VDD2 are internally connected by metal.
VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD
protection.

NOTE: In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5
is used for either VSSA, VSSR and VSSX unless otherwise noted.
IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR
pins.
VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and
VSSPLL.
IDD is used for the sum of the currents flowing into VDD1 and VDD2.

A.1.3 Pins
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There are four groups of functional pins.

A.1.3.1 5V I/O pins

Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog
inputs, BKGD pin and the RESET inputs.The internal structure of all those pins is identical, however some
of the functionality may be disabled. E.g. pull-up and pull-down resistors may be disabled permanently.

A.1.3.2 Analog Reference

This class is made up by the two VRH and VRL pins. In 48 and 52 pin package versions the VRL pad is
bonded to the VSSA pin.

A.1.3.3 Oscillator

The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied
by VDDPLL.

A.1.3.4 TEST

This pin is used for production testing only.

A.1.4 Current Injection

Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and
operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the
injection current may flow out of VDD5 and could result in external power supply going out of regulation.
Insure external VDD5 load will shunt current greater than maximum injection current. This will be the
greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is
very low which would reduce overall power consumption.

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A.1.5 Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).

Table A-1 Absolute Maximum Ratings

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Num Rating Symbol Min Max Unit

1 I/O, Regulator and Analog Supply Voltage VDD5 -0.3 6.5 V

2 Digital Logic Supply Voltage1 VDD -0.3 3.0 V

3 PLL Supply Voltage 1 VDDPLL -0.3 3.0 V

4 Voltage difference VDDX to VDDR and VDDA ∆VDDX -0.3 0.3 V

5 Voltage difference VSSX to VSSR and VSSA ∆VSSX -0.3 0.3 V

6 Digital I/O Input Voltage VIN -0.3 6.5 V

7 Analog Reference VRH, VRL -0.3 6.5 V

8 XFC, EXTAL, XTAL inputs VILV -0.3 3.0 V

9 TEST input VTEST -0.3 10.0 V

Instantaneous Maximum Current
10 I -25 +25 mA
D
Single pin limit for all digital I/O pins 2
Instantaneous Maximum Current
11 IDL -25 +25 mA
Single pin limit for XFC, EXTAL, XTAL3
Instantaneous Maximum Current
12 IDT -0.25 0 mA
Single pin limit for TEST4

13 Operating Temperature Range (packaged) T

A – 40 125 °C

14 Operating Temperature Range (junction) TJ – 40 140 °C

15 Storage Temperature Range Tstg – 65 155 °C

NOTES:
1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.
The absolute maximum ratings apply when the device is powered from an external source.
2. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA.
3. These pins are internally clamped to VSSPLL and VDDPLL
4. This pin is clamped low to VSSPLL, but not clamped high. This pin must be tied low in applications.

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A.1.6 ESD Protection and Latch-up Immunity

All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-2 ESD and Latch-up Test Conditions
Model Description Symbol Value Unit
Series Resistance R1 1500 Ohm
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Storage Capacitance C 100 pF

Human Body
Number of Pulse per pin -
positive - 3
negative 3
Series Resistance R1 0 Ohm
Storage Capacitance C 200 pF
Machine
Number of Pulse per pin -
positive - 3
negative 3
Minimum input voltage limit -2.5 V
Latch-up
Maximum input voltage limit 7.5 V

Table A-3 ESD and Latch-Up Protection Characteristics

Num C Rating Symbol Min Max Unit
1 C Human Body Model (HBM) VHBM 2000 - V

2 C Machine Model (MM) VMM 200 - V

3 C Charge Device Model (CDM) VCDM 500 - V

Latch-up Current at 125°C
4 C positive ILAT +100 - mA
negative -100
Latch-up Current at 27°C
5 C positive ILAT +200 - mA
negative -200

A.1.7 Operating Conditions

This chapter describes the operating conditions of the device. Unless otherwise noted those conditions
apply to all the following data.

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NOTE: Instead of specifying ambient temperature all parameters are specified for the more
meaningful silicon junction temperature. For power dissipation calculations refer
to Section A.1.8 Power Dissipation and Thermal Characteristics.
Table A-4 Operating Conditions
Rating Symbol Min Typ Max Unit
I/O, Regulator and Analog Supply Voltage VDD5 2.97 5 5.5 V

Digital Logic Supply Voltage1 VDD 2.25 2.5 2.75 V

PLL Supply Voltage 1 VDDPLL 2.25 2.5 2.75 V

Voltage Difference VDDX to VDDA ∆VDDX -0.1 0 0.1 V

Voltage Difference VSSX to VSSR and VSSA ∆VSSX -0.1 0 0.1 V

Oscillator fosc 0.5 - 16 MHz

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Bus Frequency fbus 0.5 - 25 MHz

Operating Junction Temperature Range TJ -40 - 140 °C

NOTES:
1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. .

A.1.8 Power Dissipation and Thermal Characteristics

Power dissipation and thermal characteristics are closely related. The user must assure that the maximum
operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in °C can be
obtained from:
T J = T A + ( P D • Θ JA )

T J = Junction Temperature, [°C ]

T A = Ambient Temperature, [°C ]

P D = Total Chip Power Dissipation, [W]

Θ JA = Package Thermal Resistance, [°C/W]

The total power dissipation can be calculated from:

P D = P INT + P IO

P INT = Chip Internal Power Dissipation, [W]

Two cases with internal voltage regulator enabled and disabled must be considered:
1. Internal Voltage Regulator disabled

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P INT = I DD ⋅ V DD + I DDPLL ⋅ V DDPLL + I DDA ⋅ V DDA

∑
2
P IO = R DSON ⋅ I IO
i i

Which is the sum of all output currents on I/O ports associated with VDDX and VDDM.
For RDSON is valid:
V OL
R DSON = ------------ ;for outputs driven low
I OL
respectively
V DD5 – V OH
R DSON = ------------------------------------ ;for outputs driven high
I OH
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2. Internal voltage regulator enabled

P INT = I DDR ⋅ V DDR + I DDA ⋅ V DDA

IDDR is the current shown in Table A-8 and not the overall current flowing into VDDR, which
additionally contains the current flowing into the external loads with output high.

∑
2
P IO = R DSON ⋅ I IO
i i

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Which is the sum of all output currents on I/O ports associated with VDDX and VDDR.
Table A-5 Thermal Package Characteristics1
Num C Rating Symbol Min Typ Max Unit
1 T Thermal Resistance LQFP48, single layer PCB2 θJA - - 69 oC/W

Thermal Resistance LQFP48, double sided PCB with

2 T θJA - - 53 o
C/W
2 internal planes3

3 T Junction to Board LQFP48 θJB 30 oC/W

4 T Junction to Case LQFP48 θJC 20 o

C/W

5 T Junction to Package Top LQFP48 ΨJT 4 oC/W

6 T Thermal Resistance LQFP52, single sided PCB θJA - - 65 oC/W

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Thermal Resistance LQFP52, double sided PCB with

7 T θJA - - 49 o
C/W
2 internal planes

8 T Junction to Board LQFP52 θJB 31 o

C/W

9 T Junction to Case LQFP52 θJC 17 oC/W

10 T Junction to Package Top LQFP52 ΨJT 3 oC/W

11 T Thermal Resistance QFP 80, single sided PCB θJA - - 52 o

C/W
Thermal Resistance QFP 80, double sided PCB with
12 T θJA - - 42 oC/W
2 internal planes

13 T Junction to Board QFP80 θJB 28 oC/W

14 T Junction to Case QFP80 θJC 18 o

C/W

15 T Junction to Package Top QFP80 ΨJT 4 o

C/W
NOTES:
1. The values for thermal resistance are achieved by package simulations
2. PC Board according to EIA/JEDEC Standard 51-2
3. PC Board according to EIA/JEDEC Standard 51-7

A.1.9 I/O Characteristics

This section describes the characteristics of all I/O pins. All parameters are not always applicable, e.g. not
all pins feature pull up/down resistances.

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Table A-6 5V I/O Characteristics

Conditions are 4.5< VDDX <5.5V Termperature from -40˚C to +140˚C, unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 P Input High Voltage V 0.65*VDD5 - - V
IH

T Input High Voltage VIH - - VDD5 + 0.3 V

2 P Input Low Voltage VIL - - 0.35*VDD5 V

T Input Low Voltage VIL VSS5 - 0.3 - - V

3 C Input Hysteresis VHYS 250 mV

Input Leakage Current (pins in high ohmic input

4 P mode)1 I
in –2.5 - 2.5 µA
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Vin = VDD5 or VSS5

Output High Voltage (pins in output mode)

5 C V VDD5 – 0.8 - - V
Partial Drive IOH = –2mA OH

Output High Voltage (pins in output mode)

6 P VOH VDD5 – 0.8 - - V
Full Drive IOH = –10mA
Output Low Voltage (pins in output mode)
7 C VOL - - 0.8 V
Partial Drive IOL = +2mA
Output Low Voltage (pins in output mode)
8 P V - - 0.8 V
Full Drive IOL = +10mA OL

Internal Pull Up Device Current,

9 P tested at V Max. IPUL - - -130 µA
IL

Internal Pull Up Device Current,

10 C tested at V Min. IPUH -10 - - µA
IH

Internal Pull Down Device Current,

11 P tested at V Min. IPDH - - 130 µA
IH

Internal Pull Down Device Current,

12 C tested at V Max. IPDL 10 - - µA
IL

13 D Input Capacitance Cin 7 - pF

Injection current2
14 T Single Pin limit IICS -2.5 - 2.5 mA
Total Device Limit. Sum of all injected currents IICP -25 25

15 P Port P, J Interrupt Input Pulse filtered3 tPIGN 3 µs

16 P Port P, J Interrupt Input Pulse passed(3) tPVAL 10 µs

NOTES:
1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for
each 8 C to 12 C in the temperature range from 50 C to 125 C.
2. Refer to Section A.1.4 Current Injection, for more details
3. Parameter only applies in STOP or Pseudo STOP mode.

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Table A-7 3.3V I/O Characteristics

Conditions are VDDX=3.3V +/-10%, Termperature from -40˚C to +140˚C, unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 P Input High Voltage V 0.65*VDD5 - - V
IH

T Input High Voltage VIH - - VDD5 + 0.3 V

2 P Input Low Voltage VIL - - 0.35*VDD5 V

T Input Low Voltage VIL VSS5 - 0.3 - - V

3 C Input Hysteresis VHYS 250 mV

Input Leakage Current (pins in high ohmic input

4 P mode)1 I
in –2.5 - 2.5 µA
Vin = VDD5 or VSS5
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Output High Voltage (pins in output mode)

5 C V VDD5 – 0.4 - - V
Partial Drive IOH = –0.75mA OH

Output High Voltage (pins in output mode)

6 P V VDD5 – 0.4 - - V
Full Drive IOH = –4.5mA OH

Output Low Voltage (pins in output mode)

7 C V - - 0.4 V
Partial Drive IOL = +0.9mA OL

Output Low Voltage (pins in output mode)

8 P V - - 0.4 V
Full Drive IOL = +5.5mA OL

Internal Pull Up Device Current,

9 P tested at V Max. IPUL - - –60 µA
IL

Internal Pull Up Device Current,

10 C tested at VIH Min. IPUH -6 - - µA

Internal Pull Down Device Current,

11 P tested at V Min. IPDH - - 60 µA
IH

Internal Pull Down Device Current,

12 C tested at V Max. IPDL 6 - - µA
IL

11 D Input Capacitance Cin 7 - pF

Injection current2
12 T Single Pin limit IICS -2.5 - 2.5 mA
Total Device Limit. Sum of all injected currents IICP -25 25

13 P Port P, J Interrupt Input Pulse filtered3 tPIGN 3 µs

14 P Port P, J Interrupt Input Pulse passed(3) tPVAL 10 µs

NOTES:
1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for
each 8 C to 12 C in the temperature range from 50 C to 125 C.
2. Refer to Section A.1.4 Current Injection, for more details
3. Parameter only applies in STOP or Pseudo STOP mode.

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A.1.10 Supply Currents

This section describes the current consumption characteristics of the device as well as the conditions for
the measurements.

A.1.10.1 Measurement Conditions

All measurements are without output loads. Unless otherwise noted the currents are measured in single
chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator.

A.1.10.2 Additional Remarks

In expanded modes the currents flowing in the system are highly dependent on the load at the address, data
and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be
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given. A very good estimate is to take the single chip currents and add the currents due to the external
loads.

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Table A-8 Supply Current Characteristics

Conditions are shown in Table A-4 with internal regulator enabled unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 P Run Supply Current Single Chip IDD5 40 mA
Wait Supply current
P All modules enabled 30
2 IDDW mA
P VDDR<4.9V, only RTI enabled2 3.5 8
C VDDR>4.9V, only RTI enabled 2.5

Pseudo Stop Current (RTI and COP disabled)23

C -40°C 340
P 27°C 360 450
C 85°C 500
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3 P "C" Temp Option 100˚C IDDPS1 550 1450 µA

C 105°C 590
P "V" Temp Option 120˚C 720 1900
C 125°C 780
P "M" Temp Option 140°C 1100 4500

Pseudo Stop Current (RTI and COP enabled)2 3

C -40°C 540
C 27°C 700
4 IDDPS(1) µA
C 85°C 750
C 105°C 880
C 125°C 1300

Stop Current 3
C -40°C 10
P 27°C 20 80
C 85°C 100
5 P "C" Temp Option 100˚C IDDS1 140 1000 µA
C 105°C 170
P "V" Temp Option 120˚C 300 1400
C 125°C 350
P "M" Temp Option 140°C 520 4000

NOTES:
1. STOP current measured in production test at increased junction temperature, hence for Temp Option "C" the test is
carried out at 100˚C although the Temperature specification is 85˚C. Similarly for "v" and "M" options the temperature
used in test lies 15˚C above the temperature option specification.
2. PLL off
3. At those low power dissipation levels TJ = TA can be assumed

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Appendix B Electrical Specifications

B.1 Voltage Regulator Operating Conditions

Table B-1 -Voltage Regulator Electrical Parameters

Nu C Characteristic Symbol Min Typical Max Unit
m

1 P Input Voltages VVDDR,A 2.97 — 5.5 V

Regulator Current
2 P Reduced Power Mode IREG — 20 50 µA
Shutdown Mode — 12 40 µA
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Output Voltage Core

Full Performance Mode 2.35 2.5 2.75 V
3 P VDD
Reduced Power Mode 1.6 2.5 2.75 V
Shutdown Mode — —1 — V

Output Voltage PLL

Full Performance Mode 2.35 2.5 2.75
V
4 P Reduced Power Mode2 VDDPLL 2.0 2.5 2.75
2.5 V
Reduced Power Mode3 1.6 2.75
V
Shutdown Mode — —4 —

Low Voltage Interrupt5

5 P Assert Level VLVIA 4.30 4.53 4.77 V
Deassert Level VLVID 4.42 4.65 4.89 V

6 P Low Voltage Reset6

Assert Level VLVRA 2.25 — — V

Power-on Reset7
7 C Assert Level VPORA 0.97 — — V
Deassert Level VPORD — — 2.05 V

NOTES:
1. High Impedance Output
2. Current IDDPLL = 1mA (Colpitts Oscillator)
3. Current IDDPLL = 3mA (Pierce Oscillator)
4. High Impedance Output
5. Monitors VDDA, active only in Full Performance Mode. Indicates I/O & ADC performance degradation due to low supply
voltage.
6. Monitors VDD, active only in Full Performance Mode. MCU is monitored by the POR in RPM (see Figure B-1)
7. Monitors VDD. Active in all modes.

NOTE: The electrical characteristics given in this section are preliminary and should be
used as a guide only. Values in this section cannot be guaranteed by Motorola and
are subject to change without notice.

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B.2 Chip Power-up and LVI/LVR graphical explanation

B.2.0.1 POR

The release level VPORR and the assert level VPORA are derived from the VDD Supply. They are also valid
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by nuposc.

B.2.0.2 LVR

The release level VLVRR and the assert level VLVRA are derived from the VDD Supply. They are also valid
if the device is powered externally. After releasing the LVR reset the oscillator and the clock quality check
are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self
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clock. The fastest startup time possible is given by nuposc.

Voltage regulator sub modules LVI (low voltage interrupt), POR (power-on reset) and LVR (low voltage
reset) handle chip power-up or drops of the supply voltage. Their function is described in Figure B-1.

Figure B-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled)

V VDDA

VLVID

VLVIA
VDD

VLVRD
VLVRA

VPORD

t
LVI

LVI enabled LVI disabled due to LVR

POR

LVR

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B.3 Output Loads

B.3.1 Resistive Loads

The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits allows no
external DC loads.

B.3.2 Capacitive Loads

The capacitive loads are specified in Table B-2. Ceramic capacitors with X7R dielectricum are required.
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Table B-2 Voltage Regulator - Capacitive Loads

Num Characteristic Symbol Min Typical Max Unit
1 VDD external capacitive load CDDext 440 440 12000 nF

2 VDDPLL external capacitive load CDDPLLext 90 220 5000 nF

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B.4 ATD Characteristics

This section describes the characteristics of the analog to digital converter.
VRL is not available as a separate pin in the 48 and 52 pin versions. In this case the internal VRL pad is
bonded to the VSSA pin.
The ATD is specified and tested for both the 3.3V and 5V range. For ranges between 3.3V and 5V the
ATD accuracy is generally the same as in the 3.3V range but is not tested in this range in production test.

B.4.1 ATD Operating Characteristics In 5V Range

The Table B-3 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
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VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not
drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will
effectively be clipped.
Table B-3 ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted. Supply Voltage 5V-10% <= VDDA <=5V+10%

Num C Rating Symbol Min Typ Max Unit

Reference Potential
1 D Low VRL VSSA VDDA/2 V
High VRH VDDA/2 VDDA V
2 C Differential Reference Voltage1 VRH-VRL 4.75 5.0 5.25 V
3 D ATD Clock Frequency fATDCLK 0.5 2.0 MHz
ATD 10-Bit Conversion Period
4 D Clock Cycles2 NCONV10 14 28 Cycles
Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV10 7 14 µs
ATD 8-Bit Conversion Period
5 D Clock Cycles2 NCONV10 12 26 Cycles
Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV10 6 13 µs
5 D Recovery Time (VDDA=5.0 Volts) tREC 20 µs
6 P Reference Supply current IREF 0.375 mA
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.75V
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.

B.4.2 ATD Operating Characteristics In 3.3V Range

The Table B-3 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive

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beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped

Table B-4 ATD Operating Characteristics

Conditions are shown in Table A-4 unless otherwise noted; Supply Voltage 3.3V-10% <= VDDA <= 3.3V+10%

Num C Rating Symbol Min Typ Max Unit

Reference Potential
1 D Low VRL VSSA VDDA/2 V
High VRH VDDA/2 VDDA V
2 C Differential Reference Voltage VRH-VRL 3.0 3.3 3.6 V
3 D ATD Clock Frequency fATDCLK 0.5 2.0 MHz
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ATD 10-Bit Conversion Period

4 D Clock Cycles1 NCONV10 14 28 Cycles
Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV10 7 14 µs
ATD 8-Bit Conversion Period
5 D Clock Cycles1 NCONV8 12 26 Cycles
Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV8 6 13 µs
6 D Recovery Time (VDDA=3.3 Volts) tREC 20 µs
7 P Reference Supply current IREF 0.250 mA
NOTES:
1. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.

B.4.3 Factors influencing accuracy

Three factors - source resistance, source capacitance and current injection - have an influenceon the
accuracy of the ATD.

B.4.3.1 Source Resistance:

Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance
there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS
specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or
operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source
resistance is allowable.

B.4.3.2 Source capacitance

When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage ≤ 1LSB, then the external filter capacitor, Cf ≥ 1024 * (CINS- CINN).

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B.4.3.3 Current injection

There are two cases to consider.

1. A current is injected into the channel being converted. The channel being stressed has conversion
values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less
than VRL unless the current is higher than specified as disruptive conditions.
2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this
current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy
of the conversion depending on the source resistance.
The additional input voltage error on the converted channel can be calculated as VERR = K * RS *
IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted
channel.
Table B-5 ATD Electrical Characteristics
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Conditions are shown in Table A-4 unless otherwise noted

Num C Rating Symbol Min Typ Max Unit
1 C Max input Source Resistance RS - - 1 KΩ

Total Input Capacitance

2 T Non Sampling CINN 10 pF
Sampling CINS 15

3 C Disruptive Analog Input Current INA -2.5 2.5 mA

4 C Coupling Ratio positive current injection Kp 10-4 A/A

5 C Coupling Ratio negative current injection Kn 10-2 A/A

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B.4.4 ATD accuracy (5V Range)

Table B-6 specifies the ATD conversion performance excluding any errors due to current injection, input
capacitance and source resistance.
Table B-6 ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted
VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV
fATDCLK = 2.0MHz
Num C Rating Symbol Min Typ Max Unit
1 P 10-Bit Resolution LSB 5 mV
2 P 10-Bit Differential Nonlinearity DNL –1 1 Counts
3 P 10-Bit Integral Nonlinearity INL –2 2 Counts
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4 P 10-Bit Absolute Error1 AE -2.5 2.5 Counts

5 P 8-Bit Resolution LSB 20 mV

6 P 8-Bit Differential Nonlinearity DNL –0.5 0.5 Counts
7 P 8-Bit Integral Nonlinearity INL –1.0 ±0.5 1.0 Counts

8 P 8-Bit Absolute Error1 AE -1.5 ±1 1.5 Counts

NOTES:
1. These values include quantization error which is inherently 1/2 count for any A/D converter.

B.4.5 ATD accuracy (3.3V Range)

Table B-6 specifies the ATD conversion performance excluding any errors due to current injection, input
capacitance and source resistance.
Table B-7 ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted
VREF = VRH - VRL = 3.328V. Resulting to one 8 bit count = 13mV and one 10 bit count = 3.25mV
fATDCLK = 2.0MHz
Num C Rating Symbol Min Typ Max Unit
1 P 10-Bit Resolution LSB 3.25 mV
2 P 10-Bit Differential Nonlinearity DNL –1.5 1.5 Counts
3 P 10-Bit Integral Nonlinearity INL –3.5 ±1.5 3.5 Counts

4 P 10-Bit Absolute Error1 AE -5 ±2.5 5 Counts

5 P 8-Bit Resolution LSB 13 mV

6 P 8-Bit Differential Nonlinearity DNL –0.5 0.5 Counts
7 P 8-Bit Integral Nonlinearity INL –1.5 ±1 1.5 Counts

8 P 8-Bit Absolute Error1 AE -2.0 ±1.5 2.0 Counts

NOTES:
1. These values include the quantization error which is inherently 1/2 count for any A/D converter.

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For the following definitions see also Figure B-2.

Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
Vi – Vi – 1
DNL ( i ) = ------------------------ – 1
1LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs:
n
Vn – V0
INL ( n ) = ∑ DNL ( i ) = -------------------- – n
1LSB
i=1
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DNL

LSB 10-Bit Absolute Error Boundary

Vi-1 Vi

$3FF
8-Bit Absolute Error Boundary
$3FE

$3FD

$3FC $FF
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$3FB

$3FA

$3F9

$3F8 $FE

$3F7

$3F6

$3F5
10-Bit Resolution

8-Bit Resolution
$3F4 $FD

$3F3

9
Ideal Transfer Curve
8 2

6
10-Bit Transfer Curve
5

4 1

2
8-Bit Transfer Curve
1

0
3.25 6.5 9.75 13 16.25 19.5 22.75 26 29.25 3286 3289 3292 3295 3299 3302 3305 3309 3312 3315 3318 3321 3324 3328
Vin
mV

Figure B-2 ATD Accuracy Definitions

NOTE: Figure B-2 shows only definitions, for specification values refer to Table B-6.

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B.5 NVM, Flash and EEPROM

B.5.1 NVM timing

The time base for all NVM program or erase operations is derived from the oscillator. A minimum
oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules
do not have any means to monitor the frequency and will not prevent program or erase operation at
frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at
a lower frequency a full program or erase transition is not assured.
The Flash program and erase operations are timed using a clock derived from the oscillator using the
FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within the limits
specified as fNVMOP.
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The minimum program and erase times shown in Table B-8 are calculated for maximum fNVMOP and
maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz.

B.5.1.1 Single Word Programming

The programming time for single word programming is dependant on the bus frequency as a well as on
the frequency f¨NVMOP and can be calculated according to the following formula.
1 1
t swpgm = 9 ⋅ --------------------- + 25 ⋅ ----------
f NVMOP f bus

B.5.1.2 Burst Programming

This applies only to the Flash where up to 32 words in a row can be programmed consecutively using burst
programming by keeping the command pipeline filled. The time to program a consecutive word can be
calculated as:
1 1
t bwpgm = 4 ⋅ --------------------- + 9 ⋅ ----------
f NVMOP f bus

The time to program a whole row is:

t brpgm = t swpgm + 31 ⋅ t bwpgm
Burst programming is more than 2 times faster than single word programming.

B.5.1.3 Sector Erase

Erasing a 512 byte Flash sector takes:

1
t era ≈ 4000 ⋅ ---------------------
f NVMOP

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The setup times can be ignored for this operation.

B.5.1.4 Mass Erase

Erasing a NVM block takes:

1
t mass ≈ 20000 ⋅ ---------------------
f NVMOP
The setup times can be ignored for this operation.

Table B-8 NVM Timing Characteristics

Conditions are shown in Table A-4 unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
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1 D External Oscillator Clock fNVMOSC 0.5 501 MHz

2 D Bus frequency for Programming or Erase Operations fNVMBUS 1 MHz

3 D Operating Frequency fNVMOP 150 200 kHz

4 P Single Word Programming Time tswpgm 462 74.53 µs

5 D Flash Burst Programming consecutive word tbwpgm 20.42 313 µs

6 D Flash Burst Programming Time for 32 Words tbrpgm 678.42 1035.53 µs

7 P Sector Erase Time tera 204 26.73 ms

8 P Mass Erase Time tmass 1004 1333 ms

9 D Blank Check Time Flash per block t check 115 327786 tcyc

NOTES:
1. Restrictions for oscillator in crystal mode apply!
2. Minimum Programming times are achieved under maximum NVM operating frequency f NVMOP and maximum bus frequen-
cy fbus.
3. Maximum Erase and Programming times are achieved under particular combinations of f NVMOP and bus frequency f bus
. Refer to formulae in Sections A.3.1.1 - A.3.1.4 for guidance.
4. Minimum Erase times are achieved under maximum NVM operating frequency f NVMOP .
5. Minimum time, if first word in the array is not blank
6. Maximum time to complete check on an erased block.

B.5.2 NVM Reliability

The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process
monitors and burn-in to screen early life failures.
The failure rates for data retention and program/erase cycling are specified at <2ppm defects over lifetime
at the operating conditions noted.
A program/erase cycle is specified as two transitions of the cell value from erased → programmed →
erased, 1 → 0 → 1.

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NOTE: All values shown in Table B-9 are target values and subject to further extensive
characterization.
Table B-9 NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
Data Retention at an average junction temperature of
1 C tNVMRET 15 Years
TJavg = 85°C

2 C Flash number of Program/Erase cycles nFLPE 10,000 Cycles

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B.6 Reset, Oscillator and PLL

This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).

B.6.1 Startup

Table B-10 summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
Table B-10 Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
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1 T POR release level VPORR 2.07 V

2 T POR assert level VPORA 0.97 V

3 D Reset input pulse width, minimum input time PWRSTL 2 tosc

4 D Startup from Reset nRST 192 196 nosc

Interrupt pulse width, IRQ edge-sensitive

5 D PWIRQ 20 ns
mode
6 D Wait recovery startup time tWRS 14 tcyc

B.6.1.1 SRAM Data Retention

Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.

B.6.1.2 External Reset

When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.

B.6.1.3 Stop Recovery

Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.

B.6.1.4 Pseudo Stop and Wait Recovery

The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in
both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts
fetching the interrupt vector.

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B.6.2 Oscillator

The device features an internal Colpitts oscillator. By asserting the XCLKS input during reset this
oscillator can be bypassed allowing the input of a square wave. Before asserting the oscillator to the
internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP
or oscillator fail. tCQOUT specifies the maximum time before switching to the internal self clock mode in
case no proper oscillation is detected. The quality monitor also determines the minimum oscillator start-up
time tUPOSC. The device features a clock monitor. A time-out is asserted if the frequency of the incoming
clock signal is below the Clock Monitor FailureAssert Frequency fCMFA.
Table B-11 Oscillator Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
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1a C Crystal oscillator range (Colpitts) fOSC 0.5 16 MHz

1b C Crystal oscillator range (Pierce) 1(4) fOSC 0.5 40 MHz

2 P Startup Current iOSC 100 µA

3 C Oscillator start-up time (Colpitts) tUPOSC 82 1003 ms

4 D Clock Quality check time-out tCQOUT 0.45 2.5 s

5 P Clock Monitor Failure Assert Frequency fCMFA 50 100 200 KHz

6 P External square wave input frequency 4 fEXT 0.5 50 MHz

7 D External square wave pulse width low tEXTL 9.5 ns

8 D External square wave pulse width high tEXTH 9.5 ns

9 D External square wave rise time tEXTR 1 ns

10 D External square wave fall time tEXTF 1 ns

11 D Input Capacitance (EXTAL, XTAL pins) CIN 7 pF

DC Operating Bias in Colpitts Configuration
12 C VDCBIAS 1.1 V
on EXTAL Pin
NOTES:
1. Depending on the crystal a damping series resistor might be necessary
2. fosc = 4MHz, C = 22pF.
3. Maximum value is for extreme cases using high Q, low frequency crystals
4. XCLKS =0 during reset

B.6.3 Phase Locked Loop

The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.

B.6.3.1 XFC Component Selection

This section describes the selection of the XFC components to achieve a good filter characteristics.

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Cp

VDDPLL

Cs R XFC Pin
Phase VCO
fosc 1 fref fvco
∆ KΦ KV
refdv+1
Detector
fcmp
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Loop Divider
1 1
synr+1 2

Figure B-3 Basic PLL functional diagram

The following procedure can be used to calculate the resistance and capacitance values using typical
values for K1, f1 and ich from Table B-12.
The grey boxes show the calculation for fVCO = 50MHz and fref = 1MHz. E.g., these frequencies are used
for fOSC = 4MHz and a 25MHz bus clock.
The VCO Gain at the desired VCO frequency is approximated by:
( f 1 – f vco ) ( 60 – 50 )
----------------------- ------------------------
K 1 ⋅ 1V – 100
KV = K1 ⋅ e = – 100 ⋅ e = -90.48MHz/V
The phase detector relationship is given by:

K Φ = – i ch ⋅ K V = 316.7Hz/Ω
ich is the current in tracking mode.
The loop bandwidth fC should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
typical values are 50. ζ = 0.9 ensures a good transient response.

2 ⋅ ζ ⋅ f ref 1 f ref
f C < ------------------------------------------ ------ → f C < -------------- ;( ζ = 0.9 )
2 10 4 ⋅ 10

π⋅ ζ+ 1+ζ
  fC < 25kHz

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And finally the frequency relationship is defined as

f VCO
n = ------------- = 2 ⋅ ( synr + 1 ) = 50
f ref

With the above values the resistance can be calculated. The example is shown for a loop bandwidth
fC=10kHz:
2 ⋅ π ⋅ n ⋅ fC
R = ----------------------------- = 2*π*50*10kHz/(316.7Hz/Ω)=9.9kΩ=~10kΩ
KΦ

The capacitance Cs can now be calculated as:

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2
2⋅ζ 0.516
C s = ---------------------- ≈ --------------- ;( ζ = 0.9 ) = 5.19nF =~ 4.7nF
π ⋅ fC ⋅ R fC ⋅ R

The capacitance Cp should be chosen in the range of:

C s ⁄ 20 ≤ C p ≤ C s ⁄ 10 Cp = 470pF

B.6.3.2 Jitter Information

The basic functionality of the PLL is shown in Figure B-3. With each transition of the clock fcmp, the
deviation from the reference clock fref is measured and input voltage to the VCO is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure B-4.

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0 1 2 3 N-1 N

tmin1
tnom
tmax1

tminN
tmaxN
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Figure B-4 Jitter Definitions

The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger
number of clock periods (N).
Defining the jitter as:

 t max ( N ) t min ( N ) 
J ( N ) = max  1 – --------------------- , 1 – --------------------- 
 N ⋅ t nom N ⋅ t nom 

For N < 100, the following equation is a good fit for the maximum jitter:

j1
J ( N ) = -------- + j 2
N

J(N)

1 5 10 20 N

Figure B-5 Maximum bus clock jitter approximation

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This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the
effect of the jitter to a large extent.

Table B-12 PLL Characteristics

Conditions are shown in Table A-4 unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 P Self Clock Mode frequency fSCM 1 5.5 MHz

2 D VCO locking range fVCO 8 50 MHz

Lock Detector transition from Acquisition to Tracking
3 D |∆trk| 3 4 %1
mode

4 D Lock Detection |∆Lock| 0 1.5 %(1)

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5 D Un-Lock Detection |∆unl| 0.5 2.5 %(1)

Lock Detector transition from Tracking to Acquisition
6 D |∆unt| 6 8 %(1)
mode

7 C PLLON Total Stabilization delay (Auto Mode) 2 tstab 0.5 ms

8 D PLLON Acquisition mode stabilization delay (2) tacq 0.3 ms

9 D PLLON Tracking mode stabilization delay (2) tal 0.2 ms

10 D Fitting parameter VCO loop gain K1 -100 MHz/V

11 D Fitting parameter VCO loop frequency f1 60 MHz

12 D Charge pump current acquisition mode | ich | 38.5 µA

13 D Charge pump current tracking mode | ich | 3.5 µA

14 C Jitter fit parameter 1(2) j1 1.1 %

15 C Jitter fit parameter 2(2) j2 0.13 %

NOTES:
1. % deviation from target frequency
2. fOSC = 4MHz, fBUS = 25MHz equivalent fVCO = 50MHz: REFDV = #$03, SYNR = #$018, Cs = 4.7nF, Cp = 470pF, Rs =
10KΩ.

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B.7 MSCAN
Table B-13 MSCAN Wake-up Pulse Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C Rating Symbol Min Typ Max
1 P MSCAN Wake-up dominant pulse filtered tWUP 2

2 P MSCAN Wake-up dominant pulse pass tWUP 5

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B.8 SPI

Appendix C Electrical Specifications

This section provides electrical parametrics and ratings for the SPI.
In Table C-1 the measurement conditions are listed.
Table C-1 Measurement Conditions
Description Value Unit
Drive mode full drive mode —
Load capacitance CLOAD,
50 pF
on all outputs
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Thresholds for delay

(20% / 80%) VDDX V
measurement points

C.1 Master Mode

In Figure C-1 the timing diagram for master mode with transmission format CPHA=0 is depicted.

SS1
(OUTPUT)

2 1 12 13 3
SCK 4
(CPOL = 0)
(OUTPUT) 4
12 13
SCK
(CPOL = 1)
(OUTPUT)
5 6
MISO
(INPUT) MSB IN2 BIT 6 . . . 1 LSB IN

10 9 11

MOSI
(OUTPUT) MSB OUT2 BIT 6 . . . 1 LSB OUT

1.if configured as an output.

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure C-1 SPI Master Timing (CPHA=0)

In Figure C-2 the timing diagram for master mode with transmission format CPHA=1 is depicted.

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SS1
(OUTPUT)
1
2 12 13 3
SCK
(CPOL = 0)
(OUTPUT)
4 4 12 13
SCK
(CPOL = 1)
(OUTPUT)
5 6
MISO
(INPUT) MSB IN2 BIT 6 . . . 1 LSB IN
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9 11
MOSI
(OUTPUT) PORT DATA MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA

1.If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure C-2 SPI Master Timing (CPHA=1)

In Table C-2 the timing characteristics for master mode are listed.

Table C-2 SPI Master Mode Timing Characteristics

Num C Characteristic Symbol Unit

Min Typ Max
1 P SCK Frequency fsck 1/2048 — 1/2 fbus
1 P SCK Period tsck 2 — 2048 tbus
2 D Enable Lead Time tlead — 1/2 — tsck
3 D Enable Lag Time tlag — 1/2 — tsck
4 D Clock (SCK) High or Low Time twsck — 1/2 — tsck
5 D Data Setup Time (Inputs) tsu 8 — — ns
6 D Data Hold Time (Inputs) thi 8 — — ns
9 D Data Valid after SCK Edge tvsck — — 30 ns
10 D Data Valid after SS fall (CPHA=0) tvss — — 15 ns
11 D Data Hold Time (Outputs) tho 20 — — ns
12 D Rise and Fall Time Inputs trfi — — 8 ns
13 D Rise and Fall Time Outputs trfo — — 8 ns

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C.2 Slave Mode

In Figure C-3 the timing diagram for slave mode with transmission format CPHA=0 is depicted.

SS
(INPUT)

1 12 13 3
SCK
(CPOL = 0)
(INPUT)
2 4 4
12 13
SCK
(CPOL = 1)
(INPUT) 10 8
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7 9 11 11
MISO see SEE
(OUTPUT) note SLAVE MSB BIT 6 . . . 1 SLAVE LSB OUT NOTE

5 6
MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN

NOTE: Not defined!

Figure C-3 SPI Slave Timing (CPHA=0)

In Figure C-4 the timing diagram for slave mode with transmission format CPHA=1 is depicted.

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SS
(INPUT)
1 3
2 12 13
SCK
(CPOL = 0)
(INPUT)
4 4 12 13
SCK
(CPOL = 1)
(INPUT)
9 11 8
MISO see
(OUTPUT) note SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT
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7 5 6
MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN

NOTE: Not defined!

Figure C-4 SPI Slave Timing (CPHA=1)

In Table C-3 the timing characteristics for slave mode are listed.
Table C-3 SPI Slave Mode Timing Characteristics

Num C Characteristic Symbol Unit

Min Typ Max
1 P SCK Frequency fsck DC — 1/4 fbus
1 P SCK Period tsck 4 — ∞ tbus
2 D Enable Lead Time tlead 4 — — tbus
3 D Enable Lag Time tlag 4 — — tbus
4 D Clock (SCK) High or Low Time twsck 4 — — tbus
5 D Data Setup Time (Inputs) tsu 8 — — ns
6 D Data Hold Time (Inputs) thi 8 — — ns
Slave Access Time (time to data
7 D ta — — 20 ns
active)
8 D Slave MISO Disable Time tdis — — 22 ns
9 D Data Valid after SCK Edge tvsck — — 30 + tbus 1 ns

10 D Data Valid after SS fall tvss — — 30 + tbus 1 ns

11 D Data Hold Time (Outputs) tho 20 — — ns
12 D Rise and Fall Time Inputs trfi — — 8 ns
13 D Rise and Fall Time Outputs trfo — — 8 ns
NOTES:
1. tbus added due to internal synchronization delay

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C.3 External Bus Timing

A timing diagram of the external multiplexed-bus is illustrated in Figure C-5 with the actual timing
values shown on table Table C-4. All major bus signals are included in the diagram. While both a data
write and data read cycle are shown, only one or the other would occur on a particular bus cycle.

C.3.1 General Muxed Bus Timing

The expanded bus timings are highly dependent on the load conditions. The timing parameters shown
assume a balanced load across all outputs.

Figure C-5 General External Bus Timing

1, 2
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3 4

ECLK
PE4

5 6 16 10
9 15 11
Addr/Data
data addr data
(read)
PA, PB
7
8

12 14 13
Addr/Data
data addr data
(write)
PA, PB

17 18 19
R/W
PE2

20 21 22
LSTRB
PE3

23 24 25
NOACC
PE7

26 27 28 29
PIPO0
PIPO1, PE6,5

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Table C-4 Expanded Bus Timing Characteristics (5V Range)

Conditions are 4.75V < VDDX < 5.25V, Junction Temperature -40˚C to +140˚C, CLOAD = 50pF

Num C Rating Symbol Min Typ Max Unit

1 P Frequency of operation (E-clock) fo 0 25.0 MHz

2 P Cycle time tcyc 40 ns

3 D Pulse width, E low PWEL 19 ns

4 D Pulse width, E high1 PWEH 19 ns

5 D Address delay time tAD 8 ns

6 D Address valid time to E rise (PWEL–tAD) tAV 11 ns

7 D Muxed address hold time tMAH 2 ns

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8 D Address hold to data valid tAHDS 7 ns

9 D Data hold to address tDHA 2 ns

10 D Read data setup time tDSR 13 ns

11 D Read data hold time tDHR 0 ns

12 D Write data delay time tDDW 7 ns

13 D Write data hold time tDHW 2 ns

14 D Write data setup time(1) (PWEH–tDDW) tDSW 12 ns

15 D Address access time(1) (tcyc–tAD–tDSR) tACCA 19 ns

16 D E high access time(1) (PWEH–tDSR) tACCE 6 ns

17 D Read/write delay time tRWD 7 ns

18 D Read/write valid time to E rise (PWEL–tRWD) tRWV 14 ns

19 D Read/write hold time tRWH 2 ns

20 D Low strobe delay time tLSD 7 ns

21 D Low strobe valid time to E rise (PWEL–tLSD) tLSV 14 ns

22 D Low strobe hold time tLSH 2 ns

23 D NOACC strobe delay time tNOD 7 ns

24 D NOACC valid time to E rise (PWEL–tLSD) tNOV 14 ns

25 D NOACC hold time tNOH 2 ns

26 D IPIPO[1:0] delay time tP0D 2 7 ns

27 D IPIPO[1:0] valid time to E rise (PWEL–tP0D) tP0V 11 ns

28 D IPIPO[1:0] delay time(1) (PWEH-tP1V) tP1D 2 25 ns

29 D IPIPO[1:0] valid time to E fall tP1V 11 ns

NOTES:
1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.

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Table C-5 Expanded Bus Timing Characteristics (3.3V Range)

Conditions are VDDX=3.3V+/-10%, Junction Temperature -40˚C to +140˚C, CLOAD = 50pF

Num C Rating Symbol Min Typ Max Unit

1 P Frequency of operation (E-clock) fo 0 16.0 MHz

2 P Cycle time tcyc 62.5 ns

3 D Pulse width, E low PWEL 30 ns

4 D Pulse width, E high1 PWEH 30 ns

5 D Address delay time tAD 16 ns

6 D Address valid time to E rise (PWEL–tAD) tAV 16 ns

7 D Muxed address hold time tMAH 2 ns

8 D Address hold to data valid tAHDS 7 ns

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9 D Data hold to address tDHA 2 ns

10 D Read data setup time tDSR 15 ns

11 D Read data hold time tDHR 0 ns

12 D Write data delay time tDDW 15 ns

13 D Write data hold time tDHW 2 ns

14 D Write data setup time(1) (PWEH–tDDW) tDSW 15 ns

15 D Address access time(1) tACCA 29 ns

16 D E high access time(1) (PWEH–tDSR) tACCE 15 ns

17 D Read/write delay time tRWD 14 ns

18 D Read/write valid time to E rise (PWEL–tRWD) tRWV 16 ns

19 D Read/write hold time tRWH 2 ns

20 D Low strobe delay time tLSD 14 ns

21 D Low strobe valid time to E rise (PWEL–tLSD) tLSV 16 ns

22 D Low strobe hold time tLSH 2 ns

23 D NOACC strobe delay time tNOD 14 ns

24 D NOACC valid time to E rise (PWEL–tLSD) tNOV 16 ns

25 D NOACC hold time tNOH 2 ns

26 D IPIPO[1:0] delay time tP0D 2 14 ns

27 D IPIPO[1:0] valid time to E rise (PWEL–tP0D) tP0V 16 ns

28 D IPIPO[1:0] delay time(1) tP1D 2 25 ns

29 D IPIPO[1:0] valid time to E fall tP1V 11 ns

NOTES:
1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.

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Appendix D Package Information

D.1 General
This section provides the physical dimensions of the MC9S12C32 packages 48LQFP, 52LQFP, 80QFP.
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D.2 80-pin QFP package

60 41
61 40

S
S
B

D
D
P

S
S
B
-A- -B-

C A-B
H A-B
L B V

0.05 D

M
M
-A-,-B-,-D-

0.20
0.20
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DETAIL A
DETAIL A

21
80

1 20
F
-D-
A
0.20 M H A-B S D S

0.05 A-B
J N
S
0.20 M C A-B S D S

D
M
E DETAIL C 0.20 M C A-B S D S

SECTION B-B
C DATUM
VIEW ROTATED 90 °
-H- PLANE
-C- 0.10
SEATING H
PLANE M
G

NOTES: MILLIMETERS
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982. DIM MIN MAX
2. CONTROLLING DIMENSION: MILLIMETER. A 13.90 14.10
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF B 13.90 14.10
LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC C 2.15 2.45
U BODY AT THE BOTTOM OF THE PARTING LINE. D 0.22 0.38
4. DATUMS -A-, -B- AND -D- TO BE E 2.00 2.40
T DETERMINED AT DATUM PLANE -H-.
F 0.22 0.33
5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -C-. G 0.65 BSC
DATUM -H- 6. DIMENSIONS A AND B DO NOT INCLUDE H --- 0.25
PLANE R MOLD PROTRUSION. ALLOWABLE J 0.13 0.23
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH K 0.65 0.95
AND ARE DETERMINED AT DATUM PLANE -H-. L 12.35 REF
7. DIMENSION D DOES NOT INCLUDE DAMBAR M 5° 10 °
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 TOTAL IN N 0.13 0.17
EXCESS OF THE D DIMENSION AT MAXIMUM P 0.325 BSC
K Q MATERIAL CONDITION. DAMBAR CANNOT Q 0° 7°
W BE LOCATED ON THE LOWER RADIUS OR R 0.13 0.30
THE FOOT.
S 16.95 17.45
X T 0.13 ---
DETAIL C U 0° ---
V 16.95 17.45
W 0.35 0.45
X 1.6 REF

Figure D-1 80-pin QFP Mechanical Dimensions (case no. 841B)

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D.3 52-pin LQFP package

4X 4X 13 TIPS
0.20 (0.008) H L-M N 0.20 (0.008) T L-M N
-X-
X=L, M, N
52 40
1 39 CL
AB G
3X VIEW Y
-L- -M- AB
B V
VIEW Y

BASE METAL
B1 PLATING F
V1

13 27
14 26 J U
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-N- D
A1
0.13 (0.005) M T L-M S N S
S1
A SECTION AB-AB
ROTATED 90 ° CLOCKWISE
S NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
4X θ2 THE LEAD EXITS THE PLASTIC BODY AT THE
C BOTTOM OF THE PARTING LINE.
0.10 (0.004) T 4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT
DATUM PLANE -H-.
-H- 5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE -T-.
-T- 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
SEATING 4X θ3 (0.010) PER SIDE. DIMENSIONS A AND B DO
PLANE
INCLUDE MOLD MISMATCH AND ARE
VIEW AA DETERMINED AT DATUM PLANE -H-
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL NOT
CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018).
MINIMUM SPACE BETWEEN PROTRUSION AND
ADJACENT LEAD OR PROTRUSION 0.07 (0.003).

0.05 (0.002) S

W 2X R R1
MILLIMETERS INCHES
θ1 DIM
A
MIN MAX
10.00 BSC
MIN
0.394 BSC
MAX

A1 5.00 BSC 0.197 BSC

0.25 (0.010) B 10.00 BSC 0.394 BSC
C2
θ B1 5.00 BSC 0.197 BSC
C --- 1.70 --- 0.067
GAGE PLANE C1 0.05 0.20 0.002 0.008
C2 1.30 1.50 0.051 0.059
D 0.20 0.40 0.008 0.016
K E 0.45 0.75 0.018 0.030
C1 F 0.22 0.35 0.009 0.014
E G 0.65 BSC 0.026 BSC
VIEW AA Z
J 0.07 0.20 0.003 0.008
K 0.50 REF 0.020 REF
R1 0.08 0.20 0.003 0.008
S 12.00 BSC 0.472 BSC
S1 6.00 BSC 0.236 BSC
U 0.09 0.16 0.004 0.006
V 12.00 BSC 0.472 BSC
V1 6.00 BSC 0.236 BSC
W 0.20 REF 0.008 REF
Z 1.00 REF 0.039 REF
θ 0° 7° 0° 7°
θ1 0° --- 0° ---
θ2 12 ° REF 12 ° REF
θ3 12 ° REF 12 ° REF

Figure D-2 52-pin LQFP Mechanical Dimensions (case no. 848D-03)

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D.4 48-pin LQFP package

4X
NOTES:
0.200 AB T-U Z 1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
1. CONTROLLING DIMENSION: MILLIMETER.
DETAIL Y 2. DATUM PLANE AB IS LOCATED AT BOTTOM
9 A P OF LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
A1 BODY AT THE BOTTOM OF THE PARTING
48 37 LINE.
3. DATUMS T, U, AND Z TO BE DETERMINED AT
DATUM PLANE AB.
4. DIMENSIONS S AND V TO BE DETERMINED
1 AT SEATING PLANE AC.
36 5. DIMENSIONS A AND B DO NOT INCLUDE
T U MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH AND
ARE DETERMINED AT DATUM PLANE AB.
B V 6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
AE AE 0.350.
B1 7. MINIMUM SOLDER PLATE THICKNESS
V1 SHALL BE 0.0076.
12 25 8. EXACT SHAPE OF EACH CORNER IS
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OPTIONAL.

13 24 MILLIMETERS
DIM MIN MAX
Z A 7.000 BSC
S1 A1 3.500 BSC
T, U, Z B 7.000 BSC
B1 3.500 BSC
S C 1.400 1.600
DETAIL Y D 0.170 0.270
4X E 1.350 1.450
F 0.170 0.230
0.200 AC T-U Z G 0.500 BSC
H 0.050 0.150
J 0.090 0.200
K 0.500 0.700
L 0 ° 7°
G 0.080 AC M 12 ° REF
AB N 0.090 0.160
P 0.250 BSC
R 0.150 0.250
S 9.000 BSC
S1 4.500 BSC
V 9.000 BSC
AD V1 4.500 BSC
AC W 0.200 REF
AA 1.000 REF
BASE METAL M°
TOP & BOTTOM
R
GAUGE PLANE

N J
0.250

C E
F
D
0.080 M AC T-U Z
SECTION AE-AE H W
L°
DETAIL AD K
AA

Figure D-3 48-pin LQFP Mechanical Dimensions (case no.932-03 ISSUE F)

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Device User Guide End Sheet

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