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CS-393 Lab 4

This document provides instructions for a lab assignment to implement a ROM and RAM using VHDL. Students are asked to create a 16-word 32-bit ROM using behavioral and LPM implementations, and a 16-word 32-bit RAM using behavioral and LPM_RAM_DQ implementations. Examples of behavioral ROM code and a LPM ROM component declaration are given. Notes on the LPM_RAM_DQ component parameters and operation are also provided. Students must test and simulate their designs and submit a report documenting their work.

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83 views3 pages

CS-393 Lab 4

This document provides instructions for a lab assignment to implement a ROM and RAM using VHDL. Students are asked to create a 16-word 32-bit ROM using behavioral and LPM implementations, and a 16-word 32-bit RAM using behavioral and LPM_RAM_DQ implementations. Examples of behavioral ROM code and a LPM ROM component declaration are given. Notes on the LPM_RAM_DQ component parameters and operation are also provided. Students must test and simulate their designs and submit a report documenting their work.

Uploaded by

malekhammami6
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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CS-393

Lab 4

You are to use VHDL to implement a ROM and a RAM. The ROM will be a 16 word (32
bit) ROM. The ROM is to have the following inputs and outputs:

Input
Address (4 bits)

Output
Data_out (32 bits)

Below is a sample of the VHDL code needed to create a ROM. Note the creation of a
new type called mem_array. It uses a VHDL built-in type called array. This example
creates a ROM with 8 locations of 32 bits each. Another important thing to note is that
VHDL does not allow the MSB of a 32-bit value to be 1. Keep this in mind for later
designs.
Another way to create a ROM is by way of the LPM library. A sample of the VHDL
code needed to create a ROM in this manner is also provided below. The LPM_ROM
component has its contents provided by a memory initialization file (.mif extension). I
have placed an example of a mif file on my home page. (The ROM example is also
included. Both files are in .zip file that you can download.) You must also implement the
ROM using the LPM_ROM component. Initialize it with the same contents used in the
first version of the ROM. An advantage of the LPM version of the ROM is that the MSB
of a 32-bit value can be 1. Refer to the report files for each design to compare the chip
resources used by each.

After implementing the ROMs, implement a 16 word (32 bit) RAM. The RAM will have
the following inputs and outputs:

Input
Address(4 bits), write_data (32 bits), MemWrite (1 bit), MemRead (1 bit)

Output
Read_data (32 bits)

MemRead and MemWrite are asserted when you are reading or writing the data,
respectively.

The write process for the RAM must be clocked on the rising edge of the system clock.
The read process is asynchronous (as it is for the ROM). You must implement the RAM
behaviorally and using the LPM_RAM_DQ. Be sure to thoroughly read about the
LPM_RAM_DQ in the Altera help file. Some notes regarding the LPM_RAM_DQ:

• The LPM_OUTDATA should be “UNREGISTERED” to allow asynchronous


reads
• The LPM_ADDRESS_CONTROL should also be “UNREGISTERED”

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Lab 4
• The LPM_INDATA should be “REGISTERED” to allow input to be
synchronous. This means that the inclock is needed and should be connected to
the clock in your port statement.
• To assure that the address is stable at the time we = 1, do the following:

Lpm_write <= MemWrite and (NOT clock);

Where MemWrite is in your port statement and lpm_write is a signal


connected to we in the LPM_RAM_DQ port map.

You must use MAX+PlusII simulator to verify correct operation of your designs. Be sure
to test thoroughly since the designs will be used in upcoming projects. You are to work
alone on this assignment. It should be completed by time of the lab in week 4. The report
will be due in the lab of week 5. Your report should contain a documented listing of your
VHDL files, any GDF files, simulation results, a discussion of your testing methods and a
discussion of the results.

-- behavioral version of ROM implementation


--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--
--
entity rom_mem is
port
(
data_out: out std_logic_vector(31 downto 0);
address: in std_logic_vector(2 downto 0)
);
end rom_mem;
--
--
architecture behavioral of rom_mem is
type mem_array is array(0 to 7) of std_logic_vector(31 downto 0);
signal mem: mem_array;

begin
read: process(address)
-- index is an index into the array
variable index: integer range 0 to 7 := 0; -- initialize index to 0
begin

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Lab 4
-- initialize the ROM contents
mem(0) <= x”70000000”;
mem(1) <= x”00018000”;
mem(2) <= x”00180000”;
mem(3) <= x”01800000”;
mem(4) <= x”18000000”;
mem(5) <= x”00000001”;
mem(6) <= x”00000002”;
mem(7) <= x”00000004”;
-- The conv_integer function is in the .std_logic_arith package
-- Convert the address vector into an integer to access array element
index := conv_integer( address(2 downto 0));
data_out <= mem(index);
end process;
end behavioral;

-- Example of a ROM created using LPM_ROM component

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library lpm;
use lpm.lpm_components.all;
entity myrom is
port(addr: in std_logic_vector(2 downto 0);
data: out std_logic_vector(31 downto 0));
end myrom;
architecture structural of myrom is
begin
tcgrom: lpm_rom
generic map ( lpm_widthad => 3,
lpm_outdata => "unregistered",
lpm_address_control => "unregistered",
lpm_file => "mipsrom.mif", -- init data
lpm_width => 32)
port map ( address => addr, q => data);
end structural;

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