Analyzing Static Noise Margin for Sub-

threshold SRAM in 65nm CMOS

Benton H. Calhoun and Anantha Chandrakasan

MIT, 50 Vassar St 38-107, Cambridge, MA, 02139 USA {bcalhoun,anantha}@mtl.mit.edu

Abstract: as the length of the side of a square fitted between the

VTCs and having the longest diagonal [5]. As the value
This paper evaluates the static noise margin (SNM) of 6T of the noise sources increases, the VTC-1 for inverter 1 in
SRAM bitcells operating in sub-threshold. We analyze the figure moves upward and the VTC for inverter 2
the dependence of SNM during both hold and read moves to the left. Once they both move by the SNM
modes on supply voltage, temperature, transistor sizes, value, the curves meet at only two points. Any further
local transistor mismatch due to random doping noise flips the cell. Figure 1(b) also shows that the SNM
variation, and global process variation in a commercial is lower during read access because the VTC is degraded
65nm technology. We analyze the statistical distribution by the voltage divider across the access transistor
of SNM with process variation and provide a model for (M2,M5) and drive transistor (M1,M4).
the tail of the PDF that dominates SNM failures. An expression for above-threshold SNM based on long-
channel models is given in [5], and [6] models above-
1. Introduction threshold SNM for modern processes with process
variation. This paper builds on previous work by
This paper provides a thorough evaluation of static noise examining SNM for sub-threshold SRAM. The next
margin (SNM) for SRAM bitcells functioning in the sub- section provides 1st-order equations for the VTCs in sub-
threshold region. Sub-threshold digital circuit design has threshold and evaluates their accuracy. Section 3
emerged as a low energy solution for applications with describes the impact of various parameters on SNM.
strict energy constraints, such as micro-sensor networks. Local mismatch due to random doping variation and
Analysis of sub-threshold designs has focused on logic global process variation provide the focus since these
circuits (e.g. [1]). The large fraction of chip area often have the dominant effect on SNM.
devoted to SRAM makes low power SRAM design very
important as well. Recent low power memories show a 2. Modeling Sub-VT Static Noise Margin
trend of lower voltages with some designs holding state
on the edge of the sub-threshold region (e.g. [2]). This It is well-known that lowering VDD reduces gate current
scaling will continue, leading to sub-threshold storage much more rapidly than sub-threshold current, so total
modes and even sub-threshold operation for SRAM’s current in the sub-threshold region is given by (1).
operating in tandem with sub-threshold logic.  V − VT   −V 
I D = I S exp GS 1 − exp DS   (1)
The minimum voltage for retaining bistability was  
 nVth   Vth 
theorized in [3] and modeled for SRAM in [4], but
degraded SNM can limit voltage scaling for SRAM The sub-threshold factor n=1+Cds/Cox, Vth=kT/q, and IS
designs above this minimum voltage. SNM quantifies the is the current when VGS equals VT. For simplicity, we
amount of voltage noise required at the internal nodes of treat PMOS parameters as positive values. For the 65nm
technology used in this paper, the NMOS drive current is
a bitcell to flip the cell’s contents. Figure 1(a) shows the
location of the noise sources in the 6 transistor (6T) higher in above-threshold than the PMOS for iso-width,
bitcell schematic. Figure 1(b) provides the common but the PMOS current is higher in sub-threshold. During
graphical representation of SNM for a cell during read hold mode, WL=0 so M2 and M5 have VGS ≤ 0 and thus
access and while holding data (un-accessed). The voltage negligible current. We can model the cell VTCs (VOUT =
transfer curves (VTCs) of the two inverters are shown fVTC(VIN)) as those of a simple inverter in sub-threshold.
with one VTC inverted. The SNM is found graphically n1n3  I S 3  1 − exp((−VDD + Q ) / Vth )  
Vth ln + ln  
n1 + n3  I S 1  1 − exp( −Q / Vth ) 

VDD Read QB = (2)
WL n1VDD n n V V 
WL + + 1 3  T 1 − T 3 
M3
Hold n1 + n3 n1 + n3  n1 n3 
M6
+- M5 Equation (2) [3] gives the inverse VTC for inverter 1
QB

M2 +-
QB (VIN=fVTC-1(VOUT)). The inverse of (2) is given in [7] for
Q M1 M4 VTC
−1
inv1 matched PMOS and NMOS (same n, VT, IS). We give a
BL BLB full solution for VOUT=fVTC(VIN) for inverter 2 in (3).
VTC inv2
  −V DD 
Inv1 Inv2   
(a) (b) Q QB = VDD + Vth ln 0.5 * 1 − G + (G − 1) 2 + 4e Vth G  ,
  
Figure 1: Schematic for 6T bitcell showing voltage    (3)
 n4 + n6 I V 1  VT 4 VT 6  
noise sources for finding SNM (a). SNM plots (b). G = exp Q − ln S 6
− DD
−  − 
 n4 n6Vth I S 4 n6Vth Vth  n4 n6  
Figure 2(a) plots (2) and (3) against simulation curves for in the chip’s environment create a distribution of SNM
no local mismatch and for 1σ VT mismatch in M6. across the bitcells in a given memory, and the worst-case
During a read access, WL=VDD and the bitlines are tail of this distribution determines the yield. This section
precharged to VDD so, if Q=0 prior to access, M1 and M2 examines the impact of different parameters on SNM in
are both on. This creates a voltage division that raises the sub-threshold and offers a model for estimating the tail
voltage at Q. Assuming PMOS current is negligible in of the SNM density function for process variation.
the region of interest, (4) shows the inverse VTC
equation near the SNM [2] for inverter 1. 3.1 Dependence on VDD
I  1 − exp(( −VDD + Q ) / Vth )  SNM for a bitcell with ideal VTCs is still limited to
n1Vth ln S 2 + n1Vth ln  
I S1  1 − exp(−Q / Vth )  VDD/2 because of the two sides of the butterfly curve. An
QB = (4)
n1 upper limit on the change in SNM with VDD is thus ½.
+ VT 1 + (VDD − VT 2 − Q ) Figure 4 shows how SNM varies with VDD for both hold
n2
and read mode. The slopes of the curves confirm that less
This equation cannot be inverted analytically, and it than ½ of VDD noise will translate into SNM changes.
applies only to the region of the VTC where VOUT is low.
Figure 2(b) shows (4) and its graphical inverse combined 0.5
Hold
piecewise with (2) and (3) and plotted against simulation 0.4
Read
VDD/2
for no local mismatch and for 1σ VT mismatch in M1 for
minimum device sizes at 25oC. 0.3

SNM (V)
sims sims 0.2
V −1σ (4);(2)
T6 eqns eqns
0.1
QB

QB

0
0 0.2 0.4 0.6 0.8 1 1.2
VDD (V)

(2) VT1−1σ Figure 4: SNM versus VDD.

(3)
(3); (4) graphical 3.2 Dependence on Temperature
inverse
Q Q Varying temperature from -40oC to 125oC only alters
(a) Hold (b) Read read and hold SNM by 21mV and 6mV, respectively.
Figure 2: 1st-order VTC equations versus simulations. Higher temperatures lower SNM in sub-threshold due to
the degraded gain in the inverters that results from worse
Graphical or numerical solutions for SNM are easily sub-threshold slope (see Figure 3(b)). Also, PMOS
derived from the VTC equations, although no direct devices weaken relative to NMOS at higher temperature.
analytical solution exists. The equations provide a good
3.3 Dependence on Sizing
estimate of the behavior of the SNM based on key
parameters. One shortcoming of (2)-(4) is the assumption In contrast to above-threshold [8], Figure 5 shows that
that sub-threshold slope (S=nVthln10) is constant for cell ratio ((W/L)1/(W/L)2 or (W/L)4/(W/L)5) has very
each transistor. Figure 3(a) shows that S varies with VGS, little impact on SNM during sub-threshold read. In fact,
and Figure 3(b) shows S changing with temperature sub-threshold SNM sensitivity to any sizing changes is
without the expected constant slope due to Vth. A more reduced. The lower impact of sizing is intuitively
crucial problem with (2)-(4) is the assumption that reasonable considering the exponential dependence of
certain currents are negligible. These assumptions break sub-threshold current on other parameters. Mathe-
down under certain combinations of VT variation, matically, we can see from (2)-(4) that sizing changes
rendering the 1st-order equations inaccurate. affect IS,i linearly and only have a logarithmic impact on
the VTCs. One point of caution here is that VT for deep
1.2 1.15

(b) submicron devices tends to vary with size as a result of

PMOS
NMOS (a) PMOS
NMOS
narrow or short channel effects. The impact of this VT
1.1

change that might accompany a sizing change is more

1.15
VDD=0.3V
normalized S
normalized S

1.1
1.05
pronounced. These effects depend on the technology and
1 make general SNM modeling more complicated.
1.05
0.95 0.5

1 0.9
0 0.1 0.2 0.3 −50 0 50 100 150 0.4
VGS (V) Temperature (oC) Hold
Read 1.2V
Figure 3: Changes in sub-threshold slope (S) versus 0.3
SNM (V)

VGS (a) and temperature (b). 0.2

0.3V
3. Sub-VT SNM Dependencies 0.1

With embedded SRAM often providing multiple 0

megabits of storage, the SNM of the nominal bitcell 1 1.5 2 2.5 3
Cell Ratio
3.5 4 4.5 5

becomes largely irrelevant. Variations in processing and Figure 5: Cell ratio affects SNM less in sub-threshold
3.4 Dependence on Random Doping Variation in each single transistor are overlaid in white. The hold
SNM shows a saturation effect along the upper edge.
The randomness of the number of doping atoms and their SNM high and SNM low are not independent because
placement in a MOSFET channel causes random any change to a VTC that increases the SNM at one side
mismatch even in transistors with identical layout [9]. tends to decrease SNM at the other side.
The impact on threshold voltage, whose σ is proportional
to (WL)-½, is the worst for minimum sized devices which 0.2 0.2
are common in SRAM. The exponential dependence of (a) SNM Hold (b) SNM Read
current on VT in sub-threshold operation makes this
random variation even more influential. Furthermore, the 0.1 0.1
large number of bitcells in many SRAMs makes the tails

SNM low

SNM low
(5-6σ) of the probability density function (PDF) more
critical for modeling since the extreme cases are the 0 0
limiting factor for yield.
Previous work has shown that above-threshold SNM is SNM high SNM high
nearly linear with VT, and modeling ∂SNM / ∂ VTi as a 0 0.1 0.2 0 0.1 0.2
constant allows an approximation of the joint PDF for Figure 8: Scatter plots for SNM high vs. SNM low
SNM [6]. Likewise, the sensitivity of above-threshold
with single FET dependencies overlaid in white.
SNM to VT is linearized for each transistor in [10].
Figure 6(a) shows that the sensitivity of SNM high (the The actual SNM that matters for a bitcell is the
upper-left box in Figure 1(b)) is nearly linear with each minimum of SNM high and SNM low. Thus, the random
individual VT. However, Figure 6(b) shows the relation- variable XSNM = min(XSNMhigh, XSNMlow). Order statistics
ship between SNM and VT4 for a few different values of can provide us with the PDF for the minimum of n
the other VTs. The obvious dependence of the slope on independent, identically distributed (iid) random
the other VTs prevents using a model of the form SNM = variables, Xi. If f is the PDF, and F is the CDF for Xi, the
SNM0+ΣciVTi for sub-threshold SNM. PDF of the minimum of two iid variables is given in (5).
3 5 f (min( X 1 , X 2 )) = 2 f X (1 − FX ) (5)
Norm. Read SNM high

(a) (b) Although SNM high and SNM low are normally
Norm. Read SNM high

2 M1 3 distributed with approximately the same mean and

M4 variance, we have previously shown that they are not
1 M5 1
independent. However, we are less interested in
modeling the entire PDF for SNM than we are in
M3 M6 modeling the worst-case tail. As previously stated, the
0 −1
M2 tail toward lower SNM is the limiting factor. Let us
assume that they are iid. Then we can write:
−1
−5 ∆VT (σ) 5
−3
−5 ∆V (σ) 5 f SNM = 2 f SNMhigh (1 − FSNMhigh ) (6)
T4
Figure 6: Dependence of SNM high on single FETs is Figure 9 shows the histogram for a 5k-point M-C
simulation of read SNM plotted on linear axes (a) and
nearly linear (a) but slope depends on other VTs (b).
semilog axes (b). Clearly, SNM is not normally distri-
600
(a)
600
(b) buted, and its mean is lower than the mean of SNM high
and SNM low. Figure 9(b) shows that a Gaussian PDF
does not match the worst-case tail on the left side of the
400 Hold 400 Hold PDF. On the other hand, the PDF based on (6) provides a
Read Read good estimate of the tail. This PDF gives the powerful
option of estimating the SNM at the worst-case end of
200 200
the PDF without using extremely long M-C simulations.
Figure 10 shows several estimated PDFs using (6) that
3
0 0 500 10
−0.1 0 SNM high (V)0.2 −0.1 0 SNM high (V)0.2 (a) (b)
Figure 7: SNM high and low (not shown) for a min. 2
sized cell (a) and for 4*WL (b) is normally distrib- 10
uted with random VT mismatch in all transistors.
1
250 10
Figure 7 shows the results of 5k-point Monte-Carlo (M-
C) simulations with random independent VT mismatch in 10
0

all transistors. These histograms confirm that sub-

threshold SNM at the upper lobe of the butterfly curve −1
0 10
(SNM high) is normally distributed. The solid lines show −0.1 SNM (V) 0.1 −0.1 SNM (V) 0.1
a fitted Gaussian PDF, and the markers show simulation Figure 9: Histogram of SNM M-C simulation
results. Larger sizes for the bitcell clearly have the (circles) with normal PDF (dash) and PDF based on
advertised effect of lowering the variance of VT as seen (6) (solid) over-laid. The semilog plot (b) shows that
in Figure 7 (b). The SNM low PDFs are very similar.
the PDF based on (6) matches the worst-case tail
The scatter plot in Figure 8 shows that SNM high and
quite well.
SNM low are correlated. The dependencies for mismatch
are based on data sets of different lengths. These that any die within 3σ of the mean is usable, we found
estimates are plotted over a 50k-point M-C simulation. A the global process corner that gives an SNM yield
1000-point M-C simulation gives an estimate that equivalent to -3σ for both hold and read cases. Figure 12
overlays the estimate from the 50k-point case on the plot shows that the impact of mismatch at this 3σ process
(< 3% error). Using this approach allows a designer to corner is essentially to shift the mean of the PDF by the
reliably estimate the tail of the SNM PDF for a large offset caused by global variation. This means that the
memory with relatively few samples. models we have presented remain valid for the case of
combined global and local variation.
10k
model 4. Conclusions
sim
Static noise margin is a critical metric for SRAM bitcell
100 stability. This paper has explored the impact of different
parameters on SNM for SRAM bitcells in sub-threshold.
Model for N−pt M−C The dominant factor affecting sub-threshold circuits in
1 N=100,500,800,1k,50k general and SNM specifically is VT mismatch due to
random doping variation, and the critical region for
0 SNM (V) 0.06 examination is the tail of the SNM PDF. We have shown
that first-order theoretical models for calculating SNM
Figure 10: 50k-pt. M-C simulation for SNM with
are accurate close to the nominal values of VT, but they
4*WL sized transistors. Model based on 1k-pt. M-C cannot accurately account for all of the mismatch cases.
overlays model based on 50k-pt. M-C. We have shown that SNM high and SNM low are
normally distributed with VT mismatch and correlated.
3.5 Impact of Global Process Variation Despite their correlation, we have shown that treating
Thus far we have assumed that device mismatch occurs them as iid leads to a PDF for SNM that gives an
in transistors that start off as typical for the process. In accurate model of the tail cases. This estimate is
addition to the inter-die VT mismatch that we have invaluable for avoiding long Monte-Carlo simulations in
described is an intra-die process variation that sets the the design of large SRAMs for sub-threshold operation.
process corner (e.g. fast NMOS, slow PMOS, etc.). Even
for no mismatch, the process corner impacts the SNM.
Acknowledgements
Figure 11 shows the SNM PDF for a minimum sized 6T This work was funded by Texas Instruments and by the
bitcell from a M-C simulation of global process corner in Defense Advanced Research Projects Agency (DARPA)
which nine process parameters are varied. Here again, through a subcontract with MIT Lincoln Laboratory. Thanks to
the tail of the PDF is the limiting factor. Raúl Blázquez for many helpful discussions.

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