Hi3798M V100

Hi3798M V100 Brief Data Sheet

Key Specifications
CPU z Dolby Digital/DTS transparent transmission
z Quad-core ARM Cortex A7, up to 1.5 GHz dominant z AAC-LC and HE AAC V1/V2 decoding
frequency z APE, FLAC, Ogg, AMR-NB, and AMR-WB decoding
z Integrated multimedia acceleration engine NEON z G.711 (u/a) audio decoding
z Hardware Java acceleration z Downmixing, resampling, highly dynamic volume control
z Integrated hardware floating-point coprocessor z High-quality Karaoke, supporting echo cancellation and
G.711v (u/a), AMR-NB, AMR-WB, and AAC-LC audio
3D GPU
encoding
z Quad-core Mali450
Image and Display Processing (Imprex
z OpenGL ES 2.0/1.1/1.0 OpenVG 1.1, EGL
Processing Engine)
Memory Interfaces
z Hardware overlaying of multi-channel graphics and video
z DDR3/DDR3L interface inputs
− Maximum 2 GB capacity
z Three OSD layers
− 32-bit memory
z Four video layers
− Maximum 800 MHz frequency (DDR-1600)
z Screen mirroring
z NAND flash interface z Ultra-low-delay video processing
− SLC/MLC flash memory
z Letter box and PanScan
− 8-bit data width
z Full format 3D video processing and display
− Maximum 64 GB capacity
z Multi-tap vertical and horizontal scaling of videos and
− Maximum 64-bit ECC
graphics; free scaling
z eMMC/tSD/fSD flash memory z Enhanced full-hardware TDE
HiVXE Video Decoding z Full-hardware anti-aliasing and anti-flicker
z H.265 Main [email protected] High-tie z CSC with configurable coefficients
z H.264 BP/MP/[email protected] z Image enhancement and denoising
z Full-HD 3D videos (MVC), blu-ray navigation z Deinterlacing
z AVS baseline profile @L6.0, AVS-P16 (AVS+) z Sharpening
z MPEG1 z Chrominance, luminance, contrast, and saturation
z MPEG2 SP@ML, MP@HL adjustment
z MPEG4 SP@L0−3, ASP@L0−5, GMC z Video Db/Dr processing
z MPEG4 short header format (H.263 baseline) Audio/Video Interfaces
z VC-1 SP@ML, MP@HL, AP@L0−3 z PAL, NTSC, and SECAM standard output, and forcible
z VP6/8 standard conversion
z 4K x 2K@30 fps decoding z Aspect ratio of 4:3 or 16:9 and forcible aspect ratio
z Low delay decoding conversion
z Simultaneous 4-channel HD decoding z 4K x 2K/1080p50/1080p30/1080p24/1080i60/1080i50
Image Decoding /720p/576p/576i/480p/480i output
z Full HD JPEG hardware decoding, maximum 64 z One SD output and one HD output from the same source or
megapixels different sources
z MJPEG decoding, maximum 1080p@40 fps z One HDMI 1.4a TX with HDCP 1.4 output
z PNG hardware decoding, maximum 64 megapixels z Analog video interfaces
Video and Image Encoding − One CVBS interface
− One embedded VDAC
z H.264 BP/MP/[email protected] video encoding, 1080p@30 fps
z Audio interfaces
z JPEG hardware encoding, maximum 1080p@30 fps
− Audio-left and audio-right channels
z VBR or CBR mode for video encoding
− SPDIF interface
z Low delay encoding
− Embedded ADAC output
Audio Encoding and Decoding 2
− One I S/PCM digital audio input/output（Optional）
z MPEG L1/L2 − HDMI audio output
z Dolby Digital/Dolby Digital Plus Decoder-Converter
Peripheral Interfaces
z Dolby True HD decoding
z One USB 3.0 host port（Optional）
z DTS and DTS HD core decoding

Copyright © HiSilicon Technologies Co., Ltd. 2015. All rights reserved.

New R&D Center, Wuhe Road, Bantian, Longgang District, Shenzhen 518129 P. R. China www.hisilicon.com
Issue: 03 1 Date: 2016-10-16
 Hi3798M V100
Hi3798M V100 Brief Data Sheet
z Three USB 2.0 host ports Other Specifications
z Boot and debugging over the USB port z Embedded secure boot module, supporting
z One SDIO 3.0 interface anti-ROM-flashing
z One 10 Mbit/s or 100 Mbit/s adaptive Ethernet port with z Secure video path
the integrated FE PHY z 2-layer PCB design
z One IR receiver with one input interface z Various boot modes
z Multiple I2C interfaces z USB bootstrap when the flash memory is empty
z Multiple UART interfaces（Optional） z Integrated standby processor, supporting various standby
z Multiple GPIO interfaces modes and less than 30 mW standby power consumption
z Integrated POR module z Low-power design such as AVS and DVFS

Functional Block Diagram

Hi3798M V100 is a cost-effective chip solution targeted at the over-the-top (OTT) STB market. It brings the best user experience in
the industry in terms of stream compatibility, smoothness and picture quality of live video playback, and STB performance. With an
integrated high-performance quad-core processor and embedded NEON, Hi3798M V100 meets differentiated service requirements. It
also supports Dolby and DTS audio processing. To meet the growing requirements on multimedia playback, video communication,
and multi-screen transcoding, Hi3798M V100 supports HD video decoding in various formats (including H.265, H.264, AVS+, MVC,
MPEG2, MPEG4, VC-1, VP6, and VP8) and high-performance H.264 encoding. Hi3798M V100 provides a smooth man-machine
interface and rich gaming experience with a high-performance multi-core 2D/3D acceleration engine. It also enables flexible
connection schemes with one Ethernet port, three USB 2.0 ports, one USB 3.0 port(Optional), and more peripheral interfaces.

z DTS, mentioned in this document, is a registered trademark of DTS Inc. and its subsidiaries. Any
parties intending to use the trademark must obtain the permission from DTS Inc. or its subsidiaries.
z Dolby, mentioned in this document, is a registered trademark of Dolby Laboratories, Inc. Any
parties intending to use the trademark must obtain the permission from Dolby Laboratories, Inc.

Copyright © HiSilicon Technologies Co., Ltd. 2015. All rights reserved.

New R&D Center, Wuhe Road, Bantian, Longgang District, Shenzhen 518129 P. R. China www.hisilicon.com
Issue: 03 2 Date: 2016-10-16
 Hi3798M V100
Hi3798M V100 Brief Data Sheet
Acronyms and Abbreviations
ADAC audio digital-to-analog converter
ADB Android debug bridge
AVS adaptive voltage scaling
BGA ball grid array
CBR constant bit rate
CSC color space conversion
CVBS composite video broadcast signal
DSP digital signal processor
DVFS dynamic voltage frequency scaling
ECC error correcting code
eMMC embedded multimedia card
FE fast Ethernet
GMC global motion compensation
GPIO general-purpose input/output
GPU graphics processing unit
HDMI high-definition multimedia interface
HEVC high efficiency video coding
I2C inter-integrated circuit
IR infrared
I2S inter-IC sound
JPEG Joint Photographic Experts Group
MJPEG Motion Joint Photographic Experts Group
MLC multi-level cell
MPEG Moving Picture Experts Group
MVC multiview video coding
NTSC National Television System Committee
OTT over-the-top
PCB printed circuit board
PCM pulse-code modulation
POR power-on reset
ROI region of interest
SDIO secure digital input/output
SLC single-level cell
SPDIF Sony/Philips digital interface
SPI serial peripheral interface
SSVP super secure video path
STB set-top box
TDE two-dimensional engine
UART universal asynchronous receiver transmitter
VBI vertical blanking interval
VBR variable bit rate
VDAC video digital-to-analog converter

Copyright © HiSilicon Technologies Co., Ltd. 2015. All rights reserved.

New R&D Center, Wuhe Road, Bantian, Longgang District, Shenzhen 518129 P. R. China www.hisilicon.com
Issue: 03 3 Date: 2016-10-16