Modeling and Control of Grid-following

Single-Phase Voltage-Sourced Converter

Huazhao Ding, Zhengyu Wang, Lingling Fan, Zhixin Miao
Deparment of Electrical Engineering
University of South Florida
Tampa, Florida 33620
{huazhao, zhengyuwang, linglingfan, zmiao}@usf.edu

Abstract—This paper presents modeling and control of a grid- As a grid-following inverter-based system, the connection
following single-phase voltage-sourced converter (VSC). The elec- and the grid side operation condition are significantly im-
tromagnetic transient (EMT) simulation is carried out via MAT- portant to the inverter control and performance. Thus, three
LAB/Simulink with SimPowerSystems Toolbox. Detailed IGBT
switches are included in the DC/AC inverter model. Second-order major dynamic events are designed and demonstrated in the
2020 52nd North American Power Symposium (NAPS) | 978-1-7281-8192-9/21/$31.00 ©2021 IEEE | DOI: 10.1109/NAPS50074.2021.9449795

generalized integrator-based Phase-Locked-Loop (SOGI-PLL) is case study based on the same simulation testbed. The first
implemented for synchronization and dq-component extraction. event is the weak grid connection, which is caused by an
Real and reactive power control is implemented for converter increasing transmission line reactance. The second and third
operation. Multiple grid dynamic events are designed in the events emulate system dynamic responses to the changes of
simulation testbed for analysis and demonstration.
grid side voltage magnitude and frequency. For benchmarking
Index Terms—Single-phase VSC, Grid-following, SOGI, PLL. purpose, power flow-based steady state analysis and system
initialization is performed via a formulated optimization prob-
lem with YALMIP [12]. The limits of the system to handle
I. I NTRODUCTION weak grid and grid voltage changes are solved in advance and
verified in the EMT simulation.

T HE penetration of inverter-based renewable energy re-

sources significantly increases recently and control of
inverter becomes a critical topic in the renewable energy
The rest of the paper is organized as follows. Section II
introduces the detailed implementation of the gird-following
single-phase VSC testbed, including circuit, SOGI-PLL, con-
research field. Three-phase VSCs and control have been intro- trol logic, and steady-state analysis. The case studies of the
duced by many textbooks [1]–[3] and many researches have PLL performance, ripple frequency analysis, and dynamic
been developed [4], [5]. events are presented in Section III. Finally, Section IV gives
Compared to the three-phase VSC study, researches on the conclusion.
single-phase VSC have been less conducted. The major differ-
ence in control lies in the synchronizaton unit. In three-phase
system, the Park’s transformation or abc/dq transformation II. S INGLE - PHASE G RID - FOLLOWING VSC T ESTBED
with the phase angle generated by reference or estimated by A. Circuit Topology
PLL in grid forming and grid-following control can easily
extract direct-quadrature components from three-phase mea-
surement for control purposes. In single-phase system, abc/dq
is not possible since the system has only phase a.
The key of controlling single-phase VSC is to extract  

    
the direct-quadrature components. For a constant frequency 


"

system, the variable time delay method can be simply applied  

to obtained a component with 90 degree shift, which is similar 

  
to the Clark’s transformation [3]. However, such an ideal
system cannot handle the grid frequency change. The adaptive 


methods to achieve decomposition usually required feedback

   
loops [6]–[8]. Additionally, single-phase PLLs are also very    
different in structure [9]–[11].   




In this paper, an electromagnetic transient (EMT) simulation

testbed of a grid-following single-phase converter has been    

built and presented. The second-order generalized integrator
(SOGI)-based transformation and PLL are implemented for 

 

the measurement processing and inverter synchronization [3],

[11]. Fig. 1: Single line topology of the circuit.

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 The study system is shown in Fig. 1. A single-phase full- transformation is done through the following computation
bridge VSC is connected to the grid voltage through an RL process.
filter and transmission line. The point of common coupling     
(PCC) bus is connected after the RL filter for single-phase vd cos(ωt) sin(ωt) vα
= (1)
voltage and current measurements. vq − sin(ωt) cos(ωt) vβ
PCC bus measurements are collected and sent to the con-
The loop filter is a PI controller with input of vq extracted
troller. PLL is applied to generate phase angle information
from Park Transformation. The DC value will be pushed to
from voltage measurement for synchronization and dq-frame
zero while PLL is tracking the angle. As a result, eventually,
decomposition purposes. For the single-phase study system,
vd is equal to the voltage amplitude and vq is equal to 0. At
an SOGI-PLL is employed. The real and reactive power are
steady-state, the estimated phase angle is locked up with the
computed from voltage and current dq-components and fed
input and outputted as ωt, which is applied to extract current
into the control algorithm. In the end, the reference signal is
dq-components and the reference signal generation for the
fed into a 2-level bipolar PWM generator for inverter switching
PWM generator with Inverse Park Transformation. The gain
control. Table. I shows the system parameters.
applied in the implemented SOGI-PLL is presented in Table.
TABLE I: Parameters of the main system II.
Item Value Item Value TABLE II: Parameters of SOGI-PLL
Sbase 4000 VA Vn 190.52 V
R 1.1E-5 pu X 1.142 pu Item Value Item Value
Rg 0.05 pu Xg 0.25 pu Kp,PLL 60 ωc 376.9
√ rad/s
Ki,PLL 1400 k 2

B. Phase-Locked-Loop
The SOGI-PLL [3] is implemented in the testbed. The
C. Control Algorithm
block diagram of the structure is shown in Fig. 2. Compared
to conventional PLL, the SOGI-PLL has a quadrature signal In the presented testbed, the control algorithm is shown in
generator (QSG) in front of the Park Transformation, which Fig. 4. The inner control loop is current control with decou-
requires the estimated frequency to be returned for αβ- pling feed-forwards. And the outer control loop is real/reactive
components extraction. power control. Controller reference frame is based on the PCC
bus phase angle estimated by the PLL.
Park
Transform Loop Filter




/  
  


, 1


 






SOGI-QSG / , + +
+






 







Fig. 2: Block diagram of Second-order Generalized Integrator-based Phase 
 
  



Locked Loop (SOGI-PLL). 


 



 

 

Fig. 3 presents the structure of SOGI-QSG in detail. va
Fig. 4: Block diagram of the inverter control. Inner loop is current control.
is the single-phase AC voltage measurement from PCC bus Output loop is real/reactive (P/Q) power control.
and sent into the SOGI-PLL as input. The estimated αβ-
components, vα and vβ , are the outputs of the QSG. Note For the dynamic real/reactive (P/Q) power at PCC bus in
the vα and vβ are 90 degrees apart, and vα is the same as per unit system, the expression can be carried out as follows.
input signal at steady state.
P = vd id + v q iq (2)
Q = vq i d − v d i q (3)


  

  
Due to the PCC reference frame, vd = Vpcc and vq = 0,
  then the expressions can be rewritten as:
 

P = Vpcc id (4)
Q = −Vpcc iq (5)
Fig. 3: Structure of SOGI for quadrature signal generation.
From above expression, it shows that the real power control
With extracted αβ-components, the Park Transformation required negative feedback control loop and reactive power
is applied to gather dq-frame components, vd and vq . The control needs positive feedback.

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 For inner control, the algorithm is concluded from circuit Vg = 1;
analysis. On dq-reference frame, the dynamic equation can be i = (vpcc-Vg)/(Rg+1i*Xg);
written as follows. S = vpcc*conj(i);
did P = real(S); Q = imag(S);
L = −Rid + ed − Vpcc + Lωiq (6)
dt    To solve the objective within constraints, the values of Vpcc
ud
and θpcc are obtained. Furthermore, by changing the system
diq
L = −Riq + eq − Lωid , (7) parameters, such as grid voltage magnitude and transmission
dt    line impedance, the stability of the system can be examined
uq
under weak grid and voltage dip condition [4].
where ed and eq are the VSC terminal voltage’s dq-
components. The equations above can explain the structure of III. C ASE S TUDY
the current control, where the current PI controllers’ outputs
are ud and uq , respectively. In order to generate ed and eq In the case study, the SOGI-PLL performance is first
order, cross-coupling term −ωLiq and feedforward term Vpcc examined to track a single-phase AC voltage signal under
are added to ud to generate ed . Similarly, cross-coupling term magnitude increase, frequency dip, and phase angle jump.
ωLid is added to uq to generate eq . Then, the instantaneous power with FFT analysis is presented.
In the end, the terminal voltage dq-components are sent Next, the simulation result will show PQ regulation capability
into the Inverse Park Transformation to generate the control of the control. Finally, the testbed is simulated under weak
reference signal with the estimated phase angle, ωt. Table. III grid, voltage dip, and frequency dip conditions with steady
presents all the gains for PI controllers in the testbed. state limit approaching via YALMIP.

TABLE III: Parameters of the controller

A. SOGI-PLL Demonstration
Item Value Item Value The SOGI-PLL in Fig. 2 is implemented in MAT-
Kp,P 0.4 Ki,P 45 LAB/Simulink individual to test its performance. The input
Kp,Q 0.4 Ki,Q 40
Kp,id 0.4758 Ki,id 3.2655
signal is a single-phase AC voltage signal with no noise. The
Kp,iq 4 Ki,iq 15 following events are designed for presenting [10].
• Event 1: Input magnitude increase
• Event 2: Input frequency drop
• Event 3: Input phase angle jump
D. Steady State Analysis • Event 4: Combined dynamic event
To study the operation condition of the grid-following VSC, Figure. 5 presents dynamic response in Event 1. At 1
the steady state analysis is performed based on power flow via second, the input voltage has a magnitude step change from 1
constrained optimization formulated within YALMIP. Solver to 1.5 per unit. Upper plot shows the input AC voltage signal,
used is IPOPT. the lower plot shows the estimated voltage magnitude from
With PQ control implemented, the PCC bus power follows
the reference at steady state. The equality constraints can be SOGI-PLL can track the reference change.
formulated as follows.
Constraints= [P_ref == P; Q_ref == Q];

Between PCC bus and grid voltage source, the only un-
known variables are the Vpcc and θpcc , and they are introduced
as symbolic decision variables (sdpvars). To grab real and
reactive power, the transmission line current phasor, I¯g is
carried out as follows.
V̄pcc − V̄g
I¯g = (8)
Rg + jXg
The complex power at PCC bus can be obtained from the
following expression.
Spcc = V̄pcc I¯g∗ (9)
In the end, take the real and imaginary parts of the complex
power into the constraints for objective solving. The formu- Fig. 5: Magnitude change of the SOGI-PLL.
lated problem is shown below.
Vpcc = sdpvar(1); In Event 2, the input voltage signal experiences a frequency
theta = sdpvar(1); dip from 60 Hz to 50 Hz at 1 second. Figure. 6 shows the input
assign(Vpcc,1); signal and estimated frequency.
assign(theta,0);
In Figure. 7, the estimated phase angle is compared to the
vpcc = Vpcc*exp(1i*theta); reference signal while the input signal has a phase angle jump

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 1.5
Input signal
phase
phase
1

0.5

Voltage (pu)
0

-0.5

-1

-1.5
0.95 1 1.05 1.1 1.15
Time (seconds)

Fig. 8: Multiple changes of the SOGI-PLL.

Fig. 6: Frequency change of the SOGI-PLL.

The instantaneous power (p(t)) can be derived as shown

below.
from 0 degree to 30 degree at 1 second. The upper plot shows
the rotating phase angle (in rad) tracking and the lower plots p(t) = v(t)i(t) (12)
shows the static phase angle tracking (in degree).
= Vrms Irms cos(φ) + Vrms Irms cos(2ωt + φ) (13)
     
DC Component Double frequency component

Fig. 9 shows the collected instantaneous power measure-

ment from the simulation testbed. The fundamental frequency
of the system is 60 Hz. The ripple frequency is 120 Hz.

Fig. 7: Phase change of the SOGI-PLL (θ= wt).

For Event 4, multiple changes are applied on the input signal

for testing SOGI-PLL’s performance. At 1 second, the input
signal gets a magnitude drop from 1 to 0.8 pu, a frequency
Fig. 9: Instantaneous power of the PCC bus.
increase from 60 Hz to 70 Hz, and a phase jump from 0 to
15 degree. Figure. 8 shows the comparison between input and
To verify, the data is analyzed with Fast Fourier Transform.
estimated vα , as well as, vβ , which is 90 degrees behind.
Fig. 10 clearly presents there is a DC components at a
magnitude of 0.5 and a 120 Hz dominated component at a
magnitude of 0.58.
B. Double frequency ripple of instantaneous power
C. Power regulation capability
In time domain, the instantaneous power in the single-phase
AC system will include a DC component and an AC ripple. With PQ control algorithm implemented, the VSC is op-
The ripple frequency is double of the fundamental frequency. erated in grid-following mode. To examine the PQ control
Assume the instantaneous voltage (v(t)) and current (i(t)) are function, step changes are applied on reference signals, Pref
expressed as follows. and Qref . Initially, the real power is 0.5 pu and the reactive
power is 0.3 pu. At 1.5 second, Pref increases from 0.5 to 0.8
√ pu. And at 2 second, Qref decreases from 0.3 to 0.1 pu. Fig.
v(t) = 2Vrms cos(ωt) (10)
√ 11. shows the power regulation results. The red curves are the
i(t) = 2Irms cos(ωt + φ) (11) reference signals and blue curves are the measurements.

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 0.7 0.6
X: 120 Xg= 1.7 pu
Y: 0.5849 X = 1.8 pu
0.6 g
X: 0 0.55 Xg= 1.9 pu
Y: 0.5002
0.5 120 Hz ripple
component 0.5
DC component
0.4
Magnitude

0.45

P
0.3

0.4
0.2

0.1 0.35

0 0.3
0 20 40 60 80 100 120 140 160 6.9 6.95 7 7.05 7.1 7.15 7.2 7.25 7.3 7.35 7.4
Frequency Time (seconds)

Fig. 10: FFT analysis of instantaneous power. Fig. 12: Measurements of PCC bus real power under different line reactance.

1.5
E. Grid voltage dip
1

In a large power system, the voltage dip could appear

P

0.5
when there is a fault somewhere not too far away from the
0 measurement bus. For the relatively small system in this paper,
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
the single-phase grid voltage dip is designed to emulate the
1 fault condition.
Same as previous case study, the voltage dip limit is
0.5
obtained from YALMIP solving. According to the approaching
Q

0
results, it finds that the minimum grid voltage magnitude to
maintain the stability is 0.32 pu. From the simulation testbed,
-0.5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
the observed marginal grid voltage magnitude is 0.37 pu,
Time (seconds) which is relatively accurate.
Fig. 11: Real power, reactive power and its step. The dynamic events are designed as follows.
• Event 1: voltage dip from 0.5 pu to 0.39 pu
• Event 2: voltage dip from 0.5 pu to 0.37 pu
D. Weak grid condition • Event 3: voltage dip from 0.5 pu to 0.35 pu
As the transmission line becomes longer, the line reactance The time-domain measurement of grid voltage and PCC bus
increases and the grid becomes weaker. In the case study, the voltage after a filter are shown in Fig. 13, and the real power
line impedance is gradually increased until the system col- measurement to indicate the system stability is shown in Fig.
lapses. Before moving on to the simulation, steady-state power 14.
flow analysis is performed. From the YALMIP solving, it is
found that the marginal reactance causes unstable condition is 500
140
1.85 pu. The simulation testbed has dynamics included. Due 400 120 Voltage dip to 0.39 pu
Grid voltage (V)

100 Voltage dip to 0.37 pu

300 Voltage dip to 0.35 pu
to dynamic stability limits, the real system limit should be 200
80
60
lower than 1.85 pu. 100
3 3.01 3.02 3.03 3.04 3.05

0
The designed dynamic events are shown as follows. The -100
measurement of the PCC bus real power is shown in the Fig. 3 3.01 3.02 3.03 3.04 3.05 3.06 3.07 3.08 3.09 3.1

12.
PCC voltage after a filter (V)

500
400 150 Voltage dip to 0.39 pu
• Event 1: Line impedance increases from 1.6 to 1.7 pu 300
Voltage sip to 0.37 pu
Voltage dip to 0.35 pu
• Event 1: Line impedance increases from 1.6 to 1.8 pu 200 100
3 3.01 3.02 3.03 3.04 3.05
100
• Event 1: Line impedance increases from 1.6 to 1.9 pu
0
-100
From Fig. 12, the real power measurement shows that
3 3.01 3.02 3.03 3.04 3.05 3.06 3.07 3.08 3.09 3.1
system is stable in Event 1; the system is still stable but Time (seconds)

weakened in Event 2 due to longer settling time; the system Fig. 13: Grid voltage and PCC bus voltage after a filter.
suddenly lost stability in Event 3. The true marginal reactance
for weak grid connection in the testbed is examined to be 1.81
pu, which is less than the steady-state limit considering only From Fig. 14, it can tell when the grid voltage magnitude
algebraic relations. dips across the marginal voltage can cause the instability issue.

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 0.6
presented. The VSC type is detailed IGBT switch-based. The
Voltage dip to 0.39 pu
Voltage dip to 0.37 pu
control algorithm implementation including SOGI-based PLL
0.55 Voltage dip to 0.35 pu and αβ-components extraction are discussed in detail. Several
case studies on SOGI-PLL, instantaneous power analysis,
0.5
controller capability, and system operation limits are demon-
0.45 strated.
P

0.4
R EFERENCES
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Frequency dip to 46 Hz
60 Frequency dip to 41 Hz
Frequency dip to 40 Hz
Frequency

50

40

30

20
0 0.5 1 1.5 2 2.5

3
Frequency dip to 46 Hz
2 Frequency dip to 41 Hz
Frequency dip to 40 Hz
1
P

-1

-2
0 0.5 1 1.5 2 2.5
Time (seconds)

Fig. 15: Frequency dip.

IV. C ONCLUSION
In this paper, a Simulink/SimPowerSystem EMT testbed
of single-phase full-bridge VSC in grid-following mode is

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