BEHAVIORAL MODEL OF PIPELINE ADC BY USING SIMULINK@

Erkan Bilhan, Pedro C. Estrada -Gutierrez, Ari Y. Valero-Lopez, Franco Maloberti

Texas A&M University

Department of Electrical Engineering
College Station, Texas 77840 U.S.A.
bilhan @ee.tamu.edu

ABSTRACT

The presented work concentrates on behavioral

modeling of pipeline ADCs. For this purpose the
I -.-'-
+ 1
%, N-bits
parameters that affect the operation of basic pipeline
ADC blocks are investigated. The non-ideal parameters
Digital Correction Circuit-.,
...
+ADC
Output
of these blocks are modeled by using MATLAE4@ and
SIMULINK?

I. INTRODUCTION
d; (1.5 bits)
Early stages of analog design circuits foresee
the validation of the selected architecture and the Yes,
definition of the basic blocks' specifications. These steps
are performed with a behavioral analysis of systems: an
investigation at the transistor level is often premature.
Even if possible, it is quite time consuming. Behavioral
description can be achieved by the use of different high-
level languages [ 13. This paper employs the MATLAB@
and SIMULINK@environment. However, other solutions
(like HDL-A or Labview) can be used as well.
Specifically, we study the behavioral model and derive
performances of a pipeline ADC. It consists of cascaded Figure 1. Pipeline ADC block diagram and stage transfer
identical stages. Each stage processes the input signal curve
and produces a digital word plus a residual voltage for
the next stage. The resolution of a single stage may vary This work accounts for all these non-idealities and
according to the design specifications. In our case we permits to estimate the accuracy and the speed
used IS-biVstage (Figure 1) that is normally used performances of the conversion before the design.
together with the digital correction technique [2]. The
transfer function of a stage is as below: 11. SAMPLE/HOLDAMPLIFIER
2Vin

2V1n
+ Vref
+ Vref
; d =
;d=01
; d = 10
00

I
A sample and hold amplifier precedes the pipeline chain.
A Sample and Hold (SBrH) block is a critical
part of an ADC. Its function is to sample and then retain
the input signal long enough for the A/D converter to
complete a conversion without significant error.

Each of the pipe stages comprises four main blocks: a

sub-ADC, sub-DAC, residue amplifier and subtractor.
Generally an MDAC realizes the last three. The accuracy
of the converter critically depends on the non-idealities
of the actual components used. Such non-idealities come
from the limited matching of components, the finite gain 4 c1k
and gain bandwidth of amplifiers. Figure 2. Basic Sample and Hold circuit

0-7803-6742-1/01/$10.0002001 IEEE 147

 We have modeled a S&H block considering the different regions: linear and overdrive. The model is able
non-idealities of clock jitter and acquisition timelslew to determine the region of operation and to apply the
rate. A basic S&H circuit is shown in Figure 2. The proper behavioral model. The hysteresis is included to
clock jitter is modeled during the sampling instance, model the metastability error present in the comparator
which is when the clock is asserted. The acquisition time due to signals whose magnitude is very close to the
is defined as the time the S&H takes to charge or comparator reference. Fixed offset voltage and random
discharge from one sampling point to another within half offset voltage are added to the input. Fixed offset voltage
a clock period. When the clock signal goes high, the accounts the intrinsic offset of the comparator and causes
S&H samples the input and the data is stored in the Chid a shift in the threshold voltage of the amplifier. The
capacitor. The opamp with the unity gain functions as a random offset accounts for the random variations in the
buffer. After the clock switches to low, the output holds reference voltage.
onto the voltage stored in the Chid capacitor. The Figure 3 shows the SIMULINK@model of the
acquisition voltage depends on the slew rate of the comparator. The signal can follow two different paths
opamp at the output. When the slew rate is limited or depending on the operation region of the comparator. In
there is a large output capacitance, it may cause the linear mode the signal is amplified, limiteaand latched,
output to fall short from the desired input level. This will whereas in the overdrive mode the signal goes from the
cause signal degradation and as such affect the initial voltage to the final voltage in an exponential
performance of the whole system. fashion. This exponential behavior introduces the speed
Clock jitter is the difference of time from its limitation of the comparator into the model.
ideal rising clock edge. This difference occurs randomly
before or after its ideal rising edge. The specification of
the model is limited to kTJ2 (T,=sampling period). From
the description above, the model will have to be able to
interpolate between two points. The two points may lie
between a past and present point or a present and future
point. The actual jitter in the system is usually within an
acceptable range of error. With this assumption and
considering that the input signal frequency is reasonably
slow, it is best to use linear interpolation because of its
simplicity. The acquisition is the time the circuit takes Figure 3. Comparator macromodel
given a certain time constant to achieve the sampling
point. The final value of current sampling may not be IV. MDAC MODEL
equal to the input value if the time constant is large. The
S&H model includes a memory block to remember the The performance of a pipeline ADC critically
last value as the initial point to calculate the final point depends on the performance of the MDAC amplifier.
due to acquisition time. used to generate the residue voltage for the next stage.
In this model it was assumed that charging or Figure 4 shows the typical switched capacitor MDAC
discharging of the capacitor occurs during first half of configuration used in a 1.5 bit per stage architecture [3].
clock period. Thus the time in this case is T,/2. The Phi,
acquisition time equation is modeled as a simple RC
circuit. The study of the effect of non-linearities
associated to the on-resistance of the switch is also
possible but it's not done here to limit the simulation
time.

111. COMPARATOR

The comparator is one of the most widely used

blocks in analog to digital converters. It is the block that Figure 4.MDAC Configuration
ultimately links the analog signal to a digital During the first phase (Phi,) capacitors C1 and C2 are
representation. One of the most popular comparator charged to the input voltage while during the second
implementations for high-speed has one or two stages of phase (Phiz) C2 is connected in feedback and C, is
preamplification followed by a latch. The comparator connected to a proper reference voltage determined by
model is comprised of two stages, a preamplifier and a the digital output of the sub-ADC. Successive cells
latch (with hysteresis). The amplifier can operate in two operate with complementary phases so that while the

148
 L

equal or higher than 205 times of their overdrive voltage

(Vd). So the slew-rate is effective only for large input
voltages. During the slewing condition the output voltage
changes proportionally to the maximum current that can
be driven from amplifier. For other cases the amplifiers
operate in linear condition (LOP), in which the speed of
the charge transfer is determined by gain bandwidth of
amplifier. The circuit in Figure 5 is modeled as in Figure
6 by using a single pole approximation for the amplifiers,
to investigate the discussed limitation on the converter’s
performance. The current sources model either the
Figure 5. MDAC Configuration for sequential two stages slewing condition (I=I-) or the normal operation
(I=g,V,,). Equation (2) gives the system equations
first stage generates the residue voltage the next stage describing the circuit’s behavior for all operating
samples it (see Figure 5). conditions of amplifier. This equation was solved for the
The performance of a stage depends on how four different situations summarized in Table 1
precisely they can generate the residue for the next stage. depending on the operating condition of amp-I and amp-
In other words the settling of the amplifier’s output 2. A behavioral model is developed that uses the
voltage to the right value in a half clock cycle determines solutions of the system equations. The simulation results
the precision of the next stage. The ideal transfer are discussed in the next section.
function of amplifier is given in (1). There are four basic
error sources: Capacitor matching and open loop gain,
gain bandwidth, and the slew-rate of the amplifier. If the
capacitor mismatch is accounted the ideal residue
function has to be modified as follows:

More complex is the modeling of the finite gain, gain- Figure 6. Circuit model used to analyze the MDAC given
bandwidth and slew-rate of the amplifier. Finite open in Fig. 5
loop gain modifies the gain of the feedback system and
this will introduce an error to the residue value. The Table 1: Operating conditions for amplifier and solution
gain-bandwidth and slew-rate determines the speed of
the operation. If the time for residue generation is I I amp-1 I amp-2 I (3) is solved for I
smaller than the settling time of the amplifier the residue
does not settle to the proper voltage and it introduces an
error to the voltage sampled by the next stage.
The amplifiers, shown in Figure 5, operate in
slewing condition (SLW) if the voltage at their input is

149
 V. SIMULATIONRESULTS

The discussed model above was used to

simulate a 1.5biVstage 10-bits pipeline ADC at 100 MHz =it 1
, , , , , ]

with digital correction. 0 005 oi 046 02 026

Several simulations were performed considering

variation of a non-ideal
\ parameter
; while the! rest of the i g05

blocks were considered ideal. The rest of the non-

idealities in the same block were only considered 0
0 005 01 015 02 025
constant. This analysis shows the effect of every non- F l x d Onad (V)

ideality isolated from the rest of the parameters. Figure 7. INL and DNL plots for offset in comparator.
First, results for the Sample and Hold are shown
in Tables 2 and 3. Table 2 shows the effect of reducing
the time constant or acquisition time of the S&H. Table 3 8, . I , I I . , , , ,
considers the effect of jitter noise. The values in the jitter
column represent in percentage of the clock frequency,
the maximum jitter noise possible for that simulation.
We can see that the system is very sensitive starting from
certain value.

ill_i
Table 2. Maximum INL and DNL for different values of
acquisition time (Tau)
0 50 02 04 06 08 1 12 14 16 18 2
Tau [s] Max INL [LSB] Max DNL [LSB]
le-5 0 0
Time EoIulall*
5e-5 0.5574 0.1893 I
1e-4 0.9734 0.1986 Figure 8. INL and DNL plots for speed in comparator.
5e-4 1.1738 1.1957
le-3 2.0879 2.3934
-

il
laa
em-
Table 3. Maximum INL and DNL vs. Jitter
2 a-
Jitter [Yo] Max INL [LSB] Max DNL [LSB] m-
10 0.1237 0.0562 09 ow 094 096 ow 1 102

25 0.974 1 0.7236
35 1.7428 1.4295
45 2.3782 1.9647
49 3.1284 2.3863
It
Simulations performed under the specified 09 092 094 0% 0% 1 102
conditions show that the offset of the comparators should tiptensir (V)

be below 250mV, the bandwidth of the comparator Figure 9. INL and DNL plots for hysteresis in
larger than .15OMHz and the hysteresis smaller than lV, comparator.
see figures 7, 8 and 9. From the previous values we can
see that the digital correction at the output of the ADC The capacitor values are chosen as CI=C2=C3=C4=lpF,
helps to relax the specifications of the building blocks. 2C,,=2CpZ =Cp3 =O.lpF for MDAC simulations. The
The offset and hysteresis show values from which the amplifier parameters such as transconductance ( G d
performance of the comparator degrades rapidly, but output resistance (1/G) and the maximum current (Imx)
these values are large enough to provide a very relaxed are calculated according to the assigned values of AV,
specification. GBW and SR.The parameters used for simulations and
the performance results in terms of INL are summarized
in Table 4.

150
Table 4: Simulation results for the MDAC IO-BIT ADC OUTPUT

3.8779
25.1817
1.4529
60.3555
5 80 700 100 1.8653
6 80 600 75 49.7195
7 80 600 250 0.61-39

The input-output plot of 10-bit ADC for the lst

parameter set is given in Figure 10. Some sparkling "
codes from Figure 10, and an INL error of 4LSBs from -1 a8 46 44 42 0 02 04 06 08 1
INUT
Figure 11 can be observed. The'chosen parameter set can
not meet the linearity specification, which is an INL
error within OSLSBs. For an optimal solution the values Figure 10. ADC Output plot for the first parameter set in
for the parameters AV, GBW, SR should be changed. Table4.
Table 4 presents some possible combinations (data set
from 2 to 7) and the result of simulation. As seen from
these results, increasing one parameter while keeping the
others constant does not improve the performance 4

further. The contribution of the other parameters to INL 2

is more significant than the parameter that is increased. It INL
can be deducted from simulation results that the 0
limitation factors on performance for the first parameter
set are the GBW and SR of the amplifier rather than the -2
AV.For an optimal solution one must seek an increase of
these two, GBW, SR parameters.

REFERENCES

[ l ] F. Maloberti, P. Estrada, A. Valero, P. Malcovati,

"Behavioral Modeling and Simulation of Data
Converters," IMEKO 2000, September 2000, Viena,
Austria
[2] Lewis, S.H.; Gray, P.R., "A pipeline SMsample/s 9
bit analog-to-digital converter," IEEE JSSC, vol. SC-22,
pp.954-61, Dec 1987
[3] Gunay, Z.S.; Soenen, E.G.; Embabi, S.; Sanchez-
Sinencio, E., "A 1.8 V pseudo-differential switched-
capacitor amplifier," Custom Integrated Circuits Figure 11. INL and DNL plots for the first parameter set
Conference, 1998. Proceedings of the IEEE, pp. 373 - in Table 4
376, 1998

151