COA Lab Manual

Lab 1): Verification of Logic Gates

Logic Gates:
 Logic gates are the basic building blocks of any digital system.
 It is an electronic circuit having one or more than one input and only
one output.
 The relationship between the input and the output is based on a
certain logic. ss
 Based on this, logic gates are named as
 AND gate
 OR gate
 NOT gate
 NAND gate
 NOR gate
 XOR gate
 XNOR gate
AND Gate: If both the values are TRUE then output is True or else False.

OR Gate: If one of the value is TRUE then output is True or else False

NOT Gate: If input is True then output is False and Vice versa.

Dept. of CSE || RGUKT SRIKAKULAM Page 1

 COA Lab Manual

NAND Gate: Exact Opposite to AND Gate

NOR Gate: Exact opposite to OR Gate.

Dept. of CSE || RGUKT SRIKAKULAM Page 2

 COA Lab Manual

XOR Gate: One value should be False then Output is True else False

XNOR Gate: Both values should be same either False or True then output is
True else False

Lab 2: Verification of Full adder and Full Subtractor

FULL ADDER: Full Adder is the adder which adds three inputs and produces two
outputs. The first two inputs are A and B and the third input is an input carry as C-IN.
The output carry is designated as C-OUT and the normal output is designated as S
which is SUM.
A full adder logic is designed in such a manner that can take eight inputs together to
create a byte-wide adder and cascade the carry bit from one adder to the another.

Circuit Diagram:

Dept. of CSE || RGUKT SRIKAKULAM Page 3

 COA Lab Manual

Truth Table:

FULL SUBTRACTOR: A full subtractor is a combinational circuit that performs

subtraction of two bits, one is minuend and other is subtrahend, taking into account
borrow of the previous adjacent lower minuend bit. This circuit has three inputs and
two outputs. The three inputs A, B and Bin, denote the minuend, subtrahend, and
previous borrow, respectively. The two outputs, D and Bout represent the difference
and output borrow, respectively.

Circuit Diagram:

Truth Table:

Dept. of CSE || RGUKT SRIKAKULAM Page 4

 COA Lab Manual

LAB 3: Verification of Ripple carry Adder and Carry-look Ahead Adder

Ripple Carry Adder: Ripple Carry Adder is a combinational logic circuit. It is used
for the purpose of adding two n-bit binary numbers. It requires n full adders in its circuit
for adding two n-bit binary numbers. It is also known as n-bit parallel adder.
Circuit Diagram:

Truth Table:

Dept. of CSE || RGUKT SRIKAKULAM Page 5

 COA Lab Manual

Carry-look Ahead Adder: A carry look-ahead adder reduces the propagation

delay by introducing more complex hardware. In this design, the ripple carry design is
suitably transformed such that the carry logic over fixed groups of bits of the adder is
reduced to two-level logic. Let us discuss the design in detail.

Circuit Diagram:

Truth Table:

Dept. of CSE || RGUKT SRIKAKULAM Page 6

 COA Lab Manual

LAB 4: Implement Booths Algorithm.

Booths Algorithm
1. Booth’s Algorithm is used to multiply two SIGNED numbers.
2. When we multiply two “N-bit” numbers, the answer is “2 x N” bits.
3. Three registers A, Q and M, are used for this process.
4. Q contains the Multiplier and M contains the Multiplicand.
5. A (Accumulator) is initialized with 0.
6. At the end of the operation, the Result will be stored in (A & Q) combined.
7. The process involves addition, subtraction and shifting.
Algorithm:
The number of steps required is equal to the number of bits in the multiplier. At
the beginning, consider an imaginary “0” beyond LSB of Multiplier
1. At each step, examine two adjacent Multiplier bits from Right to Left.
2. If the transition is from “0 to 1” then Subtract M from A and Right-Shift (A &
Q) combined.
3. If the transition is from “1 to 0” then ADD M to A and Right-Shift.
4. If the transition from “0 to 0” then add M to A and Right Shift.
5. If the transition from “1 to 1” then simply Right Shift.
Repeat the steps 1 to 5 for all bits of the multiplier.
The Final answer will be in A and Q combined.

Flow chart:

Dept. of CSE || RGUKT SRIKAKULAM Page 7

 COA Lab Manual

Example: 7 X 6 = 42

Dept. of CSE || RGUKT SRIKAKULAM Page 8

 COA Lab Manual

LAB 5: Implement Restoring and Non-Restoring Division Algorithm

Restoring:
1) Let Q register hold the divided, M register holds the divisor and A
register is 0.
2) On completion of the algorithm, Q will get the quotient and A will get the
remainder.
Algorithm:
The number of steps required is equal to the number of bits in the
Dividend.
1) At each step, left shift the dividend by 1 position.
2) Subtract the divisor from A (perform A - M).

Dept. of CSE || RGUKT SRIKAKULAM Page 9

 COA Lab Manual

3) If the result is positive then the step is said to be “Successful”. In this

case quotient bit will be “1” and Restoration is NOT Required.
4) If the result is negative then the step is said to be “Unsuccessful”.
In this case quotient bit will be “0”.
Here Restoration is performed by adding back the divisor.
Hence the method is called Restoring Division.
Repeat steps 1 to 4 for all bits of the Dividend.

Example: (6) / (4)

Non-Restoring:
1) Let Q register hold the divided, M register holds the divisor and A register is 0.
2) On completion of the algorithm, Q will get the quotient and A will get the remainder.
Algorithm:
The number of steps required is equal to the number of bits in the Dividend.
1) At each step, left shift the dividend by 1 position.

Dept. of CSE || RGUKT SRIKAKULAM Page 10

 COA Lab Manual

2) Subtract the divisor from A (perform A - M).

3) If the result is positive then the step is said to be “Successful”. In this
case quotient bit will be “1” and Restoration is NOT Required. The Next
Step will also be Subtraction.
4) If the result is negative then the step is said to be “Unsuccessful”.
i. In this case quotient bit will be “0”.
ii. Here Restoration is NOT Performed.
iii. Instead the next step will be ADDITION in place of subtraction
iv. As restoration is not performed, the method is called Non-Restoring
Division.
Repeat steps 1 to 4 for all bits of the Dividend.
Example: (7) / (5)

LAB 6: Implement Page Replacement Techniques

Page replacement happens when a requested page is not in memory (page
fault) and a free page cannot be used to satisfy the allocation, either because there are
none, or because the number of free pages is lower than some threshold.
We have three techniques of page replacement. They are
1) FIFO (First In First Out)

Dept. of CSE || RGUKT SRIKAKULAM Page 11

 COA Lab Manual

2) LRU (Least Recently Used)

3) LFU (Least Frequently Used)

LAB 7) Implement 2bit Multiplier

The circuit implements a two-bit by two-bit multiplier by multiplying each bit of
the multiplicand by each bit of the multiplier to form the partial products. The partial
products are then weighted and summed to get the overall product.
Circuit Diagram:

Dept. of CSE || RGUKT SRIKAKULAM Page 12

 COA Lab Manual

Truth Table:

Dept. of CSE || RGUKT SRIKAKULAM Page 13