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VLSI Testing and Testability: Fault Simulation

The document discusses fault simulation techniques used in VLSI testing and testability. It describes serial fault simulation where faults are injected one by one into a circuit and simulated sequentially. Various types of fault simulators are discussed including parallel, deductive, concurrent approaches. Fault dropping techniques are explained which help reduce computation by removing detected, hyperactive, and hypertrophic faults during simulation to improve efficiency.

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154 views

VLSI Testing and Testability: Fault Simulation

The document discusses fault simulation techniques used in VLSI testing and testability. It describes serial fault simulation where faults are injected one by one into a circuit and simulated sequentially. Various types of fault simulators are discussed including parallel, deductive, concurrent approaches. Fault dropping techniques are explained which help reduce computation by removing detected, hyperactive, and hypertrophic faults during simulation to improve efficiency.

Uploaded by

sanjay_nitt
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSI Testing and Testability

Fault Simulation

Dr. S. Sivanantham
School of Electronics Engineering
VIT University
Vellore 632014
INIDA
VLSI Testing and Testability
FAULT SIMULATION TECHNIQUES

 Basics
 Fault simulation algorithms
Serial
Parallel
Deductive
Concurrent
Differential
 Random Fault Sampling

VLSI Testing and Testability


What is fault simulation?

Circuit Fault Faulty outputs


Test patterns Simulator Undetected
Fault model faults
Fault coverage

Time Complexity

• Proportional to
 n: Circuit size, number of logic gates
 p: Number of test patterns
 f : Number of modeled faults
• Complexity = P * F *G~ O(G3) with single s-a faults
• Complexity is higher than logic simulation, O(G2), but is much lower
than test pattern generation.
• In reality, the complexity is much lower due to fault dropping and
advanced techniques.
VLSI Testing and Testability
Definitions
 Fault Specification Defining a set of modeled faults and
performing fault collapsing
 Fault Dropping The removal of detected, hyperactive and
hypertrophic faults during the run ( Inverse of
fault insertion)
 Fault Insertion Selecting a subset of faults to be simulated
and creating a netlist with these faults

Propagation of fault effects


A fault can be termed detected iff :
 It is activated by the test vector
 It’s faulty value is transferred from the effected net(internal) onto the
primary output pins

VLSI Testing and Testability


Fault Dropping
 Number of faults requiring simulation decreases as the run proceeds
because the main goal is to determine the fault coverage of a given
test pattern
 Detected faults can be immediately removed, drastically reducing the
average list length and thus the computing load
 Some faults must be removed in any case for the sake of efficiency.
These belong to two main classes: hyperactive and hypertrophic
faults
 Hypertrophic fault causes the network to remain in an unknown status
on almost all the nodes
e.g., a fault on a reset line
It cannot be detected, and wastes CPU time and memory.
 Hyperactive fault produces very high activity, e.g., a group of elements
starts to oscillate. It, too, is undetectable and very CPU-time consuming
Referred from “S.Gai, P.L.Montessoro, Fabio Somenzi, “MOZART, a Concurrent Multilevel Simulator”, IEEE Transactions on Computer-Aided Design,
vol. 7, no. 9, September 1988, pp. 1005-1016”

VLSI Testing and Testability


Fault Injection

VLSI Testing and Testability


Fault Simulator Flow

Logic simulation on both


good (fault-free) and
faulty circuits

Need for Fault Simulation


 To evaluate the quality of test set ; in terms of fault coverage
 To incorporate into ATPG for test generation
 To construct fault dictionary

VLSI Testing and Testability


Algorithms for fault simulation
The fault simulator must classify the given faults as detected or undetected by
the given stimuli

for all vectors in the test vector set:


• the fault-free circuit is simulated;
• copies of the the circuit, each having one fault are simulated
• the binary output is the fault-free, and faulty circuit simulations are
compared
• a different output means that current vector detects the fault that has been
injected into the simulated copy of the circuit

Remarks:
• expensive in computation
• fault dropping is applied, i.e. simulation is stopped after a specific fault fn
has been detected for the first time

VLSI Testing and Testability


Types of fault simulators
• Serial

• Parallel
– Simulation of w faults in parallel

• Deductive
– Predicts faulty responses from fault-free

• Concurrent
– Interleave faulty and true-value simulation

VLSI Testing and Testability


Serial Fault Simulation

 First, perform fault-free logic simulation on the original circuit


 Good (fault-free) response
 For each fault, perform fault injection and simulate the error netlist
 Faulty circuit response

Test vectors Fault-free circuit Comparator f1 detected?

Circuit with fault f1


Comparator f2 detected?
Circuit with fault f2

Comparator fn detected?
Circuit with fault fn

Each one of these computations are done one by one sequentially


VLSI Testing and Testability
Serial fault simulation
• Algorithm:
Simulate fault-free circuit and save responses for further comparison

Repeat following steps for each fault in the fault list:


1. Modify the netlist by injecting one fault
2. Simulate the modified netlist using every test vector
3. For each of the vector, compare the fault-free response and the current response
(one fault injected)
4. The fault is detected if the responses differ; the simulation process may be stopped
5. If the responses do not differ, then currently injected fault is not detected back to
step 1

• Advantages
– Easy to implement: a regular logic simulator is used, plus a mechanism for injecting
faults
– A wide range of fault models are supported
• Drawback
– Low performance: simulation time can be prohibitively high for large fault lists
e.g. for n faults, n time the simulation time of a true-value will be needed
VLSI Testing and Testability
Example

VLSI Testing and Testability

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