SKEE2263 Mini-Project Guide

Digital Design with the Amazing EPM240 Board

Release 2020

Mun’im Zabidi
 Administrivia
Objectives of the Mini-Project
■ To build a complete digital system design containing a datapath unit and control unit
■ To perform top-down design and bottom-up implementation of a digital system
■ To implement and test the design on a FPGA/CPLD board with all relevant I/O devices
■ To manage a team project with the aid of a Gantt Chart

The mini project contributes 30% of your overall marks. At the end of semester, you must
implement a complete digital system a FPGA/CPLD board. To ensure you successfully complete
the project, the mini project has six different stages, so that you build the complete system
incrementally. The following Gantt Chart outlines the tasks.

Project Scheduling

Lecture Weeks
Milestone Deliverable
1 2 3 4 5 6 7
1 Quartus familiarization
2 CPLD familiarization
3 Basic Input/Output
4 Finite State Machines
5 Datapath Unit
6 System Integration & Demo

What to Submit
1. Plagiarism Declaration — hardcopy

2. Marking Rubric -– hardcopy

3. Proof of Work — Demo, YouTube video or hardcopy documents depending on lecturer

preference

4. References — hardcopy

Required Equipment

Equipment Source
Quartus II Download at http://fpgasoftware.intel.com/13.0/?edition=web
EPM240 CPLD board
Ask your lecturer or find on Internet
USB Blaster
DuPont wires
Breadboard
LEDs Should be easy to find locally
DIP switches
Resistors

i
Tutorials
Application notes at http://raden.fke.utm.my/appnotes.

Additional Instructions
1. Your circuit must be modular

■ Remember the Three Y’s – modularity, hierarchy, regularity

■ Each module must be in a separate design file.
■ Each module must have its own

ä Schematic diagram/Verilog code/state machine diagram

ä Simulation waveform printout — highlight and comment important input/out-
put patterns
ä Compilation report screenshot

■ Each module must be verified (tested, simulated) separately before integration

2. PLO8 Compliant

■ PLO8 concerns lifelong learning.

■ Know how to find references ahead of time (material not yet covered in lecture)
■ Know how to transfer knowledge from an assignment stage (milestone) to later stages

3. PLO11 Compliant

■ PLO11 concerns ethics.

■ The plagiarism declaration must be signed to receive any marks.
■ You must find enough references and you must cite the references properly.

Tips and Tricks

A wise man said “Your questions will show your intelligence better than your answers.”

■ Think at high level = High Order Thinking Skills (HOTS)

■ For a related group of signals, bus groups must be used when displaying waveforms
■ Label the bus in a suitable number system (hex, decimal or binary as appropriate)
■ Show only what important, show everything that is important. Do not give too much
information.

ii
 PLAGIARISM DECLARATION
1. I know that plagiarism means taking and using the ideas, writings, works or inventions of
another as if they were one’s own. I know that plagiarism not only includes verbatim copy-
ing, but also the extensive use of another person’s ideas without proper acknowledgement
(which includes the proper use of quotation marks). I know that plagiarism covers this sort
of use of material found in textual sources and from the Internet.

2. I acknowledge and understand that plagiarism is wrong

3. I understand that my research must be accurately referenced. I have followed the rules and
conventions concerning referencing, citation and the conventions concerning referencing
and citation.

4. This assignment is my own work, or my group’s own unique group assignment. I acknowl-
edge that copying someone else’s assignment, or part of it, is wrong, and that submitting
identical work to others constitutes a form of plagiarism.

5. I have not allowed, nor will I in the future allow, anyone to copy my work with the intention
of passing it off as their own work.

Team Name

Name

Matric Number

Signature

Date

Name

Matric Number

Signature

Date

Name

Matric Number

Signature

Date

iii
 MILESTONE 1
Quartus Familiarization
Objectives
■ Familiarization with Altera Quartus for entering, compiling and simulating a logic design.
■ Describing a complex digital system using hierarchy, modularity and regularity
■ Creation of several low-level reusable subsystems to build a module library

Pre-Requisites
Download and follow the Quartus checkout procedure in Application Note AN03 Getting Started
with Quartus:
http://raden.fke.utm.my/appnotes/AN03%20Getting%20Started%20with%20Quartus.pdf

1.1 4-bit Ripple Carry Adder

1.1.1 Half-Adder

Step 1

Use Quartus schematic entry to input the half adder design.

Figure 1.1: Half-adder schematic.

Step 2

Compile the design. If there are no errors, print compilation report as PDF.

Step 3

Simulate by giving all 4 input combinations for a and b : 00, 01, 10 and 11. Maintain each input
combination for 100ns. That means the End Time for the simulation should be 400ns. Check the
result with the expected output. When the circuit is error-free, proceed to Step 4.

Step 4

Convert the module into symbol file. Call it ha.bsf.

1
Milestone 1 Quartus Familiarization

Step 5

Print the following 3 pages as PDF. You must choose landscape orientation.
Page 1: Schematic of half adder: Printscreen then convert to PDF.
Page 2: Compilation report
Page 3: Annotated simulation output waveform: This is not the same as the simulation input.
Printscreen first, then in MSPaint or similar software, highlight the important information. Save
as PDF.

1.1.2 Full Adder

Step 1

Use Quartus schematic entry to input two instances of half adder symbols from Part 1 Step 4.
Combine the two half adders with an or2 gate to build a full adder.

Half adder
Half adder
ai

bi si

c i+1
ci

Figure 1.2: Full adder schematic.

Step 2

Compile the design. If there are no errors, print compilation report as PDF.

Step 3

Simulate using all 8 input combinations 000 through 111. Maintain each input combination for
100ns. That means the End Time for the simulation should be 800ns. Check the result with the
expected output. When the circuit is error-free, proceed to Step 4.

Step 4

Convert the module into symbol file. Call it fa.bsf.

Step 5

Print the following 3 pages as PDF. You must choose landscape orientation.
Page 4: Schematic of full adder..
Page 5: Compilation report
Page 6: Annotated simulation output waveform..

2
 1.1 4-bit Ripple Carry Adder

1.1.3 Ripple Carry Adder

Step 1

Use Quartus schematic entry to input four instances of full adder symbols from Part 2 Step 4.
Combine to build the ripple carry as follows.

a3 b3 a2 b2 a1 b1 a0 b0

FA FA FA FA
c4 c3 c2 c1 c0

s3 s2 s1 s0

Figure 1.3: Full adder schematic.

Step 2

Compile the design. If there are no errors, print compilation report as PDF.

Step 3

In Table 1.1, fill in columns COU T and S[3 : 0] so you know what is the expected output for each
input combination. Columns A, B and S are in hex.

Table 1.1: Test data for ripple carry adder.

A[3..0] B[3..0] CIN COUT S[3..0] Comply?
0 0 0
F F 1
F 0 0
0 F 0
F 0 1
0 F 1
8 8 0
A 5 0
C 3 0
3 C 1

In the simulation waveform input, use bus groups for A, B and S signal. (A bunch of related
signals are called a bus.) Use hexadecimal system. Simulate using the given test data. Then mark
with the adder complies with the expected results. Simulate using the 10 input combinations
given below. Maintain each input combination for 100ns. That means the End Time for the
simulation should be 1000ns. When the circuit is error-free, proceed to Step 4.

Step 4

Print the following 4 pages as PDF. You must choose landscape orientation.
Page 7: Schematic of ripple carry adder..
Page 8: Compilation report

3
Milestone 1 Quartus Familiarization

Page 9: Annotated simulation output waveform..

Page 10: References. On this page, list all web sites, articles or books you referred in completing
the assignment. You must any citation format but be consistent.

Step 5

Combine all 10 PDF pages into 1 PDF document. Add the plagiarism declaration as the front
cover. Upload to elearning.utm.my.

1.2 Bus Multiplexer

A bus multiplexer selects data from one out two buses.

1.2.1 2:1 Mux

1. Enter the 2:1 mux design.

Figure 1.4: 2:1 mux schematic.

2. Compile the design.

3. Simulate by giving all 4 input combinations for a, b and s. Maintain each input combination
for 100ns.
4. Convert the module into symbol file. Call it mux21.bsf.

4
 1.2 Bus Multiplexer

1.2.2 4-bit Bus Multiplexer

1. Instantiate four copies of mux21 symbols from the previous step.

Figure 1.5: Bus multiplexer schematic.

2. Compile the design.

3. Simulate using the following test data.

Table 1.2: Test data for 4-bit bus multiplexer.

A[3..0] B[3..0] S Y[3..0] Comply?
F 0 0
0 F 0
A 5 1
5 A 1
8 8 0
A A 1

4. Convert the module into symbol file. Call it busmux4bit.bsf. It should like Fig. 1.6.

Figure 1.6: Bus multiplexer symbol.

5
Milestone 1 Quartus Familiarization

1.3 Data Register

A data register contains a set of flip-flops that can be loaded on demand.

1.3.1 Register Cell

1. Enter the register cell design as shown Fig. 1.7. Get the DFF symbol from the Quartus library
and mux21 symbol from the previous step of this assignment.

Figure 1.7: Register cell schematic.

2. Compile the design.

3. Simulate using the following input waveform:

Figure 1.8: Register cell simulation input.

Verify the function of the register cell.

4. Convert the module into symbol file. Call it regcell.bsf.

6
 1.3 Data Register

1.3.2 4-bit Data Register

1. Instantiate four copies of regcell symbols and connect as shown in Fig. 1.9.

Figure 1.9: 4-bit data register schematic.

2. Compile the design.

3. Simulate using the following input waveform:

Figure 1.10: 4-bit data register simulation input.

4. Convert the module into symbol file. Call it reg4bit.bsf. It should like Fig. 1.11.

Figure 1.11: 4-bit data register symbol.

7
 MILESTONE 2
CPLD Familiarization
Objectives
■ Getting started with EPM240 CPLD
■ Familiarization with various methods of design entry
■ Creation of more modules for design reuse

2.1 Pre-Requisites
Download and follow the EPM240 Board checkout procedure in AN04 EPM240 Board:
http://raden.fke.utm.my/appnotes/AN04%20EPM240%20Board.pdf
After going through the example in AN04, you should get a blinking LED driven by the EPM240
CPLD.

2.2 System Overview

In this milestone, you will build a Knight Rider lights using the CPLD and 6 LEDs. The overview of
the system is in Fig. 2.1.

VDD

50 1 Hz 4 10
mapper

clock BCD BCD

MHz prescaler counter decoder

Figure 2.1: Overview of the system.

We will create all low level modules first. Afterwards, they are integrated at the top level
schematic diagram.

9
Milestone 2 CPLD Familiarization

2.3 BCD Counter

Section Objective
Using the Library of Parameterized Modules (LPM) in the block diagram/schematic editor.

The BCD counter counts in Binary Coded Decimal, i.e. 0, 1, 2, · · · , 9, 0.

1. Create a new block diagram file.

2. Save the blank file as knightrider (or milestone2 etc) and set it as Top-Level Entity.

3. Call up the New Symbol dialog and type lpm_counter in the Name field.

Figure 2.2: Insert a new lpm_counter symbol.


4. On Page 2c, click  Next >
.

5. On Page 3, set the width of the ’q’ output bus to 4 bits. Click  Next >
.

6. On Page 4, set counter type to Modulus, with a count modulus of 10. Click  Finish
.

7. On Page 7, click  Finish
.

8. Place the new lpm_counter symbol anywhere on the schematic editor.

9. Add one input port.

10. Add a bus at the output of the counter and label it q[3..0]. Refer Figure 2.3.

Figure 2.3: Connecting the input port and lpm_counter.

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 2.4 BCD Decoder

2.4 BCD Decoder

Section Objective
Using traditional TTL IC equivalent symbols in the block diagram/schematic editor.

A 7442 BCD decoder has 10 outputs and accepts a value in the range of 0..9. The output is active
low. A value greater than 9 causes all outputs to be high.

1. Still in the schematic diagram from Section 2.3, call up the New Symbol dialog and type
7442 in the Name field.

Figure 2.4: Insert a new 7442 device.

2. Add regular wires to all inputs of the 7442. Label the inputs as q0, q1, q2, and q3. The BCD
counter is now connected to the BCD decoder. Refer to Figure 2.5.

Figure 2.5: Connecting BCD counter and BCD decoder.

11
Milestone 2 CPLD Familiarization

2.5 Mapper

Section Objective
Design entry using primitives.

The mapper is a custom circuit that maps 10 BCD outputs to 6 LEDs.

1. Create a new block diagram file

2. Insert four and2 gates, 10 input ports and 6 output ports.

3. Make the connection shown in Figure 2.6.

.
Figure 2.6: Mapper schematic.

4. Save it as mapper.bdf.

5. Set it as Top-Level Entity (temporarily) and compile it.

6. Save it as mapper symbol file (mapper.bsf).

Figure 2.7: Mapper symbol. Note: you can see this symbol by opening another block diagram document and
importing it.

12
 2.6 Simulating the Circuit

2.6 Simulating the Circuit

Section Objective
Simulating a partially-complete circuit.

1. Go back to the top level schematic.

2. Insert the mapper symbol and connect with the 7442 BCD decoder.

3. Add one input port to the BCD counter, and 6 output ports from the mapper.
The top level schematic should look like Figure 2.8.

Figure 2.8: The complete circuit so far.

4. Set this file as the top-level entity. Compile this file.

5. Create a new waveform file.

6. Insert all pins into the waveform file.

7. Using the default setting for end time, set the clock period so that you can see at least 10
clock cycles in the simulation window. You should see something like Figure 2.9.

Figure 2.9: Simulation using clock period of 40 ns.

8. Save a copy the top-level bdf file so that you have two copies of the same file. Give them
distinct names such as knight_partial.bdf and knight_final.bdf or something similar. Keep
the first file as a “fallback” schematic in case something goes wrong when you add extra
modules later. Modify only the second file in the following steps.

13
Milestone 2 CPLD Familiarization

2.7 Prescaler

Section Objective
Design entry using Verilog HDL.

The prescaler module slows the clock from 50 MHz to exactly 1 Hz.

1. Create a Verilog file and enter this code.

module prescaler ( input clkin , output reg clkout ) ;

reg [25:0] counter ;

always @ ( posedge clkin )

begin
if ( counter == 0)
begin
counter <= 24999999;
clkout <= ~ clkout ;
end
else
counter <= counter - 1;
end
endmodule

2. Save as prescaler.v.

3. Set it as Top-Level Entity (temporarily) and compile it.

4. Save the prescaler as Symbol file (prescaler.bsf).

Figure 2.10: Prescaler symbol. Note: you can see this symbol by opening another block diagram document
and importing it.

5. In the top-level schematic diagram, add the prescaler module. The circuit now look like
Figure 2.11. Set the top-level module back to this diagram.

Figure 2.11: Adding the prescaler.

Note
After the prescaler is added, the circuit can no longer be simulated.

14
 2.8 Programming the CPLD

2.8 Programming the CPLD

Section Objective
Programming the CPLD.

1. From the Assignments å Device menu verify that you have chosen the EPM240T100C5
device.

2. In the Assignments å Pin Planner verify that pin 64 is set to gclk.

Figure 2.12: Set pin 64 to gclk.

3. Assign 6 more pins for the output ports. You can use any I/O bank. For example, you can
use the settings from Figure 2.13 to use pins closest to ground pin on the EPM240 connector
block. However, any other combination can be used.

Figure 2.13: A possible selection of pins.

(The two I/O bank can theoretically use different supply voltages for interfacing. On the
red EPM240 board, this is not possible because the power supply rails are tied together.
Therefore, any I/O bank can be used.)

I/O bank VCCIO GNDIO

1 Pin 9, 31,45 Pin 10, 32, 46
2 Pin 59, 80, 94 Pin 60, 79, 93

4. Recompile the design. After recompilation, the assigned pins should appear at the top level
schematic. The final schematic should be like Fig. 2.14.

5. Connect the LEDs according to Figure 2.1.

6. Program it. The LEDs should display an interesting pattern.

Your lecturer may add another pattern to program on the CPLD.

15
Milestone 2 CPLD Familiarization

Figure 2.14: Final top level schematic.

16
 MILESTONE 3
Accumulator Based Vending Machine
Objectives

■ Interfacing CPLD with simple input/output devices

■ Design of high-level modules based on specifications
■ Building a circuit on a strip board

3.1 Overall Description

Implement a vending machine simulator illustrated in Fig. 3.1 on CPLD and circuit board. The
major components are:

Table 3.1: List of modules for vending machine.

Module# Module Source
1 Adder Milestone 1
2 Accumulator Milestone 1 & Chapter 8
3 Knight Rider lights Milestone 2
4 Prescaler Milestone 2 & Subsection 9.4.3
5 Comparator Section 6.4
6 Binary-to-BCD converter Section 6.2
7 Input filter Section 9.3
8 Selector New

The vending machine is based on a 4-bit accumulator which keeps tracks of how much money
has been deposited. The accumulator value equals multiples of 10 sens. It has two button inputs:
button 1 for 20 sen, button 2 for 50 sen. Pressing a button adds 2 or 5 to the accumulator.
The 7 segment display shows the current value of accumulator in BCD up to 15. When the
accumulator contains 12 or more, the Knight Rider LEDs (from Milestone 2) will display one round
of lights (as opposed to unlimited rounds in Milestone 2).
Implementation steps:

1. Prepare all modules in Table 3.1. Simulate all independently, except the prescaler (module
4).
2. Integrate/combine all modules, except the prescaler, and simulate.
3. Prepare an I/O board consisting of two seven-segment displays, and two switches and
the necessary resistors. It is highly recommended to use a stripboard for the 7-segment
display to avoid connectivity problems. The switch can be on the same stripboard or on a
breadboard; it is less critical due to fewer wires required.
4. Add the prescaler, connect the I/O board with the CPLD and program the CPLD.

The following sections describes the module functions, grouped by level of reuse.

17
 4
3.3V 7
SW1 4 4 4
Accumulator Binary-to-BCD
7
Input filter
3.3V 4 Clear
Milestone 3 Accumulator Based Vending Machine

Selector 3.3V
SW2
Input filter
4
A Knight
A>B
Comparator Rider
4
1011 B lights
CLK2(approx.100Hz)
50MHz Prescaler
CLK1(approx.1Hz) DONE
Figure 3.1: Block diagram of vending machine

18
 3.2 Modules from Previous Milestones

3.2 Modules from Previous Milestones

3.2.1 Adder
The 4-bit ripple carry adder from Milestone 1 can be used directly without modification. No
simulation is necessary for this circuit as it is completely reusable.

3.2.2 Accumulator
The procedure to build the accumulator from Milestone 1 can be followed. However, the function
is different. In this accumulator, the control line is called Clear.

Clear Function
0 Loads data at D0-D3
1 Register is cleared (Q←0) on next clock edge

D3 D0

D Q D Q

Clear
Clk
Q3 Q0

Figure 3.2: First and last cells of the register with synchronous clear.

Build and simulate one cell first. Then combine 4 cells to build the accumulator. Show the
compilation report, schematic and simulation of the 4-cell accumulator only.

3.2.3 Knight Rider Lights

The Knight Rider lights from Milestone 2 runs forever. Make two modificaitons:

■ Add a control signal circuitry to enable/disable the lights, so that the LEDs runs only when
this input is high.
■ Add a status signal (DONE) that indicates when the lights have run a complete round.

Simulate to check if the circuit can be enabled/disabled on demand, and the DONE is activated
at the correct time.

3.2.4 Prescaler
This prescaler generates two outputs:

■ CLK1: a signal approximately 1 Hz. This speed is required so that the Knight Rider light can
run slowly and visible to humans.
■ CLK2: a signal approximately 100Hz. This speed is required to eliminate contact bounce
that happens when a button is pressed.

Implement the prescaler using a 26-bit up counter from LPM_COUNTER. Use bit 25 as CLK1
and another bit as CLK2. Do not use the Verilog version.
Do not simulate the prescaler. Do not integrate it with the main system yet. We will add it at the
final construction stage.

19
Milestone 3 Accumulator Based Vending Machine

3.3 Modules based on Circuit in Textbook

3.3.1 Comparator
The comparator gives a high output when the accumulator contains a value more than 11.
Choose a combinational or iterative comparator from Section 6.4. For the comparator, show the
compilation reports, schematics and simulation.

3.3.2 Binary-to-BCD Converter

The input to the converter is a binary input 0000 to 1111. The outputs are 7 lines to the tens digits
and 1 line to the ones digit. Inside the converter, the binary input is first converted to BCD to
produce a two-digit BCD result using the conditional add by 3 adder (cadd3) module in Section
6.2.
A 7447 module turns the proper segments on the right hand LED display. No 7447 is necessary
for the left hand LED display because it is either turned off or displays the number 1. This is
because the range of numbers displayed is limited to 0 through 15. The tens digit is represented
by d 4 which can be either 0 or 1. Simply connect d 4 to both segments b and c to display the
number 1 when required.

d4 to segments b, c
d4
0
d3
b3
cadd3 d2
b2 7-segment codes
d1 7447
b1 to ones display
b0 d0

Figure 3.3: Binary-to-BCD converter with BCD-to-7-segment decoder combination.

3.3.3 Input Filter

Button presses produce glitches lasting 1-10 milliseconds which are detected as multiple presses
if a fast clock is used. A slow clock at the filter removes the glitches. The function of the input filter
is to convert a button press into a single clean pulse.
Note that if the clock is too slow, the user must press the button for an unreasonable amount of
time before the button press is detected. The frequency of clock input is not fixed. Change it to a
suitable frequency depending on the switches used.

pulse out
switch in D Q D Q

100 Hz

Figure 3.4: Input filter.

You will need two copies of the filter, one for each button. The buttons are active low, meaning
that it is high when not pressed, and low when pressed. The circuit is Fig. 3.4 produces a single
pulse when a high-to-low transition is detected at its input.

20
 3.4 Selector

3.4 Selector
The adder add the current value of the accumulator (first input) and the value chosen by the
selector circuit (second input). The selector chooses a value to place at the second adder input
based on this table:

Switch Pressed Second adder input Accumulator function

None 0000 Hold
SW1 0010 ACC ← ACC + 2
SW2 0101 ACC ← ACC + 5

The selected value is presented for exactly one clock cycle for every button press. This is a
combinational circuit which your team must design.

3.5 Obtaining Maximum Credit

For each new module:

■ Compile until there are no errors.

■ Test/simulate using carefully selected data inputs.
■ Convert to symbol
■ Record a very short video of the entering the design (while using schematic editor or Verilog
editor).

21
 MILESTONE 4
Finite State Machines
Objectives
■ Basics of finite state machine

4.1 Preliminaries
Read the following application notes

■ AN05 Finite State Machines with Quartus State Machine Editor:

http://www.fke.utm.my/simsv1.1a/upload/labsheet-upload/AN05%20FSM%20with%20State%
20Machine%20Editor.pdf
■ AN06 mplementing One Hot State Machines Using Schematics:
http://www.fke.utm.my/simsv1.1a/upload/labsheet-upload/AN06%20One%20Hot%20State%20Machines%
20(2).pdf
■ SPACE video submissions from previous semesters:
http://raden.fke.utm.my/blog/skee22631891milestone2submissions-1

4.2 Overview of the Problem

Using the same hardware setup as the “nickel-and-dime” vending machine, build a combination
lock which runs one round of the Knight Rider lights (from Milestone 2) when the proper sequence
of buttons are pressed. Each group solves a different sequence. The possible options are:

DDDN DDND DDNN DNDD DNDN DNND DNNN

NNND NNDN NNDD NDNN NDND NDDN NDDD

After the LEDs have finished running, the machine returns to the intial state. Do not reset the
CPLD to return to the initial state.

4.3 Using State Machine Editor

This section is worth 40% of the assignment.

1. On paper, sketch the state diagram to detect the sequence given to your group. Solve it
using both Moore and Mealy approaches. Keep this sketch as your documentation.

2. Enter one state diagram (either Moore or Mealy) using the State Machine Editor in Quartus.

3. Convert to HDL and compile the design.

4. Simulate the design to check the correctness of the state diagram.

5. When simulation is successful, add the Input Filter, Prescaler and Knight Rider (from
Milestones 2 and 3).

23
Milestone 4 Finite State Machines

6. Program the CPLD.

7. Test it. The Knight Rider lights should run once when the correct sequence is entered on
the pushbuttons.

If you’re submitting the milestone by video, record the process of building and testing this circuit.
Show that entering the correct button sequence turns on the Knight Rider.

4.4 One Hot Encoding Using Schematic Editor

This section is worth another 20% of the assignment.

1. Based on the Moore version of the state diagram, get the next state equations and output
equation.

2. Enter the circuit using the Schematic Editor.

3. Simulate the design.

4. Add the Input Filter, Prescaler and Knight Rider.

5. Program the CPLD and test.

4.5 Binary Encoding Using Schematic Editor

This section is the final 40% of the assignment.

1. Based on the Mealy version of the state diagram, derive the state table. Use straight/se-
quential binary encoding.

2. Get the next state equations and output equation.

3. Enter the circuit using the Schematic Editor.

4. Simulate the design.

5. Add the Input Filter, Prescaler and Knight Rider.

6. Program the CPLD and test.

24
 MILESTONE 5
Datapath Unit Implementation
Objectives

■ Identifying components to construct a datapath unit

■ Integrating the components of the datapath unit
■ Testing the datapath unit

For Milestones 5 and 6, each group will be specified a complex digital system. The options are
in Table 5.1. The list is not exhaustive. Your lecturer may have extra topics available. You can also
propose your own topic.

Table 5.1: List of possible topics

Level of
Title Starting Point
Difficulty
Ones counter 1 In-book
GCD finder v1 2 In-book
Serial adder 3 In-book
Binary multiplier 3 http://freeusermanuals.com/backend/web/manuals/1523428835ASM_design_example_bin_mult.pdf
GCD finder v2 3 http://esd.cs.ucr.edu/labs/gcd/gcd.html
GCD finder v3 3 http://csg.csail.mit.edu/6.375/6_375_2006_www/handouts/lectures/L03-Verilog-Design-Examples.pdf
Serial binary-to- 3 https://www.digikey.com/eewiki/pages/viewpage.action?pageId=60030986
BCD converter
Laser based dis- 4 http://www2.engr.arizona.edu/~rlysecky/courses/ece274-08s/lectures/lecture13.pdf
tance measurer
UART transmitter 4 http://electrotech99.blogspot.com/2011/05/design-and-implementation-of-uart.html
Serial multiplier 4 http://digsys.upc.edu/ed/CSD/prob/Ch3/P10/Prob3_10.html
Booth multiplier 5 http://www.cse.iitd.ernet.in/~neeraj/TA/cs316/2005-2006/project/final/mansi/
Integer square 5 https://pdfs.semanticscholar.org/9b7e/07f3b5ed9c168f13206836a326bd9b91135a.pdf
root
Serial divider 5 https://www.csee.umbc.edu/portal/help/VHDL/samples/samples.shtml#div_ser
UART receiver 5 https://www.engr.siu.edu/haibo/ece428/notes/ece428_uart.pdf

The steps for building the datapath for a naïve multiplier is shown in this handout. Follow the
same procedure for the circuit assigned to you.

5.1 Problem Formulation

Every datapath unit solves an algorithm. Writing the algorithm in C lets us simulate the algorithm
at a very high level to verify its correctness.
Evry CU+DU has a different algorithm. Although the top-level function is the same, the circuits
to solve the function can be very different.
Multiplication in digital systems can be done many ways. The naïve method is by repeated

25
Milestone 5 Datapath Unit Implementation

addition of the multiplicand. A naïve multiplier performs multiplication by repeated addition1 .

In this multiplier, multiplying 2 by 5 means performing the addition five times:

0 + 2 + 2 + 2 + 2 + 2 = 10

The algorithm for computing P ← M × N is as follows:

int naivemultiplier ( int M , int N) {

int P ;

P = 0;
while ( N != 0) {
P = P + M;
N = N - 1;
}
return P ;
}

Table 5.2: Clock-by-clock countdown of Multiplier datapath.

Data Signals
Multiplicand Multiplier Product Init Work Zero
(M) (N) (P)
? ? ? 1 0 0
2 5 0 0 1 0
2 4 2 0 1 0
2 3 4 0 1 0
2 2 6 0 1 0
2 1 8 0 1 0
2 0 10 0 0 1

CU
Go Valid
Init Work Zero

DU

M 4 A[7..4]
0000
A
Init Load A[3..0] 8
M + P
Init Clear
4-bit Register B Work Load

N
Zero
8-bit Adder
P
4
8-bit Accumulator
Init Load
Work Count 4

N 8
4-bit Down counter

Figure 5.1: Naive multiplier DPU + CU.

1 A binary multiplier typically uses the binary system which can reduce hardware and execution time.

26
 5.2 Identify and Construct the Building Blocks

5.2 Identify and Construct the Building Blocks

Identify the components required to build a 4-bit × 4-bit multiplier:

■ Adder
Extend the adder from Milestone 1 from 4 bit to 8 bit.
■ M register
4-bit register with enable. This register must have 4-bit input, 4-bit output and Load control
input.
■ N register
This “register” is actually a 4-bit down-counter with load capability. The register must
have 4-bit data input, Load control input, Count down enable input and Zero output. The
Zero output is high when the counter reaches 0000. The actual value of the register is not
important except for debugging.
■ P register
8-bit register with enable. This register must have 8-bit input, 8-bit output and Load control
input.

Design and build each component and test independently. This is a design course. As a digital
designer, you are expected to be able to design each module yourself, individually. You are free
to use lpm built-in modules, create your own module using schematics or write Verilog code to
implement the modules.

5.3 Integration

1. Connect the datapath according to Fig. 5.2.

2. Test the datapath using sensible test data. Before you simulate, you should know what
the expected outputs are. Ability to select input data and to verify circuit operation is also
expected from all digital designers.
3. Save the datapath as a symbol file.

lpm_ff1 lpm_add_sub0
DFF
M[3..0] INPUT
VCC data[3..0] dataa[7..0] acc
d[3..0] A
clock result[7..0] OUTPUT P[7..0]
q[3..0] d[7..0] A+B D[7..0] Q[7..0]
enable datab[7..0]
B Load
inst3 d[7..4] inst
Clear
Clock

GND
inst4

Clock INPUT
VCC

lpm_counter0
down counter
Init INPUT
sload
VCC
N[3..0] INPUT
data[3..0]
VCC

q[3..0] OUTPUT Q[3..0]

clock OUTPUT Zero
cout
Work INPUT
cnt_en
VCC

inst5

Figure 5.2: Naive multiplier datapath. The signal group Q[3..0] shows the current value of the counter. It is
not used in the final system because the controller only needs to know whether the counter has
reached zero (cout=Zero=1).

27
Milestone 5 Datapath Unit Implementation

Figure 5.3: Simulation of naive multiplier datapath. The Work signal enables the counter to count down and
the acccumulator to load a new value. When the controller is added later, Work can be stopped
automatically when Zero = 1.

You have achieved Milestone 5 by correct simulation of the datapath unit.

28
 MILESTONE 6
Controller Implementation
Objectives
■ Implementing the control unit to manage the datapath unit from the previous milestone
■ Integrating the control unit with the datapath unit
■ Demonstrating the complete system in hardware

6.1 Procedure
Fig. 6.1 illustrates the procedure for controller design.

State Machine
Editor
One-hot controller

High-level Low-level Schematic

Algorithm Highly encoded controller
ASM ASM Editor

Verilog
Text Editor

VHDL

Figure 6.1: Procedure for controller design.

■ Algorithm describes the problem at high level. This is usually given as C code fragment or
pseudo-code.
■ High-level ASM converts the algorithm to an ASM chart that closely follows the algorithm
using the Register Transfer Language (RTL) notation. All variable names used in the
algorithm are maintained.
■ Low-level ASM replaces the RTL statements to control and status signals as defined in the
datapath unit.
■ The controller is finally implemented using one-hot or one of the highly encoded state
assignments. For full marks, submit a implementation based on the one-hot approach. For
quick prototyping and for partial marks, you can use the State Machine Editor. The highly
encoded state assignment is not recommended because the large number of inputs to the
next state logic.

29
Milestone 6 Controller Implementation

6.2 High-Level ASM

The high-level ASM for the naive multiplier is given in Fig. 6.2.

Reset

S0

0
Go

1
0
P ← 0,
M ← multiplicand, 1
N ← multiplier Go

S1 S2
P←P+M
Valid ← 1
N←N-1

0 1
N=0

Figure 6.2: High-level ASM for naïve multiplier.

Convert the high-level ASM chart to the low-level version first.

6.3 Low-Level ASM

From the low-level ASM chart, you can complete the design directly using one-hot method or you
can experiment with State Machine Editor first. The low-level ASM for the naive multiplier is given
in Fig. 6.3.

Reset

S0 001

0
Go

1 0

1
Init Go

S1 010 S2 100

Work Valid

0 1
Zero

Figure 6.3: Low-level ASM for naïve multiplier.

From the low-level ASM chart, you can complete the design directly or you can experiment with
State Machine Editor for first.

30
 6.3 Low-Level ASM

Based on the low-level ASM, the next state equations are:

S 0+ = S 0 · Go0 + S 2 · Go0
S 1+ = S 1 · Zero0 + S 0 · Go
S 2+ = S 1 · Zero + S 2 · Go

The three outputs of the controller are:

Init = S 0 · Go
Work = S 1 · Zero0
Valid = S 2

The controller can now be entered using the schematic editor. The result is shown Fig. 6.4.

Go

S0
+
S0 S0 Init
D Q
S2

S0
+
S1 S1
D Q
S1 Work

S1
+
S2 S2
D Q Valid
S2

Zero
Clock

Figure 6.4: Controller for naïve multiplier. The inverted first flip-flop method is used to automatically start the
one-hot controller upon power-on-reset.

31
Milestone 6 Controller Implementation

6.4 System Integration

Create a symbol for the controller. Then create the actual top level entity in Quartus where you
can import both the controller and datapath units. The top level entity should now look like the
one in Fig. 6.5.

Parameter Value Type

Idle 0 Signed Integer
Main 1 Signed Integer
Done 2 Signed Integer
controller

Reset INPUT reset Valid OUTPUT Valid

VCC
Clock INPUT clock Init
VCC
Go INPUT Go Work
VCC
Zero

inst

datapath

Multiplicand[3..0] INPUT OUTPUT Product[7..0]

VCC M[3..0] P[7..0]
Clock Q[3..0]
Init Zero
Multiplier[3..0] INPUT
VCC N[3..0]
Work
inst1

Figure 6.5: Top level entity for the project.

Test it by giving some numbers to multiply such as 0 × 0, 1 × 1, 2 × 5, and 15 × 15. In the

waveform editor, put the numbers you want to multiply in the Multiplicand and Multiplier bus
signals, then give a short high pulse on the Go signal to load the data into the datapath and start
the multiplication.

Figure 6.6: Simulation of 4 × 3 and 15 × 7 at the module level. Annotations helps the reader look at the
important parts of the waveform.

Page 1 of 1 Revision: naivemulitplier

32
 6.5 Demonstration

6.5 Demonstration
After the simulations have shown the circuit to work correctly, add the necessary input and output
modules such as in Fig. 6.7. The number of DIP switches and LED displays depends on the bit
width used in your particular circuit.

3.3V

Go 1 EPM240
board 7

A Result displayed
Operand1 4
in hex or decimal
B 4
7
Operand2

Binary input from

DIP switches

Figure 6.7: Demonstrating the CU+DU with decimal output. Shown here, A = 4, B = 3 and P = 4 × 3 = 12.

To demonstrate, enter the operands using the DIP switches, and press Go. After some
processing, the output should be visible on the displays. You may want to use a slow clock so
that intermediate results can be made visible.
You can also use the hexadecimal number system to display the output. For example, the
biggest value generated by the multiplier is 15×15 = 225 which requires three digits in decimal, but
only two digits in hexadecimal. However, you must replace the 7447 decimal-to-seven-segment-
display code converter with your own converter.

33