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4 COMPUTER ORAGNIZATION and Architecture

The document is a computer organization and architecture exam paper containing multiple choice and long answer questions. It tests students on topics like cache memory, addressing modes, DMA, storage hierarchies, and virtual memory.

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23 views

4 COMPUTER ORAGNIZATION and Architecture

The document is a computer organization and architecture exam paper containing multiple choice and long answer questions. It tests students on topics like cache memory, addressing modes, DMA, storage hierarchies, and virtual memory.

Uploaded by

Cricket Top 10
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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ST.

XAVIER’S COLLEGE (AUTONOMOUS), PALAYAMKOTTAI - 627 002


SECOND CONTINUOUS INTERNAL ASSESSMENT TEST (ASSIGNMENT)
PAPER : COMPUTER ORGANIZATION AND ARCHITECTURE
I BCA SEMESTER : II
TIME : 1 ½ HRS. MARKS : 50

PART - A
ANSWER ALL: 5×1=5
1. In ______________ cache memory, the word is written into cache and main
memory at the same time.
a) copy-back b) write-through c) copy-both d) write-back
2. MICR stands for ___________________________.
a) Magnetic Interface Character Resolution c) Magnetic Ink Card Reader
b) Magnetic Ink Character Reading d) Magnetic Ink Code Register
3. The transfer of data directly into high-speed main memory using the bus and
bypassing the CPU is ___________________.
a) DMA b) MMA c) CMA d) RMA
4. In _____________ addressing mode, the operand value is directly specified.
a) Direct b) Relative c) Immediate d) Indexed
5. Division by zero causes an ____________ interrupt.
a) external b) internal c) infinity d) none
PART - B
ANSWER ANY FOUR: 4 × 5 = 20
6. Explain about the storage hierarchies.
7. Discuss about the error detecting and error correcting codes.
8. Explain about Memory-Mapped I/O.
9. Discuss about the Register Transfer Language.
10. Explain about the flags, Condition Codes and Status Registers.
11. Discuss about RISC and CISC Architectures.
PART - C
ANSWER ANY ONE: 1 × 10 = 10
12. Explain about cache memory with diagrams.
13. Discuss about the Instruction cycle and Execution cycle organization.
PART - D
ANSWER ANY ONE: 1 × 15 = 15
14. Explain about virtual memory in detail.
15. Discuss about the various addressing modes in detail.
***

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