CADENCE 6.

x LAYOUT TUTORIAL
This tutorial starts off from the assumption that you are already familiar with version 6.0 of the Cadence
Suite. The previous chapters in this course deal with the Schematic, Symbol and Analog Simulation
components of the 6.0 version of the Cadence Suite.

The technology that will be used throughout this brief tutorial is AMS 0.35um, option c35b41 . To init this
technology and start using the Cadence Suite, type tools in your terminal window2. Then, in the IMSE-CAD
window, as shown in the next figure, select:

Distribution 2015/2016 > DFWII IC 6.1.6 > AMS Hit-Kit 4.10.

The command to launch the Cadece Suite with the selected AMS technology is:

ams_cds -mode fb -tech c35b4

Once you have done this, the Cadence Suite is launched. You must select also the specific variety of the
technology, as shown in the following figure:

Proceed as described in previous lessons to create a new library attached to the technology. In the window
Attach Library to Technology Library you must select TECH_C35B4.
You have created the library where you will work and
create the designs for the exercises in this lesson. In
these exercises you will create the layout view of different
designs, you will check if these are correct according to
the design rules of the technology, you will compare
different (schematic and layout) views to search for
inconsistencies, and will obtain the parasitics associated
to the layout view.

The rest of the tutorial is goes through the following

• Creating the layout view

1 This option refers to one of the flavors of the technology, such as the number of metals

2Remember that every technology to be used in the Cadence Suite must be launched from a dedicated folder. That is, if
you used two different technologies, start each one in a different folder.
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• Setting Display options
• Working with primitives
• Routing
• Using labels
• DRC
• LVS
• QRC
• Post-layout simulation

In this tutorial, you will create the layout of an inverter. Go to the Library Manager and, in your library, create
a new cell with an identifying name (such as test or inv), selecting the Type as layout.

The Virtuoso Layout Suite window opens immediately and contains the technology layers. In the next
figure you can see that window. While all the commands and menus are at the top of the window (in this
tutorial we will not go through each and every command and action), the two most important sections are the
one on the left, the Layers section, and the large, black section, which is where all layout elements and
objects are drawn by the designers.



Important: Before you start the layout, you should check the grid configuration. In the Virtuoso Layout Suite
window, choose Options → Display and edit the fields in Grid Controls, particularly the spaces X and Y
Snap. The following figure shows the configuration window with the right values.
To draw transistors with Virtuoso Layout Suite we can make use of the parametric cells. These are cells that
have already the layout of the transistors, and even other components like resistors or capacitors, depending
on the design kit of the foundry. Some guidelines are presented next:

• You can get nmos4 and pmos4 transistors from PRIMLIB by adding an instance like in the schematic
window, but now when you insert it you should choose the layout view
• For the present design substrate contact of both transistors should be included (choose it in the
parametric cell menu).
• To draw layers you must select the drw version (drawing) of the layer in the Layers tab and create
rectangles with the shortcut key 'r'.
• To draw the routing between contacts use metal 1.
• To create contacts you should select Create → Via.
• You can create rulers to measure distances between components. To do this, select Tools → Create
Ruler.
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Now you must name the nodes to match with the schematic view. This is done with labels.
Let us suppose that your inverter schematic looks something like this:

The procedure for putting the same labels in the layout is is explained next:

• Generally, the labels are created for metal1 layers. In the Layers tab select the layer PIN metal1.
• Next, in the Virtuoso Layout Suite, select Create → Label. The names chosen must match the names
defined in the schematic window: in, out, vdd!, and gnd!.
• If you feel necessary, change the Height size to about 0.5. During this step, if the label is still not visible
in the layout window, press TAB.

Important: Do not forget to select the layer PIN metal1 before you create the label. For instance, in the
figure, we have vdd! with metal1. Therefore, we have selected PIN metal1 in the Layers and just after that
we have created the label. Note that in the figure, the '+' defines the layer that is associated to the label.

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 ***

Now you must check if there are any errors in your layout, that is, you have to perform the Design Rule
Check (DRC). In this tutorial, the Assura software will be used. Thus, select Assura → Run DRC in the
layout editor.

For now, just specific rule validations will be checked. A group of rule validations is commonly known as
switches. You can find them in the window Run Assura DRC. To define the switches you should select Set
Switches and then with the CTRL key you can select more than one switch. Some key informations about
the technology we are using in this tutorial:
• Until the final stage of the layout of circuit, one can use the switches: no_coverage and
no_generated_layers.
• During the phase that we are more interested in the drawing rules violation, one can use also the
switches: no_erc and no_info.
• All the other DRC parameters must not be changed.
Note: switches are technology dependent.
If you repeat the DRC and if there is already previous data, select OK to overwrite and Yes to stop seeing
the current one. After that, select Yes to display the results.

Finally, the only with the switches no_coverage and no_generated_layers should not give any error!
Note: If there are errors, select AV (meaning All Visible) in the Error Layer Window that will show. This
allows you to see all the errors existent. Probably you will have to make a refresh on the layout window:
Window → Redraw or Window → Fit All. The colors of the errors match the ones given in the Error Layer
Window.

***

Next, we will perform the circuit extraction, that is, all the parasitics resulting the layout of the devices
(capacitances, diodes, and other components that can exist due to the interaction between different layers).
The layout view will also be compared with the schematic (Layout versus Schematic, or simply LVS)


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Without any DRC error, select Assura → Run LVS. In the main form press Set Switches, select the
resimulate_extracted option and press OK. This ensures the use of this LVS run for RCX.
In the main form press OK to start LVS.

***

If there are not LVS errors you can proceed with the extraction by Assura → Run QRC and choose the
Extraction tab. For the reference node (Ref Node) write gnd!. Proceed with OK.
If you prefer, you can also display the electrical connections between the extracted elements. You just have
to configure the display by doing Options → Display and add Nets or other elements in Display Controls.

***
Now it’s time to simulate the layout in the same way you did with the schematic. This is the only way we have
to know how the layout parasitics impact the performance of our circuit. We will go 2 methods to do the post-
layout simulation.

METHOD 1
For the present case, a quick solution is the following: Open the view av_extracted, then from there open
the ADE and load the state that you have saved in the schematic simulation (where the voltage values are
already configured and also the outputs to be plotted). Then, run the simulation and voilà!

METHOD 2
Alternatively, and as a method that generally used to any post-layout for any given cell (particularly for many
different cells) the post-layout simulation is performed as follows.

In the Library Manager window create a new view in the library inverter (File → New → Cell View), which
will be the schematic view of the inverter testbench.

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Create a circuit as the one shown in figure. Use the cell inv designed by you (use the symbol view). You can
find the other devices in the library analogLib. The square waveform generator is vpulse (between 0 and
3.3V, pulse width 2.5n, period 5n, and equal rise and fall times 100p).

The DC supply is vdc with the value 3.3V. The other components are vdd and gnd, also found in the
analogLib. With the DC source as depicted in figure the internal nodes are automatically defined (vdd! and
gnd!). The pin out is just used to avoid Warning from the simulator, although the use of a capacitive load
would be more appropriated to this design.
Do Check and Save and you can close the Schematic view. Now, create a new cellview of the cell
inv_testbench choosing the tool Hierarchy-Editor and proceed with proceed with OK.

It will open the configuration window. Choose Use Template and Spectre. Edit the values to match the
following figure and proceed with OK.

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Open now the view config in the Library Manager. Select the Topcell schematic.

In the schematic (note that it is the view config) open the ADE. Configure the simulation. The post-layout
simulation results are presented below.

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