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CS322 - Handout Computer Organization and Architecture - Updated

This document provides information about the course CS322 Computer Organization and Architecture offered in the 2021-2022 academic year. The course is offered at the Faculty of Science and Technology and aims to provide students with an understanding of computer structure, operation, and design. It will cover topics like functional units, bus structures, instruction cycles, CPU design, pipelining, memory hierarchy, and I/O interfacing. Students will be evaluated through tests, quizzes, and a comprehensive exam. The course is taught across 45 lectures and references computer organization textbooks.

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Kiran Trade
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Download as PDF, TXT or read online on Scribd
146 views

CS322 - Handout Computer Organization and Architecture - Updated

This document provides information about the course CS322 Computer Organization and Architecture offered in the 2021-2022 academic year. The course is offered at the Faculty of Science and Technology and aims to provide students with an understanding of computer structure, operation, and design. It will cover topics like functional units, bus structures, instruction cycles, CPU design, pipelining, memory hierarchy, and I/O interfacing. Students will be evaluated through tests, quizzes, and a comprehensive exam. The course is taught across 45 lectures and references computer organization textbooks.

Uploaded by

Kiran Trade
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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ICFAI Foundation for Higher Education, Faculty of Science and Technology

(Declared as Deemed-to-be university u/s 3 of the UGC Act 1956)


Faculty of Science and Technology
2021-2022
Course Handout

Course No: CS322 Course Title: Computer Organization and L P U


Architecture 3 0 3

Course Objectives

1. To have a thorough understanding of the basic structure and operation of a digital computer.
2. To study the different ways of communicating with I/O devices and standard I/O interfaces.
3. To impart an understanding of the internal organization and operations of a computer.
To introduce the concepts of processor logic design and control logic design.

Learning Outcomes
Upon successful completion of the course, student will be able to:
1. Identify the basic structure and functional units of a digital computer.
2. Analyze the effect of addressing modes on the execution time of a program.
3. Design processing unit using the concepts of ALU and control logic design.
4. Identify the pros and cons of different types of control logic design in processors.
5. Select appropriate interfacing standards for I/O devices.
6. Identify the roles of various functional units of a computer in instruction execution

Instructor-in-charge: 1. DR. SANDEEP KUMAR PANDA

Text Book T Hamacher C., Z. Vranesic and S. Zaky, Computer Organization, 5/e,
McGraw Hill, 2011, 5th Edition.
Mano M. M., Digital Logic & Computer Design, 4/e, Pearson Education,
Reference book(s) R1
2013. 6th Edition.
Patterson D.A. and J. L. Hennessey, Computer Organization and Design,
Reference book(s) R2
5/e, Morgan Kauffmann Publishers, 2013, 6th Edition.
Lecture-wise plan:

Lecture No. Learning Objective Topics to be covered Reference

1-2 Introduction Basic Structure of computers–functional units T1 Ch.1


– basic operational concepts.
3-9 Bus Structure, Bus structures – software. Memory locations T1 Ch.2
Addressing Mode, and addresses – memory operations –
Instruction Cycle instructions and instruction sequencing –
addressing modes –Basic I/O operations –
stacks subroutine calls. Basic processing unit
– fundamental concepts – instruction cycle -
execution of a complete instruction –multiple-
bus organization – sequencing of control
signals.

10-12 CPU design Introduction to CPU design, Instruction R1 Ch.5, R2


interpretation and execution, Micro-operation
and their RTL specification, Hardwired
control CPU design, Micro-programmed
control CPU design.

13-24 Pipeline Flynn’s classification, Introduction to R2


pipelining and pipeline hazards, design issues
of pipeline architecture, Instruction level
parallelism and advanced issues, Cache
coherence.

25-30 Threading Simultaneous Multithreading, Interconnection T1 Ch.4, R2


network
31-40 Memory Memory Concepts, Memory Hierarchy, R2
Physical memory design, Cache memory and
related mapping and replacement policies,
Virtual memory.
41-45 DMA DMA controller, Secondary storage and type R1 Ch.6
of storage devices, Introduction to buses and
connecting I/O devices to CPU and memory.

Chamber Consultation Hour:

S.No Faculty Name Day Timings


1 Dr. R. Balamurali
2. Dr. Sandeep Kumar Panda

Evaluation Scheme:
Student evaluation is based on the series of tests and quizzes conducted during the course of semester
followed by a comprehensive examination.

Evaluation Syllabus
Duration Weightage Date Remarks
Component (Lec.No.)
Test-1 50 Mins 20% 23/02/2022 1 to 10
Test-2 50 Mins 20% 23/03/2022 10 to 24
10% each
Quizzes 1 & 2 10 Mins -- --
(20%)
Comprehensive
40% -- --
Exam

Make-up Policy: Refer to student Handbook section 6.5 for the Makeup Policy. Prior and
proper information to the concerned instructor is a must and the student should maintain a
minimum attendance.

General: All students are advised to attend classes regularly and strictly maintain an attendance of
75% at least. Students failing to maintain the required percentage of theory/practical attendance will
not be permitted to appear for the tests and examinations.

It is expected that students refrain from using cell phones during lectures and in the labs. The cell
phone must be kept switched off and used only during recess or outside class hours.

Instructor-In-charge
Dr. R. Balamurali

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