Moog BRE440 RADHardCPU Datasheet
Moog BRE440 RADHardCPU Datasheet
The BRE440 Chip represents the culmination of several years of internal development
effort aimed at producing the highest level of space based processing capabilities.
© NASA
BRE440™ RADHARD CPU
SPECIFICATIONS
Features
EXBus EXBus UART UART MAC MAC
High Performance IBM PPC440 Core, 2 MIPS/MHz CTRL CTRL
Timers GPIO
0 1 ETH0 ETH1
ANSI/IEEE 754-1985 compliant FPU
Arbiter
Manufactured on Honeywell 150nm HX5000 Radiation Hardened ASIC Line
OPB
ON-CHIP PERIPHERAL BUS 32-BIT
Superscalar, Dual Issue, 32-bit RISC, Book E Compliant
Memory PPC440
Int
32 kByte L1 Instruction & Data Caches Ctrl 1 CORE
FPU
256 kByte unified L2 Cache (can be configured as general purpose SRAM) Int 32k 32k OPB 2
Ctrl 0 D-cache I-cache PLB DMA
On-Chip 8 kByte SRAM 4 channel
DCW
DCR
ICR
High Bandwidth Main Memory Access with Error Detection and Correction PLB 2
OPB
Interfaces Tag & 256kb
PCI Interface for Peripheral Communication Data L2Cache SRAM
SRAM Control
PCI Arbitration for up to 6 External Peripherals (Clock Distribution)
DCW
DCR
ICR
4 Channel DMA with Scatter/Gather Capability Arbiter
PLB