ECEN720: High-Speed Links

Circuits and Systems

Spring 2021

Lecture 12: CDRs

Sam Palermo
Analog & Mixed-Signal Center
Texas A&M University
Announcements
• Lab 6 due Apr 12
• Project Preliminary Report due Apr 19
• Project Final Report due Apr 29

2
Agenda
• CDR overview
• CDR phase detectors
• Single-loop analog PLL-based CDR
• Dual-loop CDRs
• Phase interpolators
• CDR jitter properties

3
Embedded Clock I/O Circuits
• TX PLL

• TX Clock Distribution

• CDR
• Per-channel PLL-based
• Dual-loop w/ Global PLL &
• Local DLL/PI
• Local Phase-Rotator PLLs
• Global PLL requires RX
clock distribution to
individual channels

4
 Clock and Data Recovery

[Razavi]

• A clock and data recovery system (CDR) produces the clocks to sample
incoming data
• The clock(s) must have an effective frequency equal to the incoming
data rate
• 10GHz for 10Gb/s data rate
• OR, multiple clocks spaced at 100ps
• Additional clocks may be used for phase detection
• Sampling clocks should have the proper phase relationship with the
incoming data for sufficient timing margin to achieve the desired bit-
error-rate (BER)
• CDR should exhibit small effective jitter
5
 Embedded Clocking (CDR)
PLL-based CDR Dual-Loop CDR
VCTRL Frequency 800MHZ
CP PFD Ref Clk
Synthesis
PLL Vctrl
4
PLL[0]

5-stage coupled VCO

PLL[4:0] PLL[4:0]
proportional (3.2GHz)
RX[n:0] gain
5:1 5:1
5 Mux/ MUX MUX 10
integral Interpolator
Din gain
Pairs 15
early/
late early/
RX late sel
FSM
Loop Filter (16Gb/s) PD
Phase-Recovery Loop
• Clock frequency and optimum phase position are extracted from incoming data
• Phase detection continuously running
• Jitter tracking limited by CDR bandwidth
• With technology scaling we can make CDRs with higher bandwidths and the jitter tracking
advantages of source synchronous systems is diminished
• Possible CDR implementations
• Stand-alone PLL
• “Dual-loop” architecture with a PLL or DLL and phase interpolators (PI)
• Phase-rotator PLL
6
Agenda
• CDR overview
• CDR phase detectors
• Single-loop analog PLL-based CDR
• Dual-loop CDRs
• Phase interpolators
• CDR jitter properties

7
CDR Phase Detectors

[Perrott]

• A primary difference between CDRs and PLLs is that the

incoming data signal is not periodic like the incoming
reference clock of a PLL

• A CDR phase detector must operate properly with missing

transition edges in the input data sequence
8
CDR Phase Detectors
• CDR phase detectors compare the phase between the input
data and the recovered clock sampling this data and
provides information to adjust the sampling clocks’ phase
• Phase detectors can be linear or non-linear
• Linear phase detectors provide both sign and magnitude
information regarding the sampling phase error
• Hogge

• Non-linear phase detectors provide only sign information

regarding the sampling phase error
• Alexander or 2x-Oversampled or Bang-Bang
• Oversampling (>2)
• Baud-Rate
9
Hogge Phase Detector
Late

Tb/2
ref

[Razavi]
Late

Tb/2 ref

• Linear phase detector

• With a data transition and assuming a full-rate clock
• The late signal produces a signal whose pulse width is proportional to the
phase difference between the incoming data and the sampling clock
• A Tb/2 reference signal is produced with a Tb/2 delay
• If the clock is sampling early, the late signal will be shorter than Tb/2
and vice-versa
10
 Hogge Phase Detector
Late

Tb/2
ref

[Razavi]
Late

(Late – Tb/2 ref) Tb/2 ref

[Lee] “1” Average Output • For phase transfer 0rad is w.r.t

Amplitude
optimal Tb/2 () spacing between
sampling clock and data
• e = in – clk – 
• TD is the transition density – no
transitions, no information
1 • A value of 0.5 can be assumed for
K PD  TD  random data
“-1” Average
Output Amplitude

11
 PLL-Based CDR with a Hogge PD
[Razavi]

• XOR outputs can directly drive the charge pump

• Need a relatively high-speed charge pump

12
Alexander (2x-Oversampled) Phase Detector
• Most commonly used CDR phase detector
• Non-linear (Binary) “Bang-Bang” PD
• Only provides sign information of phase
error (not magnitude)
• Phase detector uses 2 data samples and
one “edge” sample
• Data transition necessary
En
Dn  Dn 1
• If “edge” sample is same as second
bit (or different from first), then the
clock is sampling “late”
En  Dn En
• If “edge” sample is same as first bit
(or different from second), then the
clock is sampling “early”
En  Dn 1
[Sheikholeslami]
13
Alexander Phase Detector Characteristic
(No Noise)
(Late – Early)

[Lee]

• Phase detector only outputs phase error sign information in

the form of a late OR early pulse whose width doesn’t vary
• Phase detector gain is ideally infinite at zero phase error
• Finite gain will be present with noise, clock jitter, sampler
metastability, ISI
14
Alexander Phase Detector Characteristic
(With Noise)
• Total transfer
characteristic is the
convolution of the ideal
PD transfer characteristic
and the noise PDF
• Noise linearizes the
phase detector over a
phase region
corresponding to the [Lee]
peak-to-peak jitter
2
K PD  TD 
J PP Output
“1” Average
Pulse Width
Output Amplitude
• TD is the transition density –
no transitions, no information
• A value of 0.5 can be
assumed for random data “-1” Average Output
Output Amplitude Pulse Width
15
Mueller-Muller Baud-Rate Phase Detector
“1”
• Baud-rate phase detector
[Musa]
only requires one sample
clock per symbol (bit)

“-1” “-1”
• Mueller-Muller phase
detector commonly used

• Attempting to equalize the

amplitude of samples taken
before and after a pulse

16
 Mueller-Muller Baud-Rate Phase Detector
MM-PD is measuring the effective “1”
[Musa]
ଵ ିଵ
which can be computed by
“-1” “-1”
௞ ௞ିଵ ௞ ௞ାଵ

• If this is positive, then

the effective post-cursor
ISI is too high and we
are sampling too early
• If this is negative, then
the effective pre-cursor
ISI is too high and we
are sampling too late
17
Mueller-Muller Baud-Rate Phase Detector
[Spagna ISSCC 2010]

• Comparing the current sample versus the desired reference

level (en) and correlating that with the appropriate data
sample (dn) gives pre/post-cursor information
• This requires additional error samplers w/ |VREF| thresholds
• en gives dn-1 post-cursor (h1) information
• en-1 give dn pre-cursor (h-1) information
18
Mueller-Muller Baud-Rate Phase Detector
[Spagna ISSCC 2010]

• Simplified MM-PD only

considers transition patterns

• If consecutive error samples

are different, phase error
polarity is given by ej
19
Agenda
• CDR overview
• CDR phase detectors
• Single-loop analog PLL-based CDR
• Dual-loop CDRs
• Phase interpolators
• CDR jitter properties

20
 Analog PLL-based CDR

“Linearized” KPD

[Lee]

21
Analog PLL-based CDR

[Lee]

• CDR “bandwidth” will vary with input phase variation

amplitude with a non-linear phase detector
• Final performance verification should be done with a
time-domain non-linear model
22
56Gb/s PAM4 Analog PLL-based CDR
• Quarter-rate Output

architecture
1-tap FIR, 1-tap
PAM4 Equalizer IIR DFE
+ Z-1

• 3 data samplers
MUX
DFE
DFE DFE
IIR Slicer
FIR IIR
Time

for PAM4
Weight Amp. Thr.
Const.
Input 2-bit Flash ADC
CTLE 3 12
D

detection
+

Error Sampler Adaptation

4 ER
4:8 8:32
Logic
• 1 edge sampler Edge Sampler
4 ED

for CDR and 4 4

DFE adaptation
Divider 14 GHz
and LC-VCO
Buffers

• 1 error sampler
BBPD

for threshold
adaptation [Roshan-Zamir JSSC 2019]

23
56Gb/s PAM4 Analog PLL-based CDR
• PLL-based CDR to In Dn[1:3]
24 PAM4 Early
Loop Filter
BBPD
reduce power



12 Charge
4:8 Late
 En Pump

consumption 
8
4

14 GHz

• Bang-bang phase 4 4
2X Oversampling
LC-VCO

detector works on
Clock Generators
Data I
Phase
symmetric PAM4
CLK CLK0
Calibration 4 I Q
CLK45
CML
VCNT
Divider
transitions to
4 IB
Edge CLK90 Q
CLK QB

minimize detection CML

to

errors
CMOS

• Parallel charge
pumps minimize
logic and loop delay

[Roshan-Zamir JSSC 2019]

24
56Gb/s PAM4 Analog PLL-based CDR
• LC-VCO w/ In Dn[1:3]
24 PAM4 Early
Loop Filter
BBPD
additional source



12 Charge
4:8 Late
 En Pump

LC filter improves 
8
4

phase noise
14 GHz
LC-VCO
2X Oversampling
4 4

• 8-phase quarter-
Clock Generators
Data I
Phase
rate clock
CLK CLK0
Calibration 4 I Q
CLK45
CML
VCNT
IB Divider
• CML divider
4
Edge CLK90 Q
CLK QB

• 2X oversampling CML
to

clock CMOS

[Roshan-Zamir JSSC 2019]

25
Agenda
• CDR overview
• CDR phase detectors
• Single-loop analog PLL-based CDR
• Dual-loop CDRs
• Phase interpolators
• CDR jitter properties

26
Single-Loop CDR Issues
PLL-based CDR
VCTRL

proportional
RX[n:0] gain

integral
Din gain
early/
late
Loop Filter

• Phase detectors have limited frequency acquisition range

• Results in long lock times or not locking at all
• Can potentially lock to harmonics of correct clock frequency
• VCO frequency range variation with process, voltage, and temperature
can exceed PLL lock range if only a phase detector is employed
27
Phase Interpolator (PI) Based CDR
• Frequency synthesis loop
can be a global PLL

• Can be difficult to
distribute multiple phases
long distance
• Need to preserve phase
spacing
• Clock distribution power
increases with phase number
• If CDR needs more than 4
phases consider local phase
generation

28
DLL Local Phase Generation
• Only differential clock is
distributed from global PLL
• Delay-Locked Loop (DLL)
locally generates the
multiple clock phases for
the phase interpolators
• DLL can be per-channel or
shared by a small number (4)
• Same architecture can be
used in a forwarded-clock
system
• Replace frequency synthesis
PLL with forwarded-clock
signals
29
Phase Rotator PLL
• Phase interpolators can be
expensive in terms of power
and area
• Phase rotator PLL places
one interpolator in PLL
feedback to adjust all VCO
output phases
simultaneously
• Now frequency synthesis
and phase recovery loops
are coupled
• Need PLL bandwidth greater
than phase loop
• Useful in filtering VCO noise
30
Agenda
• CDR overview
• CDR phase detectors
• Single-loop analog PLL-based CDR
• Dual-loop CDRs
• Phase interpolators
• CDR jitter properties

31
Phase Interpolators
[Weinlader]
• Phase interpolators realize
digital-to-phase conversion
(DPC)
• Produce an output clock that is
a weighted sum of two input
clock phases
• Common circuit structures
• Tail current summation
interpolation
• Voltage-mode interpolation
• Interpolator code mapping
techniques
• Sinusoidal
[Bulzacchelli]
• Linear
32
Sinusoidal Phase Interpolation

X I  A sin(t )

X Q  A sin(t   / 2)   A cost 

Y  A sin t   
 
 A cos sin t   A sin   cost  0    
 2
 cos X I  sin  X Q  a1 X I  a2 X Q

• Arbitrary phase shift can be Y  A sin t     a1 X 1  a2 X Q

generated with linear where a1  cos  and a2  sin  
summation of I/Q clock signal a12  a22  1

33
Sinusoidal vs Linear Phase Interpolation
[Kreienkamp]

• It can be difficult to generate

a circuit that implements
sinusoidal weighting
a12  a22  1

• In practice, a linear weighting

is often used
a1  a2  1
34
Phase Interpolator Model
[Weinlader]

w/ ideal step inputs (worst case)

small output 

• Interpolation linearity is a function

of the phase spacing, t, to
output time constant, RC, ratio
large output 
• Important that interpolator output
time constant is not too small
(fast) for phase mixing quality
35
 Phase Interpolator Model
w/ ideal step inputs w/ finite input Spice simulation
transition time

w/ ideal step inputs:

w/ finite input transition time:

For more details see D. Weinlader’s Stanford PhD thesis

36
Tail-Current Summation PI
[Bulzacchelli
JSSC 2006]

• Control of I/Q polarity allows for full 360 phase rotation

with phase step determined by resolution of weighting DAC
• For linearity over a wide frequency range, important to
control either input or output time constant (slew rate)
37
 Voltage-Mode Summation PI
[Joshi VLSI Symp 2009]

• For linearity over a wide frequency range, important to

control either input or output time constant (slew rate)
38
Delay-Locked Loop (DLL)

[Sidiropoulos JSSC 1997]

• DLLs lock delay of a voltage-controlled delay line (VCDL)

• Typically lock the delay to 1 or ½ input clock cycles
• If locking to ½ clock cycle the DLL is sensitive to clock duty cycle
• DLL does not self-generate the output clock, only delays
the input clock
39
 Voltage-Controlled Delay Line

KDL

[Sidiropoulos]

40
DLL Delay Transfer Function
[Maneatis]

• First-order loop as delay line doesn’t introduce a (low-frequency) pole

• The delay between reference and feedback signal is low-pass filtered
• Unconditionally stable as long as continuous-time approximation holds,
i.e. n<ref/10

41
Agenda
• CDR overview
• CDR phase detectors
• Single-loop analog PLL-based CDR
• Dual-loop CDRs
• Phase interpolators
• CDR jitter properties
• Jitter transfer
• Jitter generation
• Jitter tolerance
42
 CDR Jitter Model

“Linearized” KPD

[Lee]

43
 Jitter Transfer

“Linearized” KPD

[Lee]

• Jitter transfer is how much input jitter “transfers” to the output

• If the PLL has any peaking in the phase transfer function, this jitter can
actually be amplified

44
Jitter Transfer Measurement

System Clean Clock

recovered
clock

System input clock with sinusoidal Sinusoidal Sinusoidal input

phase modulation (jitter) output voltage voltage for phase
mod.

[Walker]
45
 Jitter Transfer Specification

[Walker]

46
Jitter Generation
[Mansuri]

• Jitter generation is how much jitter the CDR “generates”

• Assumed to be dominated by VCO
• Assumes jitter-free serial data input
out s2 s2
VCO Phase Noise: H n s    
VCO
n  K Loop  K Loop s 2  2 n s  n2
VCO 2
s    RCs 
 N  N
For CDR, N should be 1
47
 Jitter Generation
Jitter accumulates up to time 
High-Pass Transfer Function
1/PLL bandwidth

out(s)
20log 10
vcon(s)

[McNeill]
• SONET specification:
• rms output jitter ≤ 0.01 UI
48
Jitter Tolerance
• How much sinusoidal jitter can the CDR “tolerate” and still achieve a
given BER? [Sheikholeslami]

[Lee]
Maximum tolerable e
 out s   Timing Margin
 e s    1 
 n.in s  

 in  s   2

TM
JTOLs   2n.in s  
 out s  
1  
 in s  

49
Jitter Tolerance Measurement

[Lee]

• Random and sinusoidal jitter are added by modulating the BERT clock
• Deterministic jitter is added by passing the data through the channel
• For a given frequency, sinusoidal jitter amplitude is increased until the
minimum acceptable BER (10-12) is recorded
50
Jitter Tolerance Measurement
[Lee]

(within CDR
bandwidth)

TM
JTOLs   2n.in s  
Flat region is beyond  out s  
1  
CDR bandwidth  in s  

51
CDR Take-Away Points
• CDRs extract the proper clock frequency and phase
position to sample the incoming data symbols
• Specialized phase detectors suited for random data
symbols are required
• Dual-loop CDRs are often used to both optimize
jitter performance and provide robust frequency
acquisition
• Jitter tolerance is an important CDR metric that is
improved with increased loop bandwidth

52
Next Time
• Forwarded-Clock Deskew Circuits
• Clock Distribution Techniques

53