APW8700

Dual-Phase Synchronous-Rectifier Buck Controller

Features General Description

• Voltage-Mode Operation with Current Sharing The APW8700, two-phase PWM control IC, provides a
precision voltage regulation system for advanced graphic
• Operate with 4.5V~13.2V Supply Voltage
card and motherboard applications. The integration of
• Support Single and Two-Phase Operations
power MOSFET drivers into the controller IC and reduces
• +2% Reference Voltage Accuracy Over
the number of external parts for a cost and space saving
Temperature
power management solution.
• Loss-Less Inductor DCR Current Sensing The APW8700 uses a voltage-mode PWM architecture,
• Adjustable Over Current Protection use DCR operating with adjust frequency from 100kHz to 800kHz.
Current Sensing The device uses the voltage across the DCRs of the in-
• Programmable PWM Switching Frequency from ductors for current sensing achieves high efficiency. The
100kHz to 800kHz device integrates adjustable load line voltage position-
• Dynamic Output Voltage Adjustment ing (droop) and adopts low side RDS_ON for channel-cur-
• Adjustable Soft-start rent balance.
The automatic phase reduction and over-current protec-
• QFN4x4-24 Package
tion are accomplished through continuous inductor DCRs
• Halogen and Lead Free Available (RoHS Compliant)
current sensing.
The APW8700 also implement a one-bit VID control op-
Simplified Application Circuit eration in which the feedback voltage is regulated and
tracks external input reference voltage.
This controller protection features include over-
VIN
temperature(OTP), over-voltage(OVP), under-voltage
SS
UGATE1
(UVP) and over-current protections (OCP).
RT/EN VOUT
OFF The device also provides a power-on-reset function and
ON
PSI
a programmable soft-start to prevent wrong operation and
LGATE1
VREF limit the input surge current during power-on or start-up.
REFIN The APW8700 is available in QFN4x4-24 packages.
UGATE2
COMP

FB
LGATE2
Applications
• VGA
• Mother Board

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.

Copyright  ANPEC Electronics Corp. 1 www.anpec.com.tw

Rev. A.1 - Jun., 2011
APW8700

Ordering and Marking Information

APW8700 Package Code
QA : QFN4x4-24
Assembly Material Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code Handling Code
Temperature Range TR : Tape & Reel
Assembly Material
Package Code G : Halogen and Lead Free Device

APW8700 QA : APW8700 XXXXX - Date Code

XXXXX

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).

Pin Configuration
APW8700
UGATE2
PHASE2
LGATE2
BOOT2
RSET
VID

24 23 22 21 20 19

REFIN 1 18 VCC
VREF 2 17 PVCC
RT/EN 3 16 LGATE1
IOFS 4 15 PHASE1
(Exposed Pad)
COMP 5 GND 14 UGATE1
FB 6 13 BOOT1
7 8 9 10 11 12
EAP
SS
CSN
CSP
PSI
AGND

QFN4x4-24
Top View

Absolute Maximum Ratings (Note 1)

Symbol Parameter Rating Unit
VVCC Input Supply Voltage (VVCC to GND) -0.3 ~ 16 V
VPVCC Gate Driver Supply Voltage (VPVCC to GND) -0.3 ~ VVCC+1 V
BOOT1/2 to PHASE1/2 Voltage -0.3 ~ 16 V
BOOT1/2 to GND Voltage -0.3 ~ 30 V
> 200ns -0.3 ~ VBOOT1/2+0.3 V
UGATE1/2 to PHASE1/2 Voltage
< 200ns -5 ~ VBOOT1/2+5 V
> 200ns -0.3 ~ VVCC+0.3 V
VLGATE1/2 LGATE1/2 to GND Voltage
< 200ns -5 ~ VVCC+5 V
> 200ns -0.3 ~ 16 V
VPHASE1/2 PHASE1/2 to GND Voltage
< 200ns -10 ~ 30 V
REFIN, VREF, RT/EN, IOFS, COMP, FB, EAP, SS, CSP, CSN, PSI, VID,
-0.3 ~ 7 V
RSET to AGND Voltage
AGND to GND -0.3 +0.3 V
PD Power Dissipation 2.5 W

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Rev. A.1 - Jun., 2011
APW8700

Absolute Maximum Ratings (Cont.) (Note 1)

Symbol Parameter Rating Unit
o
TJ Maximum Junction Temperature 150 C
o
TSTG Storage Temperature -65 ~ 150 C
o
TSDR Maximum Lead Soldering Temperature (10 Seconds) 260 C

Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom-
mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability

Thermal Characteristics
Symbol Parameter Typical Value Unit

θJA Junction-to-Ambient Resistance in free air (Note 2) o

QFN4x4-24 41 C/W

θJC
o
Junction-to-Case Resistance QFN4x4-24 9 C/W

Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.

Recommended Operating Conditions (Note 3)

Symbol Parameter Range Unit
VVCC VCC Supply Voltage (VVCC to GND) 4.5 ~ 13.2 V
VOUT VOUT to GND 0.6 ~ 5.5 V
VIN Converter Input Voltage 2 ~ 13.2 V
FOSC Oscillator Frequency 100 ~ 800 kHz
IOUT Converter Output Current 0 ~ 60 A
o
TA Ambient Temperature -40 ~ 85 C
o
TJ Junction Temperature -40 ~ 125 C
Note 3: Refer to the application circuit for further information.

Electrical Characteristics
Refer to figure 1 in the “Typical Application Circuits”. These specifications apply over VVCC = 12V, TA= 25oC, unless otherwise noted.

APW8700
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
SUPPLY CURRENT
VCC Supply Voltage Range 4.5 - 13.2 V
IDD_SD No switching, RT/EN=GND - 4 5 mA
Input DC Bias Current
IDD UGATE1/2, LGATE1/2 open, switching - 5 7 mA
VPVCC Regulated Supply Voltage RT/EN=GND, IPVCC=0mA 8 9 10 V
POR Threshold of VCC 3.8 4.1 4.4 V
POR Hysteresis 0.3 0.5 0.6 V
POR Threshold of PVCC 3.8 4.1 4.4 V
POR Hysteresis 0.3 0.5 0.6 V

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Rev. A.1 - Jun., 2011
APW8700

Electrical Characteristics (Cont.)

Refer to figure 1 in the “Typical Application Circuits”. These specifications apply over VVCC = 12V, TA= 25oC, unless otherwise noted.

APW8700
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
CHIP ENABLE/FREQUENCY SETTING
IRT/EN RT/EN Source Current RT/EN=GND - - 120 µA
RT/EN Shutdown Threshold 0.45 0.5 0.55 V
Enable Debounce time RT/EN high debounce - 200 - µs
VRT/EN RT/EN Voltage RRT/ENB=33kΩ - 1 - V
Switching Frequency Setting Range 100 - 800 kHz
FOSC Free Run Switching Frequency RRT/EN=33kΩ 255 300 345 kHz
ΔFOSC Switching Frequency Accuracy FOSC=200kHz~500kHz -15 - 15 %
SOFT-START
ISS Soft-start Current During Soft-start - 20 - µA
SS Source/Sink Current Capability After Soft-start - 200 - µA
OSCILLATOR
Maximum Duty Cycle - 85 - %
Minmum Duty Cycle - 0 - %
ΔVOSC Ramp Amplitude VVCC=12V - 1.5 - V
POWER SAVING MODE
Threshold Voltage to Enter Dual
VPSI VPSI Rising 0.55 0.6 0.65 V
Phase
ΔVPSI Hysteresis to Enter Single Phase VPSI Falling - 0.2 - V
2 Phase to single phase debounce Continuously - 0.2 - ms
REFERENCE VOLTAGE
VREF Reference Voltage Accuracy IREF=100µA, TJ= -20oC ~ 70oC 1.98 2.00 2.02 V
VREF Maximum Output Current VREF=GND 20 - - mA
ΔVREF Reference Voltage Load Regulation IREF=0~2mA -5 - 5 mV
VREFIN-VFB, VREFIN=0.8V~2V,
-5 - 5 mV
VFB Output Voltage Accuracy RDRP=0Ω
VFB operating range 0.2 - VREF V
ERROR AMPLIFIER
Open-Loop DC Gain (Note 4) RL = 10kΩ, CL =10pF - 80 - V/V
(Note 4)
Open-Loop Bandwidth RL = 10kΩ, CL =10pF - 20 - MHz
Slew Rate (Note 4) RL = 10kΩ, CL =10pF - 8 - V/µs
FB Input Leakage Current VFB=1V - 0.1 0.5 µA
COMP High Voltage RL = 10kΩ, CL =10pF - 4.8 - V/µs
VCOMP
COMP Low Voltage RL = 10kΩ, CL =10pF - 0.2 - µA
Maximum COMP Source Current VCOMP=2V - 2 - mA
ICOMP
Maximum COMP Sink Current VCOMP=2V - 2 - mA

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Rev. A.1 - Jun., 2011
APW8700

Electrical Characteristics (Cont.)

Refer to figure 1 in the “Typical Application Circuits”. These specifications apply over VVCC = 12V, TA= 25oC, unless otherwise noted.

APW8700
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
TOTAL CURRENT SENSE
ICSN_MAX Maximum Sourcing Current 100 - - µA
GM Amplifier Offset -5 - 5 mV
Over-Current Protection Threshold
ICSN_OCP 55 60 65 µA
Level
Droop Accuracy IDRP/ICSN 90 100 110 %
PSI Accuracy IPSI/ICSN 90 100 110 %
PHASE CURRENT SENSE
gm Trans-conductance - 1.0 - mA/V
100kΩ from IOFS to VREF 1.425 1.5 1.575 V
VIOFS IOFS Voltage
100kΩ from IOFS to GND 0.475 0.5 0.525 V
VID CONTROL INPUT
VIH Logic High Threshold Level 1.2 - - V
VIL Logic Low Threshold Level - - 0.4 V
RRSET On Resistance of RSET MOSFET VID=High - 20 - Ω
IRSET Leakage Current of RSET Pin VRSET=2V, VID=GND - - 0.1 µA
Gate Driver
RUG_SRC Upper Side Gate Sourcing IUGATE=100mA Sourcing - 2 4 Ω
RUG_SNK Upper Side Gate Sinking IUGATE=100mA Sinking - 1.5 3 Ω
RLG_SRC Low Side Gate Sourcing ILGATE=100mA Sourcing - 2 4 Ω
RLG_SNK Low Side Gate Sinking ILGATE=100mA Sinking - 1 2 Ω
TDT Dead-time - 30 - ns
PROTECTION
Over Voltage Protection (OVP) VFB/VEAP 125 130 135 %
Over Voltage Hysteresis - 20 - %
Under Voltage Protection (UVP) VFB/VEAP 45 50 55 %
Over Current Protection (OCP) ICSN 55 60 65 µA
ο
Over Temperature Protection (OTP) - 150 - C
ο
Over Temperature Hysteresis - 20 - C
Note 4: Guarantee by design, not production test

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Rev. A.1 - Jun., 2011
APW8700

Pin Description
PIN NAME FUNCTION
External Reference Input. This is input pin of external reference voltage. Connect a voltage
1 REFIN
divider from VREF to REFIN to AGND to set the reference voltage.
Reference Voltage Output. This is the output pin of high precision 2V reference voltage. Bypass
2 VREF
this pin with a 1µF ceramic capacitor to AGND.
Operation Frequency Setting. Connecting a resistor between this pin and AGND to set the
3 RT/EN
operation frequency. Pull this pin to ground to shut down the APW8700.
Current Balance Adjustment. Connect a resistor from this pin to VREF or GND to adjust the
4 IOFS
current sharing.
Error Amplifier Output. Use this pin in combination with the FB pin to compensate the
5 COMP
voltage-control feedback loop of the converter.
Feedback Voltage. This pin is the inverting input to the error amplifier. Use this pin in combination
6 FB
with the COMP pin to compensate the voltage control feedback loop of the converter.
7 AGND Analog Ground. Connect this pin to the GND pin where the output voltage is to be regulated.
8 EAP Non-Inverting Input of Error Amplifier. Connect a resistor to SS pin to set the droop slope.
9 SS Soft Start Output. Connect a capacitor to GND to set the soft start interval.
10 CSN Inverting Input of Current Sensing Amplifier.
11 CSP Non-Inverting Input of Current Sensing Amplifier.
Power Saving Indicator. Connect a resistor from PSI to AGND to set the power saving mode
12 PSI threshold current level. Connect this pin to VREF for always two phases operation. Short this pin
to ground for always single-phase operation. Don’t left this pin floating.
Bootstrap Supply for the floating high-side gate driver of channel 1. Connect the Bootstrap
capacitor between the BOOT1 pin and the PHASE1 pin to form a bootstrap circuit. The bootstrap
13 BOOT1
capacitor provides the charge to turn on the high-side MOSFET. Typical values for CBOOT
range from 0.1µF to 1µF.Ensure that CBOOT is placed near the IC.
Upper Gate Driver Output for channel 1. Connect this pin to the gate of high-side MOSFET. This
14 UGATE1 pin is monitored by the adaptive shoot-through protection circuitry to determine when the
high-side MOSFET has turned off.
Switch Node for Channel 1. Connect this pin to the source of high-side MOSFET and the drain of
the low-side MOSFET. This pin is used as sink for UGATE1 driver. This pin is also monitored by
15 PHASE1
the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has
turned off.
Low-side Gate Driver Output for Channel 1. Connect this pin to the gate of low-side MOSFET.
16 LGATE1 This pin is monitored by the adaptive shoot-through protection circuitry to determine when the
low-side MOSFET has turned off.
Supply Voltage for Gate Driver. This pin is the output of internal 9V LDO. It provides current for
17 PVCC gate drives. Bypass this pin with a minimum 1µF ceramic capacitor. If VCC below 7V, connect
this pin to VCC is recommended.
Supply Voltage. This pin provides current for internal control circuit and 9V LDO. Bypass this pin
18 VCC
with a minimum 1µF ceramic capacitor next to the IC.
Low-side Gate Driver Output for Channel 2. Connect this pin to the gate of low-side MOSFET.
19 LGATE2 This pin is monitored by the adaptive shoot-through protection circuitry to determine when the
low-side MOSFET has turned off.
Switch Node for Channel 2. Connect this pin to the source of high-side MOSFET and the drain of
the low-side MOSFET. This pin is used as sink for UGATE2 driver. This pin is also monitored by
20 PHASE2
the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has
turned off.
Upper Gate Driver Output for channel 2. Connect this pin to the gate of high-side MOSFET. This
21 UGATE2 pin is monitored by the adaptive shoot-through protection circuitry to determine when the
high-side MOSFET has turned off.

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Rev. A.1 - Jun., 2011
APW8700

Pin Description(Cont.)
PIN NAME FUNCTION
Bootstrap Supply for the floating high-side gate driver of channel 2. Connect the Bootstrap
capacitor between the BOOT2 pin and the PHASE2 pin to form a bootstrap circuit. The bootstrap
22 BOOT2
capacitor provides the charge to turn on the high-side MOSFET. Typical values for CBOOT
range from 0.1µF to 1µF.Ensure that CBOOT is placed near the IC.
VID Input. This pin is used to adjust reference voltage. Logic high turns on the internal MOSFET
23 VID
connected to RSET pin.
Reference Voltage Setting. This pin is an open drain output that is pulled low when VID = high.
24 RSET
Connect a resistor from this pin to REFIN pin to set the reference voltage.
Power Ground. Tie this pad to the ground island/plane through the lowest impedance connection
Exposed Pad GND
available.

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Rev. A.1 - Jun., 2011
APW8700

Typical Operating Characteristics

Refer to the “Typical Application Circuits”, VIN=12V, VOUT=1.05V, TA=25oC unless otherwise specified
Reference Voltage vs. Supply Reference Voltage vs. Junction
Voltage Temperature
2.05 2.020
2.04 2.015
Reference Voltage, VREF(V)

Reference Voltage, VREF(V)

2.03
2.010
2.02
2.01 2.005

2 2.000
1.99 1.995
1.98
1.990
1.97
1.985
1.96
1.95 1.980
4 5 6 7 8 9 10 11 12 13 14 -40 -20 0 20 40 60 80 100 120 140 160
Supply Voltage, VVCC (V) Junction Temperature, TJ(oC)

UGATE Driver On Resistance vs. LGATE Driver On Resistance vs.

PVCC Voltage Supply Voltage
5.0 5.0

4.5 4.5
UGATE Driver On Resistance (Ω)

LGATE Driver On Resistance (Ω)

4.0 4.0
UGATE Source 3.5
3.5
3.0 3.0
LGATE Source
2.5 2.5

2.0 2.0

1.5 1.5

1.0 1.0
UGATE Sink
0.5 0.5 LGATE Sink

0.0 0.0
4 5 6 7 8 9 4 5 6 7 8 9 10 11 12

PVCC Voltage, VPVCC (V) Supply Voltage, VVCC (V)

PVCC Voltage vs. Supply Voltage

10
9
8
PVCC Voltage, VPVCC(V)

7
6
5
4
3
2
1 IPVCC = 10mA

0
4 5 6 7 8 9 10 11 12 13 14
Supply Voltage, VVCC (V)

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Rev. A.1 - Jun., 2011
APW8700

Operating Waveforms

Enable Shutdown

VRT , 1 V/Div, DC
VRT , 1V/Div, DC
1 1
VPHASE 1, 10V/Div, DC
2 2
VPHASE 1, 10V/Div, DC

VSS, 0 .5V /Div, DC

VSS , 0.5V/Div, DC

3 3

VOUT , 0.5V/Div, DC VOUT , 0 .5V /Div, DC

4 4

Time: 500µs/Div Time: 500µs/Div

Power ON Power OFF

VRT , 1 V/Div, DC VRT, 1V/Div, DC

1 1
VPHASE1, 5V/Div, DC

2 2
V PHASE1 , 5V/Div, DC
VSS , 0.5V/Div, DC VSS, 0.5V/Div, DC

3 3

VOUT, 0.5V/Div, DC
VOUT , 0.5V/Div, DC

4 4

Time: 500µs/Div Time: 50µs/Div

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Rev. A.1 - Jun., 2011
APW8700

Operating Waveforms

PSI OVP

VPSI, 1V/Div, DC
1 VFB, 1V/Div, DC

VPHASE1, 10V/Div, DC 1

2
VUGATE1, 10V/Div, DC
VPHASE2, 10V/Div, DC 2

3 3 VLGATE1, 10V/Div, DC

Time: 50µs/Div Time: 10µs/Div

OCP
V SS, 1V/Div, DC

1
VOUT , 1 V/Div, DC

I L1 +I L2 , 20A/Div, DC
3+4
I L1, 10A/Div, DC
3
I L2, 10A/Div, DC
4

Time: 20µs/Div

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Rev. A.1 - Jun., 2011
APW8700

Block Diagram

VCC

Internal Power Internal

VREF Regulator On Regulator PVCC
1 Reset 2

RSET IOFS

VID
Current
Balance
AGND Current Gm
Limit Amplifier
REFIN Buffer CSP
CSN
SS
Error Over
EAP Amplifier Current
Protection GND
FB
COMP
Power
IDRP Saving PSI
Setting

PVCC
PVCC

BOOT1 BOOT2

Logic Logic
UGATE1 Control Control
UGATE2

VOSC1 VOSC2
PHASE1 PHASE2
Oscillator
VCC VCC
Enable

LGATE1 LGATE2

1V

0.5V

RT/EN

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Rev. A.1 - Jun., 2011
APW8700

Typical Application Circuit

VREF

(option)
(option)
VREF IOFS
(option)
PHASE2
1k 1µF
CSP PHASE1
REFIN 10k
0.1µF NC
1k 8.1k 3k
CSN VOUT
RSET
VID PVCC
AGND 1µF
VCC
1µF
SS
47nF
GND VIN =12V
0 BOOT1
0.1µF
EAP 10µFx2 270µFx2
UGATE1
OFF RT/EN VOUT
33k APM3109
ON 40k PHASE1
PSI 0.8µH
2N7002 LGATE1 APM3106 820µFx3

10nF
BOOT2 10µFx2
COMP 0.1µF
10µFx2
0.27k 220nF UGATE2
FB
APM3109
PHASE2
100nF 0.8µH

680 LGATE2 APM3106

12R

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Rev. A.1 - Jun., 2011
APW8700

Function Description
VCC Power-On-Reset (POR)
dV SS I SS 20 µ A
The Power-On-Reset (POR) circuit compares the input = = During soft-start
dt C SS C SS
voltage at VCC with the POR threshold (4.1V rising, typical)
to ensure the input voltage is high enough for reliable dV SS ISS 200 µ A
= = After soft-start
operation. The 0.5V (typ) hysteresis prevents supply tran- dt C SS C SS
sients from causing a restart. Once the input voltage ex-
Figure 2 shows the simplified voltage control loop of
ceeds the POR rising threshold, startup begins. When
APW8700. VREF is a reference voltage output with 1%
the input voltage falls below the POR falling threshold,
accuracy and up to 20mA sourcing capability. RSET is an
the controller turns off the converter.
open drain output that is controlled by VID pin. RSET is

VREF pulled to FBRTN when VID = 1 and is set high imped-

ance when VID = 0.
This is the output pin of high precision 2V reference
voltage. Bypass this pin with a 1µF ceramic capacitor to
R2
AGND. The VREF have capability to drive 20mA output V SS = V REF × VID=0
R1 + R 2
current.
R2 // R3
VCC VSS = VREF × VID=1
R1+ (R2 // R3)
POR UVLO

PVCC

VREF

R1
REF REFIN

RT/EN R2
R3
SS=EAP RSET

VID
VID

Figure 1. Power on/off sequence AGND

CSS
SS Current
Limit
Soft-start
Buffer
RDRP
After the VCC voltage exceeds the POR voltage threshold
EAP Error
VOUT Amplifier
and the RT/EN voltage exceeds 0.5V, the device initials a
start-up process and then ramps up the output voltage to FB
the setting of output voltage. A 20µA current source starts IDRP
to charge the capacitor (CSS ) connected with SS and
AGND pins. Connect error amplifier non-inverting input,
EAP, to SS. The VFB starts to rise with the same rate as COMP
the soft-start voltage. Once the SS voltage reaches 80%
of VREFIN, the soft-start process is completed after 3ms.
After the soft-start process is completed, the SS could Figure 2. Simplified voltage control loop
source/sink 200µA.

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Rev. A.1 - Jun., 2011
APW8700

Function Description (Cont.)

Shutdown Control and Frequency Setting The differential current of the current balance control cir-
RT/EN is a multi function pin. Pull RT/EN below 0.5V to cuit (ISEN1-ISEN2) is used to fine-tune the COMP1/2 voltage.
shuts down the device. Connecting a resistor between The VCOMP1 and VCOMP2 will increase or decrease because
this pin and GND to set the operation frequency. The op- of these two currents. For example, when ISEN1>ISEN2, the
eration frequency range could be set from 100kHz to VCOMP1 will decrease and the VCOMP2 will increase. Therefore,
800kHz. In shutdown mode, the UGATEx and LGATEx are the duty of PWM1 will decrease and the duty of PWM2 will
pulled to PHASEx and GND respectively. When the pull- increase. Then, the device will reduce IL1 current and in-
down device is released, the APW8700 initiate a soft- crease IL2 current for current sharing, vice verse.
start process.

Rx
The switching frequency, FOSC, could be calculated as:
PHASE1 COMP
10000
F OSC = ( kHz )
R RT ( k Ω ) ISEN1
ISEN1- ISEN2 COMP1
Sample Current
VOFFSET ISEN2 & Hold Balance
Rx IOFS COMP2
1000
IOFS
PHASE2

IOFS
VOFFSET
Switching Frequency(kHz)

Figure 4. Current balance scheme

Current Sense

Below shows the circuit of sensing inductor current. Con-

necting a series resistor (RS) and a capacitor (CS) net-
work in parallel with the inductor and measuring the volt-
age (VC) across the capacitor can sense the inductor
100 current.
10 100
RRT(kΩ)
L1 DCR1
Figure 3. Switching Frequency vs. RT resistance PHASE1 VOUT

Current Balancer
RS CS
The APW8700 adopts parasitic on-resistance of the lower EAP + VC -
switches current balance as show in figure 4. When the CSP

lower switches turn on, the GM amplifier senses the volt- RCSN
age drop across the lower switches and converts it into CSN
IDRP ICSN
current signal each time it turns on. The sampled and
held current is expressed as:
IPSI PSI
IL X ⋅ RDS ( ON ) V OFFSET
ISENx = +
RX RX Figure 5. DCR current sense scheme

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Rev. A.1 - Jun., 2011
APW8700

Function Description (Cont.)

The equations of the sensing network are: Automatic Phase Reduction
The APW8700 implements automatic phase reduction
VL1(s) = IL1(s) × (sL1 + DCR1) that turns off phase 2 at light load condition and reduces
both switching and conduction losses. The automatic
1 IL1(s) × ( sL1 + DCR1)
VC(s) = VL1(s) × = phase reduction maintains high power conversion effi-
1 + sRSCS 1 + sRSCS
ciency over the output current range. The output current is
Take sensed and mirrored to PSI pin as:
L1
RSCS =
DCR1 IOUT × DCR1
IPSI = ICSN =
2 × RCSN
If the above is true, the voltage across the capacitor CS
equal to voltage drop across the inductor DCR1, and the
The IPSI creates a voltage VPSI as:
voltage VC is proportional to the inductor current IL1.

VC = DCR1× IL1 IOUT × DCR1× RPSI

VPSI = RPSI × IPSI =
2 × RCSN
VC IL1 × DCR1
ICSN = =
RCSN RCSN The APW8700 operates at dual phase if VPSI exceeds
0.6V and at single phase at VPSI below 0.4V. There is a
200mV hystersis at the phase change threshold. There
where is a 0.2ms delay when entering single phase operation
IL1 is the inductor current of phase 1
and no time delay when entering dual phase operation.
DCR1 is the inductor resistance of phase 1
When operating single phase, both UGATE2 and LGATE2
Due to the APW8700 implement current balance circuit. are turned off.
At two phase operation, the IL1 equal half of output current,
IOUT. Droop Setting
IOUT × DCR1
ICSN = In some high current applications, a requirement on pre-
2 × RCSN cisely controlled output impedance is imposed. This de-
pendence of output voltage on load current is often termed
Over Current Protection (OCP)
droop regulation. As shown in figure 4, the droop control
The APW8700 feature an over current protection adopt block generates a voltage through external resistor RDRP
current sensing. When I CSN exceed 60µA at operation, the and then set the droop voltage. The droop voltage, VDRP,
over current occurs. In over-current protection, the IC shuts is proportional to the total current in two channels. As
off the converter. The ICSN can be describe as: shown in the following equation:

V FB = V SS − IDRP × R DRP
VC IOUT × DCR1
ICSN = =
RCSN 2 × RCSN where
IDRP is the droop current that mirrored from ICSN.
The APW8700 initial a soft-start process until recycle POR The output voltage also can be describe as:
or EN/RT.
IOUT × DCR 1× R DRP
V FB = V SS − IDRP × RDRP = V SS −
2 × RCSN

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Rev. A.1 - Jun., 2011
APW8700

Function Description (Cont.)

Offset Current Adjust UVP

The APW8700 integrated IOFS allows the offset current The under-voltage protection circuit monitors the voltage
to adjust phase current. The IOFS pin voltage is nominal on FB (VFB) by Under-Voltage (UV) comparator to protect
0.5V when connecting a resistor to GND and 1.5V when the PWM converter against short-circuit conditions. When
connecting a resistor to VREF. Connecting a resistor from the VFB falls below the falling UVP threshold (50% VEAP), a
IOFS pin to GND generate a current source as: fault signal is generated and the device turns off high-
IOFS= 0.5V/RIOFS side and low-side MOSFETs. The converter shuts down
This current is add to phase 1 current signal ISEN1 for cur- and the output is latched to be floating. The APW8700 will
rent balance. Consequently, phase 2 will share more initials a soft-start process until re-cycle RT/EN or VCC
percentage of output current. Connecting a resistor from
IOFS pin to VREF generates a current source as:
IOFS= (2V-1.5V) /RIOFS
This current is add to phase 2 current signal ISEN2 for cur-
rent balance. Consequently, phase 1 will share more
percentage of output current.

Over-Temperature Protection (OTP)

The over-temperature circuit limits the junction tempera-

ture of the APW8700. When the junction temperature ex-
o
ceeds 150 C, a thermal sensor pulls UGTAEx and LGATEx
low, allowing the devices to cool. The thermal sensor
allows the converters to start a soft-start process and
regulates the output voltage again after the junction tem-
o o
perature cools by 20 C. The OTP is designed with a 20 C
hysteresis to lower the average Junction Temperature
(TJ) during continuous thermal overload conditions in-
creasing the lifetime of the device.

OVP

The over-voltage protection (OVP) circuit monitors the FB

(VFB) voltage to prevent the output from over-voltage. When
the V FB rises to 130% of the EAP voltage (V EAP ), the
APW 8700 turns off high-side and turn on low-side
MOSFETs to sink output voltage (VOUT). As soon as the VFB
falls below 110% of V EAP , the OVP comparator is
disengaged. The chip will restore its normal operation.

Copyright  ANPEC Electronics Corp. 16 www.anpec.com.tw

Rev. A.1 - Jun., 2011
APW8700

Application Information
PWM Compensation
The output LC filter of a step down converter introduces a The PWM modulator is shown in figure 8. The input is the
double pole, which contributes with -40dB/decade gain output of the error amplifier and the output is the PHASE
slope and 180 degrees phase shift in the control loop. A node. The transfer function of the PWM modulator is given
compensation network among COMP, FB, and V OUT by :
should be added. The compensation network is shown VIN
GAINPWM =
in Figure 9. The output LC filters consists of the ∆VOSC
VIN
output inductors and output capacitors. For two-phase
convertor, when assuming VIN1=VIN2=VIN, L1=L2=L, the Driver
transfer function of the LC filter is given by: OSC PWM
Comparator
1 + s × ESR × COUT
GAINLC = PHASE
1 ∆VOSC
s2 × L × COUT + s × ESR × COUT + 1
2
Output of Error
The poles and zero of this transfer functions are: Amplifier
1 Driver
FLC =
1
2× π× L × COUT Figure 8. The PWM Modulator
2
1 The compensation network is shown in figure 9. It pro-
FESR =
2 × π × ESR × COUT vides a close loop transfer function with the highest zero
The FLC is the double-pole frequency of the two-phase LC crossover frequency and sufficient phase margin.
filters, and FESR is the frequency of the zero introduced by
The transfer function of error amplifier is given by :
the ESR of the output capacitors.
1  1 
V PHASE1 L1=L V OUT // R2 + 
VCOMP sC1  sC2 
GAINAMP = =
L2=L VOUT  1 
R1//  R3 + 
COUT  sC3 
V PHASE2
 1   1 
s + ×s + 
ESR
=
R1 + R3
×
 R2 × C2   (R1 + R3) × C3 
R1× R3 × C1  C1 + C2   1 
s s + × s + 
 R2 × C1× C2   R3 × C3 
Figure 6. The Output LC Filter

FLC The pole and zero frequencies of the transfer function

are: 1
-40dB/dec FZ1 =
2 × π × R2 × C2
1
FZ2 =
2 × π × (R1+ R3) × C3
GAIN (dB)

1
FP1 =
FESR
 C1× C2 
2 × π × R2 ×  
 C1 + C2 
-20dB/dec 1
FP2 =
2 × π × R3 × C3

Frequency(Hz)
Figure 7. Frequency Resopnse of the LC filters

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Rev. A.1 - Jun., 2011
APW8700

Application Information (Cont.)

PWM Compensation (Cont.) 5. Set the second pole FP2 at the half of the switching
frequency and also set the second zero FZ2 at the output LC
C1 filter double pole FLC. The compensation gain should not
exceed the error amplifier open loop gain, check the
R3 C3 R2 C2
compensation gain at FP2 with the capabilities of the
VOUT error amplifier.
FP2 = 0.5 X FSW
FB VCOMP
R1
FZ2 = FLC
VREF
Combine the two equations will get the following
component calculations:
Figure 9. Compensation Network
R1
The closed loop gain of the converter can be written as: R3 =
FSW
−1
GAINLC X GAINPWM X GAINAMP 2 × FLC

Figure 10. shows the asymptotic plot of the closed loop 1

C3 =
converter gain, and the following guidelines will help to π × R3 × FSW
design the compensation network. Using the below
guidelines should give a compensation similar to the
curve plotted. A stable closed loop has a -20dB/ decade FZ1 FZ2 FP1 FP2
slope and a phase margin greater than 45 degree.
1. Choose a value for R1, usually between 1K and 5K.
GAIN (dB)

Compensation Gain
2. Select the desired zero crossover frequency 20log
(R2/R1)
FO= (1/5 ~ 1/10) X FSW 20log
(VIN/ΔVOSC)
Use the following equation to calculate R2:
∆VOSC FO
R2 = × × R1
VIN FLC
FLC

3. Place the first zero FZ1 before the output LC filter double FESR
Converter Gain
pole frequency FLC.
PWM & Filter Gain
FZ1 = 0.75 X FLC
Calculate the C2 by the equation: Frequency(Hz)

Figure 10. Converter Gain and Frequency

1
C2 =
2 × π × R2 × FLC × 0.75 Output Inductor Selection

4. Set the pole at the ESR zero frequency FESR: The duty cycle (D) of a buck converter is the function of
FP1 = FESR the input voltage and output voltage. Once an output volt-
Calculate the C1 by the following equation: age is fixed, it can be written as:

C2
C1 =
2 × π × R2 × C2 × FESR − 1

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Rev. A.1 - Jun., 2011
APW8700

Application Information (Cont.)

Output Inductor Selection (Cont.) caused by the AC peak-to-peak sum of the inductor’s
V current. The ripple voltage of output capacitors can be
D = OUT
VIN represented by:
For two-phase converter, the inductor value (L) determines ∆IP − P
∆VCOUT =
the sum of the two inductor ripple currents, ∆IP-P, and af- 8 × COUT × FSW
∆VESR = ∆IP − P × RESR
fects the load transient reponse. Higher inductor value
reduces the output capacitors’ripple current and induces These two components constitute a large portion of the
lower output ripple voltage. The ripple current can be total output voltage ripple. In some applications, multiple
approxminated by: capacitors have to be paralleled to achieve the desired
ESR value. If the output of the converter has to support
VIN - 2VOUT VOUT
∆IP - P = × another load with high pulsating current, more capaci-
FSW × L VIN
tors are needed in order to reduce the equivalent ESR
Where FSW is the switching frequency of the regulator.
and suppress the voltage ripple to a tolerable level. A
Although the inductor value and frequency are increased
small decoupling capacitor in parallel for bypassing
and the ripple current and voltage are reduced, a tradeoff
the noise is also recommended, and the voltage rating
exists between the inductor’s ripple current and the regu-
of the output capacitors are also must be considered.
lator load transient response time.
To support a load transient that is faster than the
A smaller inductor will give the regulator a faster load tran-
switching frequency, more capacitors are needed for
sient response at the expense of higher ripple current.
reducing the voltage excursion during load step change.
Increasing the switching frequency (FSW ) also reduces
For getting same load transient response, the output
the ripple current and voltage, but it will increase the
capacitance of two-phase converter only needs around
switching loss of the MOSFETs and the power dissipa-
half of output capacitance of single-phase converter.
tion of the converter. The maximum ripple current oc-
Another aspect of the capacitor selection is that the
curs at the maximum input voltage. A good starting point
total AC current going through the capacitors has to be
is to choose the ripple current to be approximately 30%
less than the rated RMS current specified on the ca-
of the maximum output current. Once the inductance value
pacitors in order to prevent the capacitor from over-
has been chosen, select an inductor that is capable of
heating.
carrying the required peak current without going into
saturation. In some types of inductors, especially core Input Capacitor Selection
that is made of ferrite, the ripple current will increase
Use small ceramic capacitors for high frequency
abruptly when it saturates. This results in a larger out-
decoupling and bulk capacitors to supply the surge cur-
put ripple voltage.
rent needed each time high-side MOSFET turns on. Place
Output Capacitor Selection the small ceramic capacitors physically close to the
Output voltage ripple and the transient voltage de- MOSFETs and between the drain of high-side MOSFET
viation are factors that have to be taken into con- and the source of low-side MOSFET.
sideration when selecting output capacitors. Higher The important parameters for the bulk input capacitor are
capacitor value and lower ESR reduce the output ripple the voltage rating and the RMS current rating. For reliable
and the load transient drop. Therefore, selecting high operation, select the bulk capacitor with voltage and cur-
performance low ESR capacitors is recommended for rent ratings above the maximum input voltage and larg-
switching regulator applications. In addition to high fre- est RMS current required by the circuit. The capacitor volt-
quency noise related to MOSFET turn-on and turn-off, age rating should be at least 1.25 times greater than the
the output voltage ripple includes the capacitance maximum input voltage and a voltage rating of 1.5 times
voltage drop ∆VCOUT and ESR voltage drop ∆V ESR is a conservative guideline. For two-phase converter, the

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Rev. A.1 - Jun., 2011
APW8700

Application Information (Cont.)

2
Input Capacitor Selection (Cont.) Phigh-side = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW
2
RMS current of the bulk input capacitor is roughly calcu- Plow-side = IOUT (1+ TC)(RDS(ON))(1-D)
lated as the following equation : where
IOUT I is the load current
IRMS = × 2D ⋅ (1 - 2D) OUT
2 TC is the temperature dependency of RDS(ON)
FSW is the switching frequency
For a through hole design, several electrolytic capacitors
tSW is the switching interval
may be needed. For surface mount design, solid tan-
D is the duty cycle
talum capacitors can be used, but caution must be exer-
Note that both MOSFETs have conduction losses while
cised with regard to the capacitor surge current rating.
the high-side MOSFET includes an additional transi-
MOSFET Selection tion loss. The switching interval, t SW , is the function of
The APW8700 requires two N-Channel power MOSFETs the reverse transfer capacitance CRSS. The (1+TC) term is
on each phase. These should be selected based upon a factor in the temperature dependency of the RDS(ON) and
RDS(ON), gate supply requirements, and thermal manage- can be extracted from the “RDS(ON) vs. Temperature” curve
ment requirements. of the power MOSFET.
In high-current applications, the MOSFET power
Layout Consideration
dissipation, package selection, and heatsink are the domi-
In any high switching frequency converter, a correct layout
nant design factors. The power dissipation includes two
is important to ensure proper operation of the regulator.
loss components, conduction loss, and switching loss.
With power devices switching at higher frequency, the
The conduction losses are the largest component of
resulting current transient will cause voltage spike across
power dissipation for both the high-side and the low-
the interconnecting impedance and parasitic circuit
side MOSFETs. These losses are distributed between
elements. As an example, consider the turn-off transition
the two MOSFETs according to duty factor (see the equa-
of the PWM MOSFET. Before turn-off condition, the
tions below). Only the high-side MOSFET has switching
MOSFET is carrying the full load current. During turn-off,
losses since the low-side MOSFETs body diode or an
current stops flowing in the MOSFET and is freewheeling
external Schottky rectifier across the lower MOSFET
by the low side MOSFET and parasitic diode. Any parasitic
clamps the switching node before the synchronous rec-
inductance of the circuit generates a large voltage spike
tifier turns on. These equations assume linear voltage-
during the switching interval. In general, using short and
current transitions and do not adequately model power
wide printed circuit traces should minimize interconnect-
loss due the reverse-recovery of the low-side MOSFET
ing impedances and the magnitude of voltage spike.
body diode. The gate-charge losses are dissipated by
Besides, signal and power grounds are to be kept sepa-
the APW8700 and don’t heat the MOSFETs. However,
rating and finally combined using ground plane construc-
large gate-charge increases the switching interval, tSW
tion or single point grounding. The best tie-point between
which increases the high-side MOSFET switching
the signal ground and the power ground is at the nega-
losses. Ensure that all MOSFETs are within their maxi-
tive side of the output capacitor on each channel, where
mum junction temperature at high ambient temperature
there is less noise. Noisy traces beneath the IC are not
by calculating the temperature rise according to package
recommended. Figure 11. illustrates the layout, with bold
thermal-resistance specifications. A separate heatsink
lines indicating high current paths; these traces must be
may be necessary depending upon MOSFET power,
short and wide. Components along the bold lines should
package type, ambient temperature and air flow.
be placed lose together. Below is a checklist for your
For the high-side and low-side MOSFETs, the losses are
layout:
approximately given by the following equations:

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Rev. A.1 - Jun., 2011
APW8700

Application Information (Cont.)

Layout Consideration (Cont.)
• Keep the switching nodes (UGATEx, LGATEx, BOOTx,
APW8700
and PHASEx) away from sensitive small signal nodes V IN1=VIN
since these nodes are fast moving signals. Therefore,
keep traces to these nodes as short as possible and
there should be no other weak signal traces in paral-
lel with theses traces on any layer. BOOT1
• The signals going through theses traces have both
high dv/dt and high di/dt with high peak charging and
UGATE1
discharging current. The traces from the gate drivers L1
to the MOSFETs (UGATEx and LGATEx) should be short PHASE1
and wide.
• Place the source of the high-side MOSFET and the LGATE1
drain of the low-side MOSFET as close as possible. RS1
Minimizing the impedance with wide layout plane be- V OUT
tween the two pads reduces the voltage bounce of
CSP
the node. In addition, the large layout plane between CS L
CSN O
the drain of the MOSFETs (VIN and PHASEx nodes) RCSN A
can get better heat sinking. RS2 D

• For experiment result of accurate current sensing, the

current sensing components are suggested to place LGATE2
close to the inductor part. To avoid the noise
interference, the current sensing trace should be away PHASE2
from the noisy switching nodes. L2
UGATE2
• Decoupling capacitors, the resistor-divider, and boot
capacitor should be close to their pins. (For example,
place the decoupling ceramic capacitor close to the BOOT2
drain of the high-side MOSFET as close as possible).
• The input bulk capacitors should be close to the drain
of the high-side MOSFET, and the output bulk capaci-
tors should be close to the loads. The input capaci- VIN2 =VIN
tor’s ground should be close to the grounds of the
output capacitors and low-side MOSFET.
• Locate the resistor-divider close to the FB pin to mini- Figure 11. Layout Guidelines
mize the high impedance trace. In addition, FB pin
traces can’t be close to the switching signal traces
(UGATEx, LGATEx, BOOTx, and PHASEx).

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Rev. A.1 - Jun., 2011
APW8700

Package Information
QFN4x4-24

D A

b
D2 A1
A3

Pin 1
Corner
E2
L

S QFN4x4-24
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 0.80 1.00 0.031 0.039
A1 0.00 0.05 0.000 0.002
A3 0.20 REF 0.008 REF
b 0.18 0.30 0.008 0.012
D 4.00 BSC 0.157 BSC
D2 2.50 2.80 0.098 0.110
E 4.00 BSC 0.157 BSC
E2 2.50 2.80 0.098 0.110
e 0.50 BSC 0.020 BSC
L 0.35 0.45 0.014 0.018

Copyright  ANPEC Electronics Corp. 22 www.anpec.com.tw

Rev. A.1 - Jun., 2011
APW8700

Carrier Tape & Reel Dimensions

OD0 P0 P2 P1 A

E1
F

W
B0

K0 A0 OD1 B A
B

SECTION A-A

T
SECTION B-B

d
H
A

T1

Application A H T1 C d D W E1 F
12.4+2.00 13.0+0.50
330.0±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05
-0.00 -0.20
QFN4x4-24 P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0±0.10 8.0±0.10 2.0±0.05 1.5 MIN. 4.30±0.20 4.30±0.20 1.30±0.20
-0.00 -0.40

(mm)

Devices Per Unit

Package Type Unit Quantity
QFN4x4-24 Tape & Reel 3000

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Rev. A.1 - Jun., 2011
APW8700

Taping Direction Information

QFN4x4-24

USER DIRECTION OF FEED

Classification Profile

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Rev. A.1 - Jun., 2011
APW8700

Classification Reflow Profiles

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
100 °C 150 °C
Temperature min (Tsmin)
150 °C 200 °C
Temperature max (Tsmax)
60-120 seconds 60-120 seconds
Time (Tsmin to Tsmax) (ts)

Average ramp-up rate

3 °C/second max. 3°C/second max.
(Tsmax to TP)
Liquidous temperature (TL) 183 °C 217 °C
Time at liquidous (tL) 60-150 seconds 60-150 seconds
Peak package body Temperature
See Classification Temp in table 1 See Classification Temp in table 2
(Tp)*
Time (tP)** within 5°C of the specified
20** seconds 30** seconds
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max.

Time 25°C to peak temperature 6 minutes max. 8 minutes max.

* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.

Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)

3 3
Package Volume mm Volume mm
Thickness <350 ≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
3 3 3
Package Volume mm Volume mm Volume mm
Thickness <350 350-2000 >2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C

Reliability Test Program

Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ Tj=125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA

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Rev. A.1 - Jun., 2011
APW8700

Customer Service

Anpec Electronics Corp.

Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050

Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838

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Rev. A.1 - Jun., 2011