Received February 4, 2020, accepted February 17, 2020, date of publication February 27, 2020, date of current version

March 6, 2020.
Digital Object Identifier 10.1109/ACCESS.2020.2976773

A Fully Static True-Single-Phase-Clocked

Dual-Edge-Triggered Flip-Flop for Near-Threshold
Voltage Operation in IoT Applications
YONGMIN LEE , (Student Member, IEEE), GICHEOL SHIN, (Student Member, IEEE),
AND YOONMYUNG LEE , (Senior Member, IEEE)
College of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, South Korea
Corresponding author: Yoonmyung Lee ([email protected])
This work was supported in part by the Basic Science Research Program under Grant 2019R1A2C4070438, and in part by the Basic
Research Lab Program through the National Research Foundation of Korea (NRF) under Grant 2017R1A4A1015400.

ABSTRACT A Dual-Edge-Triggered (DET) flip-flop (FF) that can reliably operate at low voltage is pro-
posed in this paper. Unlike the conventional Single-Edge-Triggered (SET) flip-flops, DET-FFs can improve
energy efficiency by latching input data at both clock edges. When combined with aggressive voltage scaling,
significant efficiency improvement is expected. However, prior DET-FF designs were susceptible to Process,
Voltage and Temperature (PVT) variations, limiting their operation at low voltage regimes. A fully static true-
single-phase-clocked DET-FF is proposed to achieve reliable operation at voltages as low as a near-threshold
regime. Instead of the two-phase or pulsed clocking scheme in conventional DET-FFs, a True-Single-Phase-
Clocking (TSPC) scheme is adopted to overcome clock overlap issues and enable low-power operation.
Fully static implementation also enables robust operation in a low voltage regime. The proposed DET-FF
is designed in 28nm CMOS technology, and a comprehensive analysis including post-layout Monte Carlo
simulation for wide PVT ranges is performed to validate the design approaches. Extensive analysis and
comparison with prior-art DET-FFs confirmed that the proposed DET-FF can operate at the lowest voltage
of 0.28 V for a temperature range of −40 ◦ C to 120 ◦ C while maintaining nearly-best energy efficiency and
power-delay-product.

INDEX TERMS Flip-flop, dual-edge-triggered (DET), single phase, low power, near-threshold voltage.

I. INTRODUCTION of the dynamic power in a synchronous system. For this

Flip-flops are one of the most essential circuit elements for reason, many research works have been performed to develop
modern digital circuit design since they provide local data flip-flops with lower power consumption and better energy
storage and synchronize the data flow. Since such synchro- efficiency to date [3]–[27].
nization should be done throughout the entire clock domain, The most popular approach for implementing a flip-flop is
a large number of flip-flops are utilized in a typical pro- using either the rising or falling edge of the clock as the trig-
cessor, often hundreds of thousands [1]. Because of their gering source for the latching operation. This type of flip-flop
sheer number, flip-flops occupy a large portion of the overall is called a Single-Edge-Triggered flip-flop (SET-FF), and
circuit architecture in terms of both power and physical area. they are widely used for their simple implementation and ease
Therefore, reducing the power consumption of flip-flops has of timing characterization [3]–[7]. In contrast, Dual-Edge-
great impact on system-level energy efficiency, especially for Triggered flip-flops (DET-FFs) take advantage of the unused
energy-constrained IoT applications. Minimizing power con- clock edge in SET-FFs, i.e. the latching operation is triggered
sumption in IoT Integrated Circuits (ICs) is very important at both the rising and falling clock edges. Utilizing both clock
for maximizing battery life [2]. However, flip-flops, which edges potentially achieves better energy efficiency because
are toggled by the clock every cycle, consume a large portion it allows twice the data throughput compared to SET-FFs
with the same clock frequency. Therefore, DET-FFs have
The associate editor coordinating the review of this manuscript and been proposed as an alternative sequential circuit element for
approving it for publication was Gian Domenico Licciardo . reducing power consumption compared to SET-FFs [8]. To

This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see http://creativecommons.org/licenses/by/4.0/
40232 VOLUME 8, 2020
Y. Lee et al.: Fully Static True-Single-Phase-Clocked DET-FF for Near-Threshold Voltage Operation in IoT Applications

implement dual edge sensitivity, various topologies, includ-

ing complementary latch pair and pulse-triggered latch, have
been studied [9]–[27], as will be discussed in Section II.
Meanwhile, a simple but widely used design technique
for maximizing energy efficiency in an electronic system
is voltage scaling [28]–[30]. By scaling down the supply
voltage, quadratic reduction in dynamic energy consumption
can be achieved. Therefore, voltage scaling is widely adopted
among energy-constrained IoT applications [31], [32] and
battery-operated miniature sensors [33]–[35]. To apply such
voltage scaling to flip-flops, aggressive voltage scalability is
of critical concern. However, due to increased sensitivity to
the process variation in low voltage regimes, guaranteeing
robust flip-flop operation at low supply voltage is a non-trivial
challenge, especially with the advanced technologies where
process variation is becoming increasingly prominent.
In this paper, a DET-FF suitable for aggressive voltage
scaling down to a near-threshold voltage regime is presented.
By adopting a single-phase clocking scheme and removing
all internal dynamic nodes, robust operation at voltage as low
as 0.28 V is verified for temperatures ranging from −40 ◦ C
to 120 ◦ C with Monte Carlo simulations.
The rest of this paper is organized as follows: Section II
analyzes the prior-art DET-FFs, categorized as three dif-
ferent types, and discusses their strengths and weaknesses.
Section III presents the proposed fully static true-single-
phase-clocked DET-FF designed for robust operation at low FIGURE 1. Latch-MUX-type DET-FFs: (a) Static DET-FF (SDET FF) [20] (b)
voltage regimes. Section IV shows the simulation results and True-single-phase-clock SDET FF (TSPC-SDET FF) [27].
comparisons with other DET-FFs, and Section V concludes
the paper.
and a multiplexer are controlled by complementary internal
II. REVIEW OF THE PRIOR-ART DUAL-EDGE-TRIGGERED clock signals (CKB, CKI), which are generated from the CLK
FLIP-FLOPS signal through 2-stage inverters.
The prior-art DET-FFs can be categorized into three types: When CLK = ‘1’, the input transmission gate of the
Latch-Multiplexer, Pulsed-Latch, and C-element. Through positive latch is turned on, and the input data is stored in
the analysis of these 3 types of DET-FF topologies, the char- the positive latch. On the other side, the input transmission
acteristics and limitations of the conventional DET-FF gate of the negative latch is turned off, keeping the value
designs are highlighted. A new DET-FF design that over- stored in the last cycle in the negative latch. Meanwhile,
comes these limitations will be introduced in the following the multiplexer is controlled to forward the value stored in
section. the negative latch to output as long as the CLK stays high.
At the falling transition of the CLK (‘1’→’0’), the data in
A. LATCH-MULTIPLEXER-TYPE DET-FF the positive latch is forwarded to the output node Q by the
Fig. 1 shows two Latch-Multiplexer (MUX) Dual-Edge- multiplexer. At the same time, the input transmission gate
Triggered flip-flops (LM-DET FFs). In this type of DET-FF, of the positive latch is turned off so that the current input
a pair of latches is utilized for latching data at the positive and data can be safely latched, fulfilling the latching operation
negative clock edges, and a multiplexer selects either of the at the falling edge of the CLK. The negative latch performs
latches to drive the output. a complementary operation, storing the following inputs for
Fig. 1(a) shows one example of an LM-DET FF, a Static the next latching operation at the rising transition of the CLK.
DET FF (SDET FF) presented in [20]. In this FF, each In this SDET FF, two-phase clock signals are required to
latch consists of back-to-back connected inverters and a control the tri-state inverters and prevent contention. The two
transmission gate. The original structure of the SDET FF latches are required to operate in a complementary manner.
in [20] utilizes single nmos (or pmos) as the pass gates, However, CKB and CKI can overlap for a short time since
which makes it vulnerable to process and voltage varia- they are generated with 2-stage inverters. Such a problem
tions. In this paper, for comparison with other DET-FFs can worsen in low voltage regimes where delay variation is
with improved reliability, the pass gates are replaced with exacerbated. As demonstrated in [27], the two transmission
transmission gates for analysis and simulations. Two latches gates that form a multiplexer can be turned on at the same

VOLUME 8, 2020 40233

 Y. Lee et al.: Fully Static True-Single-Phase-Clocked DET-FF for Near-Threshold Voltage Operation in IoT Applications

time during clock overlap, making it possible for one latch’s

data to upset the other latch’s data.
A True-Single-Phase-Clock static DET flip-flop
(TSPC-SDET FF) [27], shown in Fig. 1(b), is proposed to
address this issue. The positive and negative latches operate
in a complementary manner just like in [20]. But unlike
in the SDET FF, a single-phase clocking scheme similar
to C2MOS [36] is adopted to fundamentally eliminate the
two-phase clock overlap issue at the cost of an increased
number of transistors.
However, weak pull-up and pull-down in the TSPC-SDET
FF make its voltage scalability limited and prone to variation.
For example, when CLK = ‘0’ and SNP = ‘1’ in the positive
latch, the gate of transistor MP is not fully pulled down to
ground due to a PMOS on the pull-down path. Therefore,
the node XP is weakly pulled up by MP. Similarly, when
CLK = ‘1’ and SNN = ‘0’ in the negative latch, the node
XN is weakly pulled down. Therefore, although it claims to
be a ‘static’ DET FF, it is not fully static (i.e., it does not
swing across the full voltage range), and, because of this
problem, it is not suitable for aggressive voltage scaling and
near-threshold voltage operation.

B. PULSED-LATCH-TYPE DET-FF
As alternatives to the Latch-Multiplexer-type DET-FF, many
pulse-triggered DET FFs have been proposed [9]–[18]. In this
topology, a pulse generator generates a clock-synchronized
FIGURE 2. Pulsed-Latch-type DET-FF. (a) Dual-Edge Conditional
pulse at both the rising and falling clock edges. These clock- Pre-charge (DECP) FF [17] (b) Sense-Amplifier (SA) DET FF [11].
synchronized pulses are used as triggers for the latching
operation of the pulsed latches. Pulsed-latch-type DET-FFs require pulse-generating cir-
Pulsed-Latch-type DET FFs (PL-DET FFs) consist of cuits. Since the transparency window of pulsed latches
a pulse generator and a pulsed latch and can be classi- is determined by the pulse length, timing is very impor-
fied into two types – implicit pulse [13]–[18] and explicit tant. However, since typical pulse-generating circuits rely
pulse [9]–[12]. Fig. 2 shows a PL-DET FF using an on transistor delay to control the pulse length, the pulse
implicit pulse (Fig. 2(a)) and one using an explicit pulse characteristics can be easily affected by Process, Volt-
(Fig. 2(b)) [11], [17]. The Dual-edge Conditional Pre-charge age and Temperature (PVT) variations. Therefore, careful
flip-flop (DECP FF) [17] shown in Fig. 2(a) utilizes control pulse-generation circuit design is required to make it robust
signals generated by the input CLK. The delayed version against PVT variations. Such careful design often requires
of CLK (CK4), the inverted version of CLK (CKD), and large margins for variation tolerance, resulting in large power
the CLK signal generate a short transparency window after and area overhead.
both the rising and falling edge of the CLK. During these
windows, the input data is forwarded to the output node Q C. C-ELEMENT-TYPE DET-FF
in the pulsed latch. This implicit pulse-type DET-FF requires Another type of recently designed DET-FF includes a circuit
a robust timing window for reliable operation, so the careful element called a ‘C-element’ [23], [24]. As illustrated in
sizing of transistors is an important design issue. Fig. 3(a), when the two inputs of a C-element are the same,
An example of a pulsed-latch-type DET-FF with explicit the output is updated to the input value, whereas the earlier
pulse is the Sense-Amplifier DET flip-flop (SA-DET FF) output value is retained when the two input values differ from
[11] shown in Fig. 2(b). This DET-FF utilizes pulses gen- each other. Thanks to the ability of C-element-type DET-
erated by complementary two-phase clock signals, namely FFs to latch new data or retain data depending on the input
CLK1 and CLK2. When these signals become equal for a conditions, many different topologies have been proposed to
very short period of time due to their generation circuit struc- implement them.
ture (series-connected inverters), a pulse generator circuit Fig. 3(b), (c) show examples of DET-FF designs using
generates a short pulse signal, which is used to trigger the C-elements. The New low-power C-element Dual Data Rate
latching operation in a pulsed latch. Since the pulses are flip-flop (NCDDR FF) [23] shown in Fig. 3(b) includes two
generated whenever CLK1 and CLK2 are both ‘1’ or both latches that store the input values in opposite phases. The
‘0’, the data is latched at both CLK edges. latched input is stored in nodes A and B, which are used as

40234 VOLUME 8, 2020

Y. Lee et al.: Fully Static True-Single-Phase-Clocked DET-FF for Near-Threshold Voltage Operation in IoT Applications

FIGURE 3. C-element-type DET-FF. (a) Truth table and operation

waveforms of C-element (b) NCDDR FF [23] (c) FN_C-DET FF [24]. FIGURE 4. Simplified illustration of operation principle of
Latch-MUX-type DET-FFs. (a) SDET FF [20] (b) TSPC-SDET FF [27]
(c) proposed FS-TSPC-DET-FF.
input for the C-element. In this manner, the C-element can
latch input data at both clock edges. However, in this DET-FF
design, the latched data is held by back-to-back connected III. PROPOSED FULLY STATIC TRUE-SINGE-PHASE-
weak inverters, which incur contention when new data is CLOCKED DUAL-EDGE-TRIGGERED FLIP-FLOP
written to the storage node by overpowering the feedback For energy-efficient digital circuit operation with aggressive
inverter. For reliable operation, the feedback inverters and voltage scaling in IoT applications, DET-FFs that are robust
overriding transistors should be carefully sized. In addition, against PVT variations are required. Among the three types of
two input transmission gates controlled by the two-phase DET-FFs discussed in Section II, Pulsed-latch-type DET-FFs
clock can potentially cause a clock overlap issue, as observed require precisely timed short pulses, which are prone to
for SDET FFs. PVT variation. In addition, C-element-type DET-FFs suffer
The Floating Node C-element DET flip-flop (FN_C-DET from weak feedback, which inevitably creates contention
FF) [24] shown in Fig. 3(c) uses five C-elements in total: two during the latching operation. As a result, these two types of
2-input C-elements at the input, two 3-input C-elements in the DET-FFs have limited voltage scalability and are not suitable
middle, and one output C-element. At the input C-elements, for low-voltage operation. Therefore, a new DET-FF based on
D, CKB and CKI signals determine the logical values of the Latch-MUX topology is proposed to allow aggressive voltage
internal nodes A and B. These A and B signals control the scaling by avoiding contention during the latching operation.
output C-element, which determines the value of Q. The node The proposed DET-FF is 1) fully static without weak pull-
X is used as a feedback signal at the inner C-element pair. up/down, 2) true single-phase clocked, and 3) contention
By using five C-elements, an FN_C-DET FF forwards the free. Therefore, the proposed DET-FF is robust against PVT
input data at both clock edges. However, when the value of variations and does not require transistor sizing to overcome
A or B switches, contention can occur at the data storage contention, which allows compact sizing of the FF, enabling
node of the C-element. To reduce contention, the two inner small area and power overhead. These advantages enable
C-elements should be designed to be weaker than the two reliable operation with aggressive voltage scaling across a
C-elements at the input so that the internal storage data can wide temperature range.
be flipped correctly. Fig. 4 shows the block-level diagrams of the conven-
Although C-element-type DET-FFs offer some advan- tional Latch-MUX-type DET-FFs and the proposed Fully
tages, the usage of back-to-back inverters for retaining Static True-Single-Phase-Clock DET flip-flop (FS-TSPC-
data [23], [24] creates inevitable contention. Therefore, DET FF). In the SDET FF [20], shown in Fig. 4(a), a pair
C-element-based DET-FFs require careful design to improve of complementary phase clocks is applied to complementary
reliability and apply aggressive voltage scaling. latches to enable either of the latches at a given point in time.

VOLUME 8, 2020 40235

 Y. Lee et al.: Fully Static True-Single-Phase-Clocked DET-FF for Near-Threshold Voltage Operation in IoT Applications

(M in Fig. 5(b)) is activated, while the feedback clocked

inverter is deactivated, making the positive latch transparent
(QP = DP = D). In contrast, when CLK = ‘0’, the NOR gate
acts as an inverter (CDP = DP). In this case, two scenarios
(S1, S2) are possible depending on the DP value: S1) If DP =
‘0’, hence CDP = ‘1’, the back-to-back connected inverters
are activated, and the DP and QP nodes remain static state;
or S2) If DP = ‘1’, hence CDP = ‘0’, the feedback-clocked
inverter (N in Fig. 5(b))’s pull-down path is off since nmos
controlled by CDP is turned off. However, the feedback-
clocked inverter’s pull-up network is on since QP = CLK =
‘0’, allowing stable DP data retention with static DP and QP
nodes. As a result, every node in this positive latch is always
static, which is desired for stable operation at low voltage.
Fig. 5(c) shows the simulation waveform for the positive
latch. It can be clearly seen that the latch is transparent while
CLK = ‘1’. The negative latch in the proposed DET-FF
is complementary to the presented positive latch – it uti-
lizes the NAND gate instead of the NOR gate as a neg-
ative clock-conditioned data signal generator and becomes
transparent while CLK = ‘0’. These two static latches are
symmetric elements required for complementary operation.

B. FULLY STATIC COMPLEMENTARY CMOS MULTIPLEXER

Fig. 6(a) shows an LM DET-FF topology using the posi-
FIGURE 5. Positive latch in proposed DET-FF. (a) Transistor-level tive and negative latches described earlier, whose outputs
schematic (b) Gate-level schematic (c) Waveforms of positive latch.
are combined with the transmission-gate-based multiplexer.
As with the prior SDET FF [20], either of the latched data at
At the same time, a multiplexer (MUX), which is a pair of
the QP or QN node is transferred to the output Q through
transmission gates controlled by a two-phase clock, forwards
the MUX to function as a DET-FF. For controlling the
the latched data in either of the latches to output Q. The
transmission-gate-based MUX, two-phase clock signals are
TSPC-SDET FF [27] in Fig. 4(b) utilizes a single-phase clock
required, which can be generated by a simple inverter chain.
so that it can avoid a clock-overlap issue and operate reliably
However, as discussed in Section II, such topology can
with low supply voltage. However, the TSPC-SDET FF still
incur data upset during clock overlap due to delay mismatch
has limitations in near-threshold operations due to the weak
of CLK and CLKB at the transmission gate MUX. Introduc-
pull-up/pull-down, as stated earlier.
ing a tri-state inverter-based MUX [27] still results in weak
For better voltage scalability with robust low-voltage oper-
pull-up/down.
ation, the FS-TSPC-DET FF is proposed, whose concept is
Therefore, in the proposed DET-FF, a fully static comple-
shown in Fig. 4(c). Similar to a TSPC-SDET FF, the proposed
mentary CMOS MUX is utilized to 1) prevent data upset
DET-FF utilizes only a single-phase clock. But compared to
due to clock overlap and 2) keep every node fully static (full
TSPC-SDET FF, the proposed DET-FF utilizes a complemen-
swing) at any given time.
tary CMOS logic gate as a multiplexer, preventing poten-
The fully static complementary CMOS MUX is derived
tial issues with transmission gate MUX or tri-state inverter
by logic minimization, where multiplexing operation is per-
MUX. To make the CMOS logic gate function as a MUX,
formed only with existing internal signals. Since all of the
two clock-conditioned data signals – CDP and CDN – are
nodes in the positive/negative latches are static with full
generated with clock and data input and used as inputs for the
voltage swing, the complementary CMOS MUX can operate
MUX. These signals simultaneously 1) forward latched val-
without any stability issue. The logic minimization process
ues to output and 2) control the behavior of each latch without
for the complementary CMOS MUX is as follows:
weak pull-up or pull-down. The details of the proposed latch
Firstly, the latched data DP/DN and their inverted value
are described in the following sub-sections.
QP/QN can be written as
A. POSITIVE AND NEGATIVE LATCH
Fig. 5(a) and (b) show schematics of the positive latch in the DP = CDP·CLK + D·CDP· CLK (1)
proposed DET-FF. CDP is a positive clock-conditioned data DN = CDN·CLK + D·CDN · CLK (2)
signal generated by NOR operation of the CLK and latched
data (DP). When CLK = ‘1’, CDP is always 0 regardless of QP = DP (3)
the DP value. In this condition, the input clocked inverter QN = DN (4)
40236 VOLUME 8, 2020
Y. Lee et al.: Fully Static True-Single-Phase-Clocked DET-FF for Near-Threshold Voltage Operation in IoT Applications

In this equation, the term related to QP can be rewritten as

follows by using (3) and (5):

QP · CLK = DP·CLK = DP + CLK = CDP (8)

Therefore, equation (7) can be rewritten as

Q = CDP + QN · CLK (9)

Therefore, the transmission-gate-based MUX in Fig. 6(a) can

be replaced with a complementary CMOS AO (AND-OR)
gate as shown in Fig. 6(b). In the proposed DET-FF design,
a total of 36 transistors are used, which is less than a prior
TSPC-DET FF [27] with 38 transistors.
Fig. 7 illustrates the operation of a FS-TSPC-DET FF in
each clock and input data condition. The top row shows the
case where the initial DP value is ‘0’ and the input D is ‘0’,
whereas the bottom row shows the case where the initial DP
is ‘1’ and the input D is ‘1’. The detailed behavior is presented
as the CLK toggles from ‘0’ to ‘1’ and then from ‘1’ to ‘0’.
In the initial state (CLK = ‘0’), the positive latch holds
the internal data (DP). Note that CDP = ‘0’ when DP =
‘1’ (bottom left in Fig. 7); hence, the stacked NMOS in the
feedback-clocked inverter is turned off. However, since QP
= ‘0’, only the pull-up path of the feedback inverter matters,
and all nodes are still statically driven to VDD or GND.
Meanwhile, the output QB is determined solely by CDP since
QN is ANDed with CLK at the MUX.
As the clock rises (CLK = ‘1’), the data stored in the
negative latch is now forwarded to QB through the MUX
since CDP is forced to be ‘0’ and CLK is ‘1’. The internal data
at the positive latch (DP) can be updated since 1) the input
clocked inverter is fully on (CDP = ‘0’) and 2) the feedback
clocked inverter is fully off (CLK = ‘1’ and CDP = ‘0’).
At the clock falling transition, the negative latch
becomes transparent again, and the updated data in the
positive latch will be forwarded to the output QB/Q.
Although the TSPC-SDET FF [27] also utilizes the same
single-phase clocking method, the clock-conditioned data
signals (CDP/CDN) in the proposed DET-FF can reduce
the number of transistors connected to the input clock
(from 14 to 10), resulting in lower power consumption
caused by clock transition.
FIGURE 6. (a) The Latch-MUX DET-FF with the proposed two static latches
and the transmission gate MUX (before logic minimization) (b) proposed
fully static DET-FF with the fully static complementary CMOS MUX using IV. SIMULATION ANALYSIS AND COMPARISON
TSPC.
The proposed FS-TSPC-DET FF is designed and its lay-
out is modeled in 28nm LP bulk CMOS technology for
Secondly, the clock-conditioned data CDP/CDN can be detailed analysis. In addition, 6 other DET-FFs described
obtained with NAND/NOR operation as in section II (SDET FF [20], TSPC-SDET FF [27], DECP
CDP = DP + CLK (5) FF [17], SA-DET FF [11], NCDDR FF [23], and FN_C-DET
FF [24]) are also designed for comparison. In advanced tech-
CDN = DN · CLK (6) nology nodes, the reliability and performance of the digital
Meanwhile, the final output Q should be the output of the circuits rapidly degrade in a low-voltage regime due to exac-
MUX, which selectively forwards QP or QN depending on erbated PVT variations. Therefore, to verify the proposed
the clock phase. Its logic function can be written as design in challenging conditions, relatively advanced process
node (28nm), among those that can be accessed, is selected
Q = QP · CLK + QN · CLK (7) for design and analysis. In addition, since the proposed FF is

VOLUME 8, 2020 40237

 Y. Lee et al.: Fully Static True-Single-Phase-Clocked DET-FF for Near-Threshold Voltage Operation in IoT Applications

FIGURE 7. FS-TSPC-DET FF gate-level schematic and its operation.

targeted for IoT applications, Low-Power (LP) process, rather This approach also includes the use of non-minimum-length
than General Purpose (GP), is chosen. transistors for reliable pulse lengths in pulsed-latch-type
Fig. 8 presents the layout of the 7 DET-FFs designed DET-FFs.
for post-layout analysis. All DET-FF designs are carefully
sized to guarantee reliable operation at room temperature A. STANDARD SUPPLY VOLTAGE OPERATION
and standard supply voltage (0.95 V) while keeping the size Fig. 9 shows the simulation setup for fair data measurement
as small as possible for energy efficiency. RC parasitics and comparison, which is similar to the one used in [16], [37].
are extracted for the layouts shown in Fig. 8 so that the Two inverters are utilized as input drivers for the input
post-layout simulations can be performed at various operation clock (CLK) and data (D). To precisely model the power con-
conditions. sumption of the DET-FFs, the power consumed for driving
Among the 3 types of DET-FFs, the pulsed-latch-type each pin is estimated by measuring the power consumed on
DET-FF (DECP FF [17], SA-DET FF [11]) and the these drivers. For example, the power consumed for driving
C-element-type DET-FF (NCDDR FF [23], FN_C-DET the CLK input (PCLK ) can be calculated as
FF [24]) are more susceptible to PVT variations than the
PCLK = PDriver_CLK − PDriver_CLK _int (10)
Latch-MUX-type DET-FF (SDET FF [20], TSPC-SDET
FF [27] and FS-TSPC-DET FF) since the pulsed-latch-type where PDriver_CLK is the total measured power consump-
DET-FF requires precise pulse timing and the C-element-type tion of the power supply of the CLK-driving inverter, and
DET-FF has contention with the weak inverters. Therefore, PDriver_CLK _int is the CLK-driving inverter’s intrinsic power
these DET-FFs require proper transistor sizing for stable consumption, which can be measured by measuring the
operation. However, sizing up transistors to ensure a mini- power consumption of the CLK-driving inverter without the
mum reliable pulse length for pulsed-latch-type DET-FFs or DET-FF’s CLK pin loading. Similarly, the power consumed
making a weak inverter for C-element-type DET-FFs would for driving D input (PD ) can be calculated as
incur greater power and area overhead. Due to this trade-off,
the transistor sizes are carefully chosen for these two types PD = PDriver_D − PDriver_D_int (11)
of DET-FF designs so that stable operation at the standard
supply voltage and room temperature is guaranteed while and the power consumed for the internal switching of the flip-
keeping the area compact and energy efficiency reasonable. flop (PFlip−Flop ) can be measured by the power consumption

40238 VOLUME 8, 2020

Y. Lee et al.: Fully Static True-Single-Phase-Clocked DET-FF for Near-Threshold Voltage Operation in IoT Applications

FIGURE 8. Layout of 7 DET-FFs. (a) SDET FF (b) TSPC-SDET FF (c) DECP FF (d) SA-DET FF (e) NCDDR FF (f) FN_C-DET FF (g) FS-TSPC-DET FF.

the clock input. For example, three DET-FFs using comple-

mentary two-phase clocking – namely SDET FF, NCDDR
FF, and FN_C-DET FF – consume the least amount of
power since they have only 2 transistors at the CLK input.
In contrast, the proposed FS-TSPC-DET FF has 10 transistors
and TSPC-SDET FF has 14 transistors at the CLK input,
resulting in relatively higher CLK driver power consumption.
Meanwhile, if contention exists on the CLK node, the CLK
FIGURE 9. DET-FF simulation setup including the input driver. driver can consume more power than is proportional to the
transistor count. For example, DECP FF, shown in Fig. 2,
has 7 transistors and SA-DET FF has 6 transistors on the
of the flip-flop’s power supply. Then the total power con- CLK input. However, the pulse generator in SA-DET FF has
sumption of a DET-FF can be represented as contention during the pulse generation at the PULS node.
Therefore, SA-DET FF consumes more CLK driver power
PTotal = PFlip−Flop + PD + PCLK than DECP FF despite its lower CLK input transistor count.
= PFlip−Flop + (PDriver_D − PDriver_D_int ) Since the CLK node activity does not change with α, PCLK
+ (PDriver_CLK − PDriver_CLK _int ) (12) does not change with α.
Secondly, the power consumption of the data (D) input
Meanwhile, the potential wire capacitance and resistance driver (PD ) is directly proportional to the activity ratio (α) and
outside the DET-FF layout are not included in the simu- accounts for a relatively small percentage of the total power
lation since they can vary significantly depending on the consumption if there is no contention on D input. It can be
implementation. seen that PD is less than 10 % for TSPC-SDET FF, DECP
To evaluate the standard voltage operation of FF, FN_C-DET FF and FS-TSPC-DET FF. With SDET FF,
the 7 DET-FFs, each DET-FF is simulated with the nominal SA-DET FF and NCDDR FF, D input can be directly con-
supply voltage (0.95 V) at room temperature (27 ◦ C) assum- nected to the data retention node in certain phases or for a
ing TT (typical) process corner. A clock frequency of 1 GHz short time period, which creates contention and draws more
is used, and a varying data switching activity ratio (α) of 10%, power from D input driver. In the SDET FF and NCDDR FF,
25% or 50% is applied. Fig. 10 shows the measured power two latches and the D node can be shorted due to clock-phase
consumption of the DET-FFs, and the power consumption is misalignment, which makes PD sharply increase at α = 25%
broken down into PFlip−Flop , PD and PCLK . A few interesting and 50% compared to when α = 10%.
trends can be observed with the power consumption analysis Thirdly, the power consumption through a flip-flop’s
in Fig. 10. power supply (PFlip−Flop ) increases with a higher α but at
Firstly, the power consumption of the clock (CLK) input a lower ratio compared with α. This is because internal
driver (PCLK ) is proportional to the number of transistors at switching of a flip-flop is related to both the clock and data.

VOLUME 8, 2020 40239

 Y. Lee et al.: Fully Static True-Single-Phase-Clocked DET-FF for Near-Threshold Voltage Operation in IoT Applications

FIGURE 11. CLK-to-Q delay versus D-to-CLK delay. (a) all output
transitions at both clock edges in the proposed FS-TSPC-DET FF. (b) setup
time comparison with 7 DET-FFs.

by D input, thanks to the lack of contention. 3) The baseline

PFlip−Flop is relatively small compared with that of the other
DET-FF. This is because there is no potential contention
within the flip-flop. Overall, the proposed FS-TSPC-DET
FF has low power consumption compared with the other
analyzed DET FFs: second lowest when α = 10% or 25%
and the lowest with α = 50%. This means that the penalty
for increased data activity is smaller, thanks to the reduced
FIGURE 10. Power consumption of 7 DET-FFs at standard VDD (0.95 V). internal switching activity.
Switching activity is (a) 10% (b) 25% (c) 50%. Fig. 11 shows the CLK-to-Q delay (Tcq ) as a function
of D to CLK delay in standard VDD = 0.95 V. For accurate
For example, the amount of power consumed for driving an setup/hold time measurement, D-to-CLK delay is swept for
inverted clock signal (CLKB) in flip-flops with a two-phase every 0.02 ps, and more than 10,000 data points were mea-
clocking scheme is not correlated with and hence does not sured. In Fig. 11(a), the Tcq values for all 4 types of transition
change with α. On the other hand, the amount of power cases are shown for the proposed FS-TSPC-DET FF. In this
consumed for switching the latched data is directly correlated figure, Tcq and the setup time are determined by the case
with α. Therefore, the increase in PFlip−Flop with higher α where Q is rising at the rising edge of the CLK. Fig. 11(b)
can be minimized by minimizing the data-related internal shows Tcq for all 7 DET-FFs. In general, the Latch-MUX-
switching activity. type DET-FFs (SDET FF, TSPC-SDET FF and FS-TSPC-
In regards to these trends, the following observations can DET FF) provide a shorter Tcq than other types of DET-FFs.
be made for the proposed FS-TSPC-DET FF: 1) A large
portion of the proposed DET-FF’s power consumption is B. NEAR-THRESHOLD SUPPLY VOLTAGE OPERATION
due to the CLK driver. This is due to the large number of The DET-FFs are simulated under near-threshold voltage to
clock-loading transistors. 2) Negligible power is consumed examine voltage scalability for low-voltage operation in IoT

40240 VOLUME 8, 2020

Y. Lee et al.: Fully Static True-Single-Phase-Clocked DET-FF for Near-Threshold Voltage Operation in IoT Applications

FIGURE 13. Comparisons of power-delay-product (PDP) in low supply

voltage with 4 DET-FFs.

than with the other 3 DET-FFs, and the designs with

true-single-phase clocking schemes (TSPC-SDET FF,
FS-TSPC-DET FF) maintain faster operation than the other
DET-FFs even at low supply voltage conditions.
The total power consumption (PTotal ) and CLK-to-Q
delay (Tcq ) are both important metrics for DET-FF opera-
tion in low-voltage conditions, but there can be trade-off
between these two metrics. For this reason, the power
delay product (PDP = PTotal ×Tcq ) is often used [11],
[27], [23] to evaluate FFs. Fig. 13 shows the PDPs
of the 4 DET-FFs under near-threshold voltage opera-
FIGURE 12. Comparisons of 4 DET-FFs with low supply voltages (a) Total tion. Although the FN_C-DET FF has the lowest PTotal ,
power consumption (Ptotal ) at varying switching activity ratios (b) Supply TSPC-SDET FF and FS-TSPC-DET FF present significantly
voltage versus CLK-to-Q delay (Tcq ) plots.
better PDPs regardless of α due to significantly lower
Tcq . This implies that the proposed FS-TSPC-DET FF can
applications. To evaluate the near-threshold voltage operation be a suitable solution for low-voltage operation in IoT
of the DET-FFs, each DET-FF is simulated with a supply applications.
voltage of 0.3 V at room temperature (27 ◦ C) and a clock
frequency of 1 MHz, assuming TT (typical) process corner. C. MONTE CARLO SIMULATION WITH SUPPLY VOLTAGE
Under the given conditions, the 3 DET-FFs (SA-DET FF, AND TEMPERATURE SCALING
DECP FF and NCDDR FF) failed to function properly for at Even though the proposed FS-TSPC-DET FF has low power
least one clock edge due to failure in pulse generation or data consumption and small delay, its robustness against PVT vari-
contention. Therefore, only the remaining 4 DET-FFs (SDET ation should be verified for near-threshold voltage operation
FF, TSPC-SDET FF, FN_C-DET FF and FS-TSPC-DET FF) since the impact of variation is exaggerated in this voltage
are reported in this section. regime. To evaluate the robustness of the DET-FFs, Monte
Fig. 12 shows the total power consumption (PTotal ) and Carlo simulations (for process corner and mismatch) are
CLK-to-Q delay (Tcq ) of these 4 DET-FFs with varying performed with aggressive supply voltage scaling and a wide
switching activities (α = 10%, 25%, 50%). In Fig. 12(a), temperature range. In this simulation, the 4 DET-FF designs
the proposed FS-TSPC-DET FF shows the second lowest evaluated for near-threshold voltage operation are examined
PTotal at low α of 10% and 25% and the lowest PTotal at again.
high α of 50%, which is similar to the results obtained under Fig. 14 shows the input test pattern used for the Monte
standard voltage. In addition to PTotal , another metric that Carlo simulations, which is carefully designed to check the
requires attention under low voltage operation is Tcq . With functionality of each DET-FF for all possible input combina-
aggressive voltage scaling down to near-threshold regimes, tions. All possible transition scenarios of input D and CLK
Tcq can exponentially increase and impact the overall perfor- (up to 3 transitions of one signal while the other signal is
mance of digital circuits. Fig. 12(b) show how Tcq changes unchanged) are included in this test pattern, as shown in
with aggressive voltage scaling. As the supply voltage is the truth table. The input clock frequency is set to 1 kHz,
decreased from 0.4 V to 0.3 V, Tcq rapidly increases. It can be which is sufficiently low to allow functional failures with
seen that Tcq increases more sharply with the FN_C-DET FF long delay to be checked. A long delay between the CLK and

VOLUME 8, 2020 40241

 Y. Lee et al.: Fully Static True-Single-Phase-Clocked DET-FF for Near-Threshold Voltage Operation in IoT Applications

FIGURE 14. Test pattern and truth table for Monte Carlo simulation.

FIGURE 15. Monte Carlo simulation results with 4 DET-FFs with aggressive voltage and temperature scaling.

data transition is assumed so that only the functional failures represents ‘pass’ in 10k Monte Carlo simulations and a red
not related to setup or hold-time violations are checked. If a box represents ‘fail’ for failing at least 1 test case. Among
DET-FF operates with no functional failure, the output Q is the 4 evaluated DET-FFs, the SDET FF and FN_C-DET FF
expected as shown Fig. 14, synchronizing the input data at have limited functionality at low voltage and low temper-
each marked point (a–f). ature. This is because these DET-FFs utilize a two-phase
Monte Carlo simulations were performed for a supply clocking scheme, where the clock overlap issue can be worse
voltage range of 0.2 V to 0.5 V with 20-mV steps and a with PVT variations. Furthermore, in the FN_C-DET FF,
temperature range of −40 ◦ C to 120 ◦ C with 10 ◦ C steps. the strong and weak C-elements have contention on the data
For each condition, 10k Monte Carlo points were simulated storage node, making it susceptible to PVT variations. Thanks
for accurate evaluation. The Shmoo plots for the 4 DET-FFs to their single-phase clocking scheme, TSPC-SDET FF and
are shown in Fig. 15. In these Shmoo plots, a green box FS-TSPC-DET FF can operate without failure at the lower

40242 VOLUME 8, 2020

Y. Lee et al.: Fully Static True-Single-Phase-Clocked DET-FF for Near-Threshold Voltage Operation in IoT Applications

TABLE 1. DET-FF comparison of simulation results at standard conditions.

voltages and temperatures. However, TSPC-SDET FF cannot prior-art designs at a given supply voltage but also can operate
function below 0.3 V due to the weak pull-up/pull-down (at with the lowest supply voltage. These properties make the
node XP or XN in Fig. 1(b)). Thanks to the fully static imple- proposed FF an excellent candidate as an energy-efficient
mentation, the proposed FS-TSPC-DET FF has the lowest sequential circuit element for energy/cost-sensitive IoT appli-
functional supply voltage and temperature – it could operate cations with aggressive dynamic voltage scaling down to a
without failure at 0.28 V for the entire tested temperature near-threshold voltage of 0.28 V.
range.
Table 1 summarizes the evaluation results with standard
supply voltage conditions (VDD = 0.95 V, input clock fre- V. CONCLUSION
quency = 1 GHz, temp. = 27 ◦ C at TT corner). The nor- A dual-edge-triggered flip-flop for high energy efficiency
malized areas of the 7 DET-FFs are compared based on the and robust near-threshold operation is proposed in this paper.
layout sizes shown in Fig. 8 (FS-TSPC-DET FF = ‘1’). Unlike most of the conventional DET-FFs, such as the
The area is not directly proportional to the transistor counts Pulsed-latch-type or Latch-MUX-type DET-FF using a com-
since some designs require careful transistor sizing for robust plementary two-phase clock, the proposed FS-TSPC-DET
operation, especially when they have contention. Thanks to FF utilizes a true single-phase clock and implements a fully
their symmetric and static structure, Latch-MUX-type DET- static structure without floating state and contention. The
FFs (the SDET FF, TSPC-SDET FF and FS-TSPC-DET FF) comprehensive post-layout analysis of the DET FFs imple-
can have smaller layout areas compared to other DET-FF mented in 28nm CMOS technology showed that the proposed
designs despite the use of a large number of transistors. FS-TSPC-DET FF achieves excellent power-delay trade-off
The proposed FS-TSPC-DET FF has low power con- and high tolerance against PVT variation, thanks to the simple
sumption comparable to the best performing FN_C-DET FF. and fully static implementation. Extensive comparison with
In addition, it also has low CLK-to-Q delay comparable to the prior-art DET-FFs confirmed that the proposed DET-FF can
best performing TSPC-SDET FF, resulting in the lowest PDP operate at the lowest voltage of 0.28 V for a temperature
for α = 10% and 50% and second lowest PDP for α = 25%. range of −40 ◦ C to 120 ◦ C, making it an excellent candidate
Besides the excellent trade-off between power and perfor- as an energy-efficient flip-flop for energy/cost-sensitive IoT
mance, the proposed FS-TSPC-DET FF also exhibits robust applications.
operation at low voltage. Thanks to its fully static design
without contention, the minimum operational supply voltage
was as low as 0.28 V. Such high energy efficiency and wide ACKNOWLEDGMENT
voltage scalability suggest that the proposed FS-TSPC-DET The authors would like to thank the IC Design Education
FF not only consumes relatively lower power compared to Center (IDEC), South Korea, for providing EDA tool.

VOLUME 8, 2020 40243

 Y. Lee et al.: Fully Static True-Single-Phase-Clocked DET-FF for Near-Threshold Voltage Operation in IoT Applications

REFERENCES [22] S. Muthukumar and G. Choi, ‘‘Low-power and area-efficient 9-transistor

double-edge triggered flip-flop,’’ IEICE Electron. Express, vol. 10, no. 18,
[1] J. L. Shin, R. Golla, H. Li, S. Dash, Y. Choi, A. Smith, H. Sathianathan,
2013, Art. no. 20130639.
M. Joshi, H. Park, M. Elgebaly, S. Turullols, S. Kim, R. Masleid,
[23] S. V. Devarapalli, P. Zarkesh-Ha, and S. C. Suddarth, ‘‘A robust and low
G. K. Konstadinidis, M. J. Doherty, G. Grohoski, and C. McAllister,
power dual data rate (DDR) flip-flop using c-elements,’’ in Proc. 11th Int.
‘‘The next generation 64b SPARC core in a t4 SoC processor,’’ IEEE J.
Symp. Qual. Electron. Design (ISQED), San Jose, CA, USA, Mar. 2010,
Solid-State Circuits, vol. 48, no. 1, pp. 82–90, Jan. 2013.
pp. 147–150.
[2] E. D. Korczynski, ‘‘IoT demands: Are we ready?’’ Solid State Technol.,
[24] S. Lapshev and S. M. R. Hasan, ‘‘New low glitch and low power DET
vol. 59, no. 4, pp. 19–23, Jun. 2016.
flip-flops using multiple C-elements,’’ IEEE Trans. Circuits Syst. I, Reg.
[3] Y. Kim, ‘‘A static contention-free single-phase-clocked 24T flip-flop in Papers, vol. 63, no. 10, pp. 1673–1681, Oct. 2016.
45 nm for low-power applications,’’ in IEEE Int. Solid-State Circuits [25] M. Afghahi and J. Yuan, ‘‘Double-edge-triggered D-flip-flops for
Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, USA, Feb. 2014, high-speed CMOS circuits,’’ IEEE J. Solid-State Circuits, vol. 26, no. 8,
pp. 466–467. pp. 1168–1170, 1991.
[4] N. Kawai, S. Takayama, J. Masumi, N. Kikuchi, Y. Itoh, [26] J.-S. Wang, ‘‘A new true-single-phase-clocked double-edge-triggered
K. Ogawa, A. Ugawa, H. Suzuki, and Y. Tanaka, ‘‘A fully static flip-flop for low-power VLSI designs,’’ in Proc. IEEE Int. Symp. Circuits
topologically-compressed 21-transistor flip-flop with 75% power Syst. (ISCAS), Jun. 1997, pp. 1896–1899.
saving,’’ IEEE J. Solid-State Circuits, vol. 49, no. 11, pp. 2526–2533, [27] A. Bonetti, A. Teman, and A. Burg, ‘‘An overlap-contention free true-
Nov. 2014. single-phase clock dual-edge-triggered flip-flop,’’ in Proc. IEEE Int. Symp.
[5] F. Stas and D. Bol, ‘‘A 0.4-V 0.66-fJ/cycle retentive true-single-phase- Circuits Syst. (ISCAS), Lisbon, May 2015, pp. 1850–1853.
clock 18T flip-flop in 28-nm fully-depleted SOI CMOS,’’ IEEE Trans. [28] T. D. Burd, T. A. Pering, A. J. Stratakos, and R. W. Brodersen,
Circuits Syst. I, Reg. Papers, vol. 65, no. 3, pp. 935–945, Mar. 2018. ‘‘A dynamic voltage scaled microprocessor system,’’ IEEE J. Solid-State
[6] Y. Cai, A. Savanth, P. Prabhat, J. Myers, A. S. Weddell, and Circuits, vol. 35, no. 11, pp. 1571–1580, Nov. 2000.
T. J. Kazmierski, ‘‘Ultra-low power 18-transistor fully static [29] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, ‘‘Low-power CMOS
contention-free single-phase clocked flip-flop in 65-nm CMOS,’’ digital design,’’ IEEE J. Solid-State Circuits, vol. 27, no. 4, pp. 473–484,
IEEE J. Solid-State Circuits, vol. 54, no. 2, pp. 550–559, Feb. 2019. Apr. 1992.
[7] P. Xu, C. Gimeno, and D. Bol, ‘‘Optimizing TSPC frequency dividers for [30] W. Wang and P. Mishra, ‘‘System-wide leakage-aware energy minimiza-
always-on low-frequency applications in 28 nm FDSOI CMOS,’’ in Proc. tion using dynamic voltage scaling and cache reconfiguration in multitask-
IEEE SOI-3D-Subthreshold Microelectron. Technol. Unified Conf. (SS), ing systems,’’ IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20,
Burlingame, CA, USA, Oct. 2017, pp. 1–2. no. 5, pp. 902–910, May 2012.
[8] M. Alioto, E. Consoli, and G. Palumbo, ‘‘DET FF topologies: A detailed [31] S. Paul, V. Honkote, R. Kim, T. Majumder, P. Aseron, V. Grossnickle,
investigation in the energy-delay-area domain,’’ in Proc. IEEE Int. Symp. R. Sankman, D. Mallik, S. Jain, S. Vangal, J. Tschanz, and V. De,
Circuits Syst. (ISCAS), Rio de Janeiro, Brazil, May 2011, pp. 563–566. ‘‘An energy harvesting wireless sensor node for IoT systems featuring a
[9] T. A. Johnson and I. S. Kourtev, ‘‘A single latch, high speed double-edge near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS,’’
triggered flip-flop (DETFF),’’ in Proc. 8th IEEE Int. Conf. Electron., in Proc. IEEE Symp. VLSI Circuits (VLSI-Circuits), Honolulu, HI, USA,
Circuits Syst. (ICECS), Malta, Sep. 2001, pp. 189–192 vol. 1. Jun. 2016, pp. 1–2.
[10] Y.-Y. Sung and R. C. Chang, ‘‘A novel CMOS double-edge triggered [32] N. Lotze and Y. Manoli, ‘‘Ultra-sub-threshold operation of always-on
flip-flop for low-power applications,’’ in Proc. IEEE Int. Symp. Circuits digital circuits for IoT applications by use of schmitt trigger gates,’’
Syst. (ISCAS), May 2004, p. 665. IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 64, no. 11, pp. 2920–2933,
[11] M. W. Phyu, K. Fu, W. L. Goh, and K.-S. Yeo, ‘‘Power-efficient Nov. 2017.
explicit-pulsed dual-edge triggered sense-amplifier flip-flops,’’ IEEE [33] Y. Shi, M. Choi, Z. Li, Z. Luo, G. Kim, Z. Foo, H.-S. Kim, D. Wentzloff,
Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 1, pp. 1–9, and D. Blaauw, ‘‘A 10 mm3 inductive-coupling near-field radio for
Jan. 2011. syringe-implantable smart sensor nodes,’’ IEEE J. Solid State Circuits,
vol. 51, no. 11, pp. 2570–2583, Sep. 2016.
[12] X.-X. Wu and J.-Z. Shen, ‘‘Low-power explicit-pulsed triggered flip-flop
[34] Y. Lee, S. Bang, I. Lee, Y. Kim, G. Kim, M. H. Ghaed, P. Pannuto,
with robust output,’’ Electron. Lett., vol. 48, no. 24, pp. 1523–1525,
P. Dutta, D. Sylvester, and D. Blaauw, ‘‘A modular 1 mm3 die-stacked
Nov. 2012.
sensing platform with low power I2 C inter-die communication and
[13] H. Partovi, R. Burd, U. Salim, F. Weber, L. DiGregorio, and D. Draper, multi-modal energy harvesting,’’ IEEE J. Solid-State Circuits, vol. 48,
‘‘Flow-through latch and edge-triggered flip-flop hybrid elements,’’ in no. 1, pp. 229–243, Jan. 2013.
IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 1996, [35] M. Cho, ‘‘A 6×5×4 mm3 general purpose audio sensor node with a 4.7µW
pp. 138–139. audio processing IC,’’ in Proc. Symp. VLSI Circuits, Kyoto, Japan, 2017,
[14] F. Klass, C. Amir, A. Das, K. Aingaran, C. Truong, R. Wang, A. Mehta, pp. C312–C313.
R. Heald, and G. Yee, ‘‘A new family of semidynamic and dynamic [36] Y. Suzuki, K. Odagawa, and T. Abe, ‘‘Clocked CMOS calculator cir-
flip-flops with embedded logic for high-performance processors,’’ IEEE cuitry,’’ IEEE J. Solid-State Circuits, vol. 8, no. 6, pp. 462–469, Dec. 1973.
J. Solid-State Circuits, vol. 34, no. 5, pp. 712–716, May 1999. [37] M. Alioto, E. Consoli, and G. Palumbo, ‘‘Analysis and comparison in
[15] C. Kim and S.-M. Kang, ‘‘A low-swing clock double-edge triggered flip- the energy-delay-area domain of nanometer CMOS flip-flops: Part I—
flop,’’ IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 648–652, May 2002. Methodology and design strategies,’’ IEEE Trans. Very Large Scale Integr.
[16] P. Zhao, J. McNeely, P. Golconda, M. A. Bayoumi, R. A. Barcenas, and (VLSI) Syst., vol. 19, no. 5, pp. 725–736, May 2011.
W. Kuang, ‘‘Low-power clock branch sharing double-edge triggered flip-
flop,’’ IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 15, no. 3,
pp. 338–345, Mar. 2007.
[17] N. Nedovic, M. Aleksic, and V. G. Oklobdzija, ‘‘Conditional pre-charge
techniques for power-efficient dual-edge clocking,’’ in Proc. Int. Symp.
Low Power Electron. Design (ISLPED), 2002, pp. 56–59.
[18] J.-F. Lin, ‘‘Low-power pulse-triggered flip-flop design using gated pull-up
control scheme,’’ Electron. Lett., vol. 47, no. 24, p. 1313, 2011. YONGMIN LEE (Student Member, IEEE)
[19] A. Gago, R. Escano, and J. A. Hidalgo, ‘‘Reduced implementation of received the B.S. degree in biomedical engineer-
D-type DET flip-flops,’’ IEEE J. Solid-State Circuits, vol. 28, no. 3, ing from Konyang University, Daejeon, South
pp. 400–402, Mar. 1993. Korea, in 2016, and the M.S. degree in elec-
[20] R. Hossain, L. D. Wronski, and A. Albicki, ‘‘Low power design using tronic, electrical, and computer engineering from
double edge triggered flip-flops,’’ IEEE Trans. Very Large Scale Integr. Sungkyunkwan University, Suwon, South Korea,
(VLSI) Syst., vol. 2, no. 2, pp. 261–265, Jun. 1994. in 2019. His research interests include low-power
[21] R. P. Llopis and M. Sachdev, ‘‘Low power, testable dual edge triggered flip- circuit design and digital VLSI design.
flops,’’ in Proc. Int. Symp. Low Power Electron. Design (ISLPED), 1996,
pp. 341–345.

40244 VOLUME 8, 2020

Y. Lee et al.: Fully Static True-Single-Phase-Clocked DET-FF for Near-Threshold Voltage Operation in IoT Applications

GICHEOL SHIN (Student Member, IEEE) YOONMYUNG LEE (Senior Member, IEEE)
received the B.S. degree in electrical engineering received the B.S. degree in electronic and electrical
from Sungkyunkwan University, Suwon, South engineering from the Pohang University of Sci-
Korea, in 2017, where he is currently pursuing the ence and Technology (POSTECH), Pohang, South
joint M.S./Ph.D. degree in electronic, electrical, Korea, in 2004, and the M.S. and Ph.D. degrees
and computer engineering. His research inter- in electrical engineering from the University of
ests include ultra-low-power circuit and hardware Michigan, Ann Arbor, in 2008 and 2012, respec-
accelerator design for deep learning applications. tively.
From 2012 to 2015, he was a Research Faculty
with the University of Michigan and performed
research on ultra-low-power circuit design for mm-scale sensor platforms.
In 2013, he co-founded CubeWorks Inc., a start-up company specialized in
mm-scale sensor platforms. In 2015, he joined Sungkyunkwan University,
Suwon, South Korea, where he is currently an Associate Professor. His cur-
rent research interests include energy-efficient integrated circuits design for
low-power high-performance VLSI systems and millimeter-scale wireless
sensor systems. He has been serving as a Technical Program Committee
Member for A-SSCC, since 2017. He has received numerous awards and
scholarships, including the Distinguished Undergraduate Scholarship from
the Korea Foundation for Advanced Studies, in 2001, the Samsung Scholar-
ship, in 2005, the Best Paper Award in ISLPED, in 2009, the DAC/ISSCC
Student Design Contest, in 2009 and 2011, the Intel Ph.D. Fellowship,
in 2011, and the Samsung Human Tech Thesis Contest Silver Award, in 2012.
He has been serving as an Associate Editor for the IEEE TRANSACTIONS ON
VERY LARGE SCALE INTEGRATION SYSTEMS, since 2019.

VOLUME 8, 2020 40245