A 1.

2 V 285µA Analog Front End Chip for a

Digital Hearing Aid in 0.13 µm CMOS
Amrith Sukumaran, Kunal Karanjkar, Sandeep Jhanwar, Nagendra Krishnapura, Shanthi Pavan
Dept. of Electrical Engineering, Indian Institute of Technology Madras, Chennai 600036, India.

Abstract— We describe a low power analog front-end for Bandgap

LDO VCO
Mic. Bias Low Bat.
Reference Generator Monitor
a digital hearing aid, designed and fabricated in a 0.13 µm CMOS
t.coil speaker
process. The IC accepts inputs from a microphone or telecoil,
amplifies and digitizes it for processing by a DSP, accepts digital PGA CTDSM &
PCM-to-PWM Class-D
Decimator Driver
data from the DSP, converts it to analog form using a pulse
width modulated class D amplifier, and drives the earpiece, all mic
to/from
over a 10 kHz bandwidth. The programmable gain amplifier uses SPI Interface DSP
current sharing in the input stage to obtain low noise with low
power consumption. The single-bit continuous-time ΔΣ ADC and
the closed loop class-D amplifier use assisted opamp integrators Fig. 1. Architecture of the chip.
to reduce power dissipation. An on chip ring oscillator provides
the clock to the digital parts of the chip and to the digital signal
processor (DSP). The chip has an input referred noise of 2.1 µV,
a dynamic range of 106 dB, an output THD of 0.006 % and a a closed loop class-D H-Bridge driver converts the digital
peak output SNR of 79 dB. It occupies 2.3 mm2 and consumes signal from the DSP and drives the earphone. An on-chip
285 µA from a 1.2 V supply. oscillator provides a clock to the digital parts of the chip as
well as to the DSP. The chip also includes a low dropout
I. I NTRODUCTION regulator (LDO) and bias generation circuits which provide
A majority of present day hearing aids are of the bias to the analog portions of the chip and the microphone. A
digitally programmable type which utilize digital signal pro- four wire serial peripheral interface (SPI) is used to control the
cessing for tuning the frequency response over multiple bands, chip and communicate the data. Details of some key blocks
and to provide features such as echo and noise cancellation. and our approaches to obtain low noise and distortion with a
Such a hearing aid requires an analog front-end consisting low power consumption are described in the rest of the paper,
of an analog to digital conversion chain which amplifies the which is organized as follows.
analog signal from the microphone, digitizes it, and forwards Section II describes the PGA and the ADC. Section III
it to the digital signal processor (DSP), and a digital to analog describes the PWM class-D audio driver. The oscillator and
conversion chain which receives the processed data from the references are briefly described in Section IV. Section V
DSP, converts it to analog, and drives the earphone. Key shows the measured results. Section VI compares the work
requirements of the analog to digital conversion chain are presented here to previously published hearing aid front-end
low input referred noise, gain programmable in fine steps to ICs and concludes the paper.
support a high dynamic range (> 100 dB), and a sufficiently
high signal to noise and distortion ratio. The digital to
II. PGA AND ADC
analog conversion chain must have a low output distortion
and noise. For extended battery life, low power consumption Fig. 2(a) shows the PGA. It is a fully differential
is an overarching requirement for all parts of the hearing inverting amplifier using an opamp. The input from the
aid electronics. This paper describes a low-power low-noise microphone or telecoil is single-ended and drives one of the
analog front-end chip for a digitally programmable hearing inputs. The other input is terminated at the common mode.
aid. The differential output drives the ADC. The PGA gain is
Fig. 1 shows the architecture of our hearing aid front varied from −1 dB to 40 dB in steps of 0.5 dB. For the highest
end IC. A −1 to 40 dB programmable gain amplifier (PGA) gain of 40 dB, R1 and R2 are chosen to be 10 kΩ and 1 MΩ.
with 0.5 dB gain steps[1] followed by a 13 bit continuous- This results in an input referred noise of about 2 µV for
time delta sigma ADC digitizes the incoming signal. The chip small inputs when the PGA is operated with its maximum
accepts signals from either a microphone or a telecoil. The gain. While the gain steps are required to be logarithmic,
latter picks up the audio signal directly from a coil inside having equal resistor increments is convenient for layout. To
a (telecoil equipped) phone. Consequently, audio quality is satisfy both these constraints, the well known approximation
improved for telephone conversations, even with ambient exp(x) ≈ (1 + x/2)/(1 − x/2) is used. Let R10 and R20 be the
noise. A digital pulse width modulator (PWM) followed by input and feedback resistor values for a certain gain G0 dB.
To reduce the gain by k steps of 0.5 dB, the resistor ratio has
E-mail: [email protected]; This work was supported in part by the
Ministry of Communication and Information Technology, Government of to be changed by 10k/40 , or, equivalently, exp (k ln(10)/40).
India. The resistor ratio required to obtain this new gain value of

978-1-4799-0280-4/13/$31.00 2013
c IEEE 397
 vdda
transistors M4a,4b would be driven into triode region in certain
(a) biasp
corners due to very low VGS of M5a,5b and the dc gain would
a[14-0] a[12-0]
Vmic be significantly lowered. The dc drop across Rb prevents this
R1 R2 M3a M3b occurrence. The opamp has an input referred noise of 1 µV,
a[14-0] vp1 vm1
Vtele B
vom
R1 A mux + - supports a 400 mVppd output swing, provides a closed loop
Vcm m vm2 vp2 bandwidth of 5.5 MHz at the highest gain, and consumes
- + vop
R1 25 µW from 1.2 V.
M4a M4b
a[14-0] R2
Ra
m=1: Microphone Vin Vin/ R1
-gm
m=0: Telecoil a[12-0] Asst. Vin Rf1
C1 C2 C3
gnda
Vin − − −
Cm1
D
Cm2 R1 A1 R2 A2 R3 A3
(a) + + +

vm2 Rm
vip vm1 vop
+ - + - + -

DACa

DAC3
DAC2
DAC1
(b) Gm1 Gm2 Gm3 Asst.
DAC
vim - + vp1 - + vp2 - + vom
Rm
Cm2
Cm1 (b)
MSB
D
vdda vdda H1(z) 32 H2(z) 2 H3(z) H4(z) H5
1 21 24 24 24 24 16
sinc4 filter halfband filter FIR LPF IIR HPF K
Scaling Block

M1a M1b
C2a C2b Fig. 3. (a) Continuous-time ΔΣ ADC and (b) block diagram of the
C1a C1b
decimation filter.
vip vom vop
vim CMFB2
vm1 vp1
CMFB1 Fig. 3(a) shows the single-ended equivalent of the
vp2 vm2
M2a M2b
M5a M5b continuous-time ΔΣ ADC. A third-order modulator with cas-
cade of integrators with feedback to each integrator (CIFB)
biasn
Rb structure, a 1-bit quantizer, and an oversampling ratio (OSR)
of 128 are used. The first opamp has to supply large currents
gnda gnda
due to the 1-bit feedback DAC. To maintain a low distortion
Fig. 2. (a) Programmable gain amplifier (b) Schematic of the nested Miller with a low power consumption, a replica DAC and gm (shown
compensated opamp used in the PGA. in gray in Fig. 3(a)) provide assistance [3] to the first opamp.
The current provided by the latter is significantly reduced,
lowering the distortion. This technique, along with the use of
G0 − k · 0.5 dB is feedforward compensated opamps in the loop filter enable a
R20 R20 (1 − k ln(10)/40) low power consumption of 36 µW for a peak SNDR of 87 dB.
exp (k ln(10)/40) ≈
R10 R10 (1 + k ln(10)/40) The decimation filter has a fourth order sinc filter
followed by a half-band filter and an FIR lowpass filter. It also
Therefore, for each 0.5 dB decrease in gain, the input resistor
has an optional high-pass filter (HPF) to remove DC offsets
has to be increased by R10 ln(10)/40 and the feedback resistor
accumulated by the PGA and ADC. The last stage scales the
has to be reduced by R20 ln(10)/40. In other words, the resis-
output of the ΔΣ modulator at its maximum stable amplitude
tors change in constant steps. To maintain the approximation
to full scale.
error within bounds, the entire gain range is segmented into
4 dB subranges where the stepping described above is used. III. DAC AND C LASS D AUDIO DRIVER
Fig. 2(b) shows the opamp used in the PGA. Since
40 kHz 640 kHz 640 kHz 20.48 MHz
the closed loop gain is as high as 40 dB, a three stage opamp
with nested Miller compensation[2] is chosen in order to have Digital
input 20 16x 23 Algorithmic 23 Digital 5 Dpwm
a sufficiently high dc loop gain. The first stage uses both x[n] Interpol. PWM ΔΣ
UPWM
s[n] y[n] z[n]
pMOS and nMOS differential pairs which share a common (a)
bias current. This reduces the input referred noise for a given tri(t)
bias current. Since the PGA is driven by a single-ended signal, s[n],x[16n] s[n]
y[n]
the common mode input of the opamp is large, approximately (b) s[n-1]
m(t)
equal to half the input signals for large gains. To maintain the n
0 16
input transistors M1a,2a,1b,2b in saturation, the output common
n-1 n
mode voltage of the first stage is set to be equal to the input
common mode voltage of the opamp. The second stage uses Fig. 4. (a) Digital pulse width modulator and (b) details of the algorithmic
a pMOS differential pair. The third stage uses an nMOS pulse width modulator.
differential pair M5a,5b with a resistor Rb in the tail. If M5a,5b
were in a common source configuration with their source Pulse width modulation followed by class-D amplifi-
terminals at ground as is commonly done, the second stage cation is an efficient technique for digital to analog conversion

398 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)

of low frequency signals. Natural sampling, in which the is used to reduce distortion and supply sensitivity. Instead
pulse widths are determined by instants at which the input of comparing the output of the loop filter with a triangular
signal crosses a high frequency sawtooth wave, results in carrier, a square wave is input to the second integrator[6].
distortion free pulse-width modulation ([4], [5]). For linearity, This avoids the generation of the triangular wave. In this
PWM has to be carried out in the digital domain, because a architecture, both integrators have to supply step-like currents
perfectly linear sawtooth waveform is difficult to obtain in to their integrating capacitors. To reduce the consequent
the analog domain. To retain the potential efficiency of this nonlinearity, both opamps are assisted by replica currents
technique, the maximum clock frequency of the digital blocks from DACa and DACa1 which supply the step-like currents[3].
has to be restricted. Fig. 4(a) shows our implementation of Fig. 5(b) shows the comparator. It is a two stage
the pulse width modulator. The 20 bit PCM input x[n] at design with an nMOS input differential pair followed by
40 kHz from the DSP is interpolated to s[n] at 640 kHz. pMOS common source amplifiers. CMOS inverters are used
The algorithmic PWM block determines the cross points of at the output to obtain rail-rail digital output. The H-bridge
s[n], linearly interpolated between sucessive samples, with an transistors are driven from a non-overlap generator to prevent
ideal sawtooth wave at 640 kHz. Fig. 4(b) shows the details. crowbar currents.
The input samples are shown in red and the interpolated
samples are shown in black. The figure on the right shows the IV. O SCILLATOR AND REFERENCES
crossing of s[n], linearly interpolated between samples, and The chip contains a 20.48 MHz ring oscillator for
the sawtooth wave. y[n] which represents the cross point is clocking the ΔΣ ADC and the digital portions of the chip.
given by It is powered by an on chip low dropout regulator (LDO). An
s[n − 1] + s[n] on chip fractional bandgap reference is used to provide bias
y[n] = P to the LDO and the microphone. The ring oscillator is sized
2P + s[n − 1] − s[n]
1 to have a sufficiently low jitter such that the signal to jitter
≈ (s[n − 1] + s[n]) (2P + s[n] − s[n − 1]) induced noise in the ΔΣ ADC is 89 dB.
4P
where 2P is the peak-peak value of the sawtooth wave. V. M EASURED RESULTS
This second, approximate, expression is used to avoid digital
division. It is valid for |s[n] − s[n − 1]|  2P, which is true
in this case due to interpolation to a high frequency. A pulse
train whose pulse widths are proportional y[n] is a faithful
PWM representation of the input x[n]. But, since y[n] is 23 bit
wide, generating such a waveform requires an impractically
high clock frequency. y[n] is fed to a digital ΔΣ modulator
with a 5-bit (32 level) output z[n], also at 640 kHz. This is
converted to uniform PWM at a clock rate of 32 × 640 kHz
= 20.48 MHz.

Vdd DACa1
0 Rtri +/-Vdd/(2Rtri)
non
C1 Cz C2 overlap Vdd
gen.
Dpwm
− − speaker
Rin A1 R2 A2
+ +

Rin 1/2 H-bridge

DACa

Asst.
DAC
(a)
vdda

biasp vop1 vom1

Fig. 6. Test board and chip layout.
v vop2 vom
vop1 vom1 om2
(b) vop
Mc1 Mc2 The chip is fabricated in a 0.13 µm CMOS process.
CMFB
Fig. 6 shows the layout of the chip and the test board used for
vim vip
characterization. The chip occupies 2.3 mm2 and consumes
285 µA (195 µA analog, 90 µA digital) from a 1.2 V supply.
biasn
gnda The chip is placed in loopback mode by driving the DAC
input with the decimation filter’s output. The entire signal
Fig. 5. (a) Simplified schematic of the Class-D amplifier and (b) comparator. chain is then characterized with analog input and output at
1 kHz. Fig. 7 shows the output SN(D)R versus the normalized
The PWM waveform so generated is fed to the class-D input amplitude for PGA gains of −1, 20, and 40 dB. The
amplifier in Fig. 5. A second-order closed loop architecture (unweighted) input referred noise for the highest gain setting

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) 399

 is 2.1 µV and the dynamic range which can be covered with VI. C OMPARISON AND CONCLUSIONS
a suitable AGC in the DSP is 106 dB. The peak SNR and Table I summarizes the results of our chip and com-
SNDR are 79 dB and 76 dB respectively. The input referred pares it to other published hearing aid front end ICs. [1] is
noise is dominated by the PGA for gains higher than 25 dB a complete hearing aid chip. The others in the table describe
and by the ΔΣ ADC for lower gains. Fig. 8 shows the output parts of a hearing aid chip. The frontend IC presented here
spectrum of the class D amplifier driving a 1 kHz 1.6 Vppd has the lowest input referred noise for the analog to digital
sinusoid. Under these conditions (which do not correspond to conversion chain and the lowest THD and noise for the digital
the peak values) the SNR and SNDR in a 10 kHz bandwidth to analog conversion chain. These are due to current sharing in
are 74.5 dB (unweighted). The inset in the figure shows the the input stage of the opamp in the PGA, use of feedforward
spectrum at the output of the decimation filter. compensated opamps and opamp assistance techniques in the
The noise and distortion values mentioned above are ΔΣ ADC and the class-D amplifier.
dominated by the PGA and ADC. When a 1 kHz digital
sinusoid is externally applied to the class-D amplifier, it has TABLE I
an SNR of 85 dB and a THD+N of 0.0056% at a 1.3 Vppd P ERFORMANCE SUMMARY AND COMPARISON
output.
This work [1] [7] [8] [9]
System Analog FE Analog FE Analog FE Class-D Class-D
+ dig. filter (PGA+ADC) amplifier amplifier
80 Process 0.13 µm 0.6 µm 0.25 µm 0.35 µm 0.13 µm
Supply (V) 1.2 1.1 0.9 1.1 1.2
Area ( mm2 ) 2.3 12 0.5 0.46 1.15
70
Power ( µW) 342 297 75 31 380
BW (kHz) 10 10 8
60 PGA -1 dB - 40 dB -1 dB - 40 dB Continuous
0.5 dB steps 0.5 dB steps
50 ADC CT ΔΣ DT ΔΣ DT ΔΣ
DAC PWM Digital ΔΣ PWM Digital ΔΣ
+ Digital ΔΣ + open loop Digital ΔΣ + Analog ΔΣ
40
SNDR (dB)

+ CT cl. loop class-D + open loop cl. loop

class-D class-D
30 Noise ( µV rms) 2.1 2.8 3.8
PGA : 40 dB SNRmax (dB) 79 — 79
20 PGA : 20 dB SNDRmax (dB) 76 — 73
DR (dB) 106 —
PGA : −1dB SNR dB — 87.2
10
THD (%) 0.0063 0.02 0.0067
THD+N (%) 0.016 0.02 0.008
0
For our work, the input ref. noise is at the highest PGA gain; All other numbers correspond to peak SNR in Fig. 7;
−10 For [1], the input referred noise is at the highest PGA gain; THD is at 4 mV peak input and 34 dB PGA gain;
Dynamic Range = 106 dB
For [7], the input referred noise is for the PGA; SNRmax and SNDRmax are for the ADC, estimated from figures;
−20
−120 −100 −80 −60 −40 −20 For [8], [9], the numbers refer only to the class-D amplifier
Amplitude (dBFS)

Fig. 7. Dynamic range of the fronted IC for three PGA gain settings - the R EFERENCES
dynamic range (unweighted) is 106 dB.
[1] D. G. Gata et al., “A 1.1-V 270-µA mixed-signal hearing aid chip,”
IEEE Journal of Solid State Circuits, vol. 37, no. 12, pp. 1670-1678,
Dec. 2002.
[2] K. N. Leung et al., “Analysis of multistage amplifier frequency com-
pensation,” IEEE Transactions on Circuits and Systems-I:Fundamental
Theory and Applications, vol. 48, no. 9, pp. 1041-1056, Sep. 2001.
[3] S. Pavan and P. Sankar, “Power reduction in continuous-time delta-
sigma modulators using the assisted opamp technique,” IEEE Journal
of Solid State Circuits, vol. 45, no. 7, pp. 1365-1379, July 2010.
[4] H. S. Black, Modulation Theory, D. Van Nostrand Company, Inc., First
edition, 1953.
[5] M. B. Sandler, “Digital-to-analogue conversion using pulse width
modulation,” Electronics Communication Engineering Journal, vol.5,
no.6, pp. 339-348, Dec. 1993.
[6] M. Berkhout, “An integrated 200W class D audio amplifier,” Proc. 2002
ESSCIRC, Sep. 2002, pp. 511-514.
[7] S. Kim et al., “An energy-efficient analog front-end circuit for a sub-1-
V digital hearing aid chip,” IEEE Journal of Solid-State Circuits, vol.
41, no. 4, pp. 876-882, April 2006.
[8] V. Adrian, et al., “A low voltage micropower digital class-D amplifier
modulator for hearing aids,” IEEE Transactions on Circuits and Systems
I: Regular Papers, vol. 56, no. 2, pp. 337-349, Feb. 2009.
[9] J. Noh et al., “A Class-D amplifier with pulse code modulated (PCM)
digital input for a digital hearing aid,” IEEE Journal of Solid State
Fig. 8. Class-D output spectrum in loopback mode, for a PGA gain of Circuits, vol. 58, no. 2, pp. 465-472, Feb. 2013.
-1 dB. The inset shows the PSD at the decimator output.

400 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)