User's Guide

SLVU799 – November 2012

Using the TPS43061 Boost Evaluation Module (EVM)

This user's guide contains information for the TPS43061EVM-198 evaluation module (PWR198) including
the performance specifications, schematic, and the bill of materials.

Contents
1 Introduction .................................................................................................................. 2
2 Test Setup and Results .................................................................................................... 4
3 Schematic and Bill of Materials .......................................................................................... 10
4 Board Layout ............................................................................................................... 12

List of Figures
1 Efficiency Versus Load Current ........................................................................................... 5
2 Regulation Versus Output Current ........................................................................................ 6
3 Regulation Versus Input Voltage.......................................................................................... 6
4 Load Transient Response ................................................................................................. 6
5 Loop Response ............................................................................................................. 6
6 Output Voltage Ripple CCM .............................................................................................. 7
7 Output Voltage Ripple DCM .............................................................................................. 7
8 Output Voltage Ripple Pulse Skip Mode ................................................................................. 7
9 Input Voltage Ripple CCM ................................................................................................. 8
10 Input Voltage Ripple DCM ................................................................................................. 8
11 Start Up Relative to VIN .................................................................................................... 8
12 Start Up Relative to EN .................................................................................................... 8
13 Shutdown Relative to VIN ................................................................................................... 9
14 Shutdown Relative to EN .................................................................................................. 9
15 Gate-Drive Signals ........................................................................................................ 10
16 TPS43061EVM-198 Schematic.......................................................................................... 10
17 TPS43061EVM-198 Top Assembly and Silkscreen .................................................................. 12
18 TPS43061EVM-198 Top-Side Layout .................................................................................. 13
19 TPS43061EVM-198 Layer 2 Layout .................................................................................... 13
20 TPS43061EVM-198 Layer 3 Layout .................................................................................... 14
21 TPS43061EVM-198 Bottom-Side Layout .............................................................................. 14

List of Tables
1 Input Voltage and Output Current Summary ............................................................................ 2
2 TPS43061EVM-198 Performance Specification Summary ............................................................ 2
3 EVM Connectors and Test points ......................................................................................... 4
4 TPS43061EVM-198 Bill of Materials .................................................................................... 11

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1 Introduction
This user's guide contains background information for the TPS43061 as well as support documentation for
the TPS43061EVM-198 evaluation module (PWR198). Also included are the performance specifications,
schematic, and the bill of materials for the EVM

1.1 Background
The TPS43061 is a DC-DC synchronous boost controller designed for a maximum output voltage of 60 V
from an input voltage source of 4.5 V to 38 V. It has a 5.5-V gate-drive supply optimized for use with low
Qg NexFETs. Rated input voltage and output current range for the evaluation module are given in Table 1.
This evaluation module is designed to demonstrate the small, printed-circuit-board areas that are possible
when designing with the TPS43061 controller. The switching frequency is externally set at a nominal 750
kHz. The gate-drive circuitry for the external high-side and low-side FET is incorporated inside the
TPS43061 package. The PWR198 uses the CSD86330Q3D NexFET power block integrating both the
high-side and low-side FETs. External inductor DCR or resistor current sensing allows for an adjustable
cycle-by-cycle current limit. The compensation components are external to the integrated circuit (IC), and
an external resistor divider allows for an adjustable output voltage. Additionally, the TPS43061 provides an
adjustable undervoltage lockout with hysteresis through an external resistor divider, adjustable slow-start
time with an external capacitor and a power good output voltage indicator. The absolute maximum input
voltage for the PWR198 based on the selected external components is 25 V.

Table 1. Input Voltage and Output Current Summary

EVM Input Voltage Range Output Current Range
TPS43061EVM-198 VIN = 6 V to 12.6 V IOUT = 0 A to 2 A

1.2 Performance Specification Summary

A summary of the EVM performance specifications is provided in Table 2. Specifications are given for an
input voltage of VIN = 9 V and an output voltage of 15 V, unless otherwise specified. This EVM is designed
and tested for VIN = 6 V to 12.6 V. The ambient temperature is 25°C for all measurements, unless
otherwise noted.

Table 2. TPS43061EVM-198 Performance Specification Summary

Specification Test Conditions MIN TYP MAX Unit
VIN voltage range 6 9 12.6 V
Output voltage set point 15 V
Output current range VIN = 6 V to 12.6 V 0 2 A
Line regulation IOUT = 2 A, VIN = 6 V to 12.6 V ±0.1%
Load regulation VIN = 9 V, IOUT = 0.001 A to 2 A ±0.1%
Load transient response IOUT = 0.5 A to 1.5 A Voltage change –300 mV
Recovery time 400 µs
IOUT = 1.5 A to 0.5 A Voltage change 210 mV
Recovery time 400 µs
Loop bandwidth VIN = 9 V, IOUT = 2 A 19 kHz
Phase margin VIN = 9 V, IOUT = 2 A 68 °
Input voltage ripple IOUT = 2 A 10 mVpp
Output voltage ripple IOUT = 2 A 70 mVpp
Output rise time 25 ms
Operating frequency 750 kHz

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Table 2. TPS43061EVM-198 Performance Specification Summary (continued)

Specification Test Conditions MIN TYP MAX Unit
Peak efficiency TPS43061EVM-198, VIN = 12 V, IOUT = 2 A 97%
DCM threshold VIN = 9 V 360 mA
Pulse skipping threshold VIN = 9 V 12 mA
No load input current VIN = 9 V 1.3 mA
UVLO start threshold 5.3 V
UVLO stop threshold 4.3 V

1.3 Modifications
These EVMs are designed to provide access to the features of the TPS43061. Some modifications can be
made to this module. For further details please see the product data sheet.

1.3.1 Output Voltage Set Point

To change the output voltage of the EVM, it is necessary to change the value of resistor R8. The value of
R8 for a specific output voltage can be calculated using Equation 1, where RHS is R8, RLS is R9 and VFB is
1.22 V. It s recommended to use a value of R9 near 10 kΩ.
V VFB
RHS RLS u OUT
VFB (1)
Note: VIN must be in a range so the minimum on-time is greater than the typical 100 ns and the minimum
off-time is greater than the largest of typical 250 ns and 5% of the switching period.

1.3.2 Current Sensing

The default configuration of the EVM is for resistor current sensing. R13 and R14 are populated with R15
open. When adjusting the input voltage, output voltage or desired maximum output voltage, the current
sense resistors R16 and R17 may need to be adjusted. The peak inductor current should first be
calculated with Equation 2. Equation 3 is then used to calculate the required current sense resistor where
VCStyp is the current sense threshold. VCStyp should be determined from the TPS43061 data sheet with
the maximum duty cycle in the application. Ensure the current sense resistor is rated for the expected
power dissipation. For inductor DCR current sensing, R14 should be left open while R15, R16 and R17
are shorted.
V VIN min
VIN minu OUT
IOUT VOUT
ILpeak
VOUT VIN min 2 u L u fSW
1
VOUT (2)
VCS typ
RCS
1.2 u ILpeak (3)

1.3.3 Slow-Start Time

Adjust the slow-start time by changing the value of C7. Equation 4 can be used to calculate the required
capacitance based on a desired slow-start time, tSS. ISS is the charging current of 5-µA typical and VREF is
the internal reference voltage of 1.22 V. The EVM is set for a slow-start time of 25 ms using C7 = 0.1 µF.
t SS u ISS
CSS
VREF (4)

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1.3.4 Adjustable UVLO

The undervoltage lockout (UVLO) can be adjusted externally using R3 and R4. The EVM is set for a start
voltage of 5.34 V and stop voltage of 4.31 V using R3 = 221 kΩ and R4 = 59.0 kΩ. Use Equation 5 and
Equation 6 to calculate the required resistor values for R3 and R4 respectively for different start and stop
voltages. The typical values of the constants in the two equations are as follows: VEN_DIS = 1.14 V, VEN_ON =
1.21 V, IEN_pup = 1.8 µA, and IEN_hys = 3.2 µA.
§ VEN _ DIS ·
VSTART u ¨ ¸ VSTOP
¨ VEN _ ON ¸
RUVLO_ H © ¹
§ VEN _ DIS ·
IEN _ pup u ¨ 1 ¸ I
¨ VEN _ ON ¸¹ EN _ hys
© (5)
RUVLO_ H u VEN _ DIS
RUVLO_ L
VSTOP VEN _ DIS RUVLO _ H u IEN _ pup IEN _ hys
(6)

1.3.5 Input Voltage Rails

The EVM is designed to accommodate different input voltage levels for the power stage and control logic.
During normal operation, the VIN inputs are the same with R11 shorted. The single input voltage is
supplied to J6. If desired, the two input voltage rails may be separated by removing R11. The control logic
input voltage can be supplied to J4 and the power stage input voltage to J6.

1.3.6 Further Modification

Be aware, changing the input and output of conditions of the EVM will impact the design. It may also be
necessary to modify the inductor, output capacitor and compensation components for the desired
performance in the application. Additionally the CSD86330Q3D power block limits the output voltage to a
maximum recommend output voltage of 22 V. Please see the data sheet or the excel design spreadsheet
located in the product folder for details.

2 Test Setup and Results

This section describes how to properly connect, set up, and use the EVM. The section also includes test
results typical for the EVM covering efficiency, output voltage regulation, load transients, loop response,
output ripple, input ripple, start up and shutdown.

2.1 Input/Output Connections

This EVM includes input/output connectors and test points as shown in Table 3. A power supply capable
of supplying at least 6 A must be connected to J6 through a pair of 20-AWG wires. The load must be
connected to J2 through a pair of 20-AWG wires. The maximum load-current capability must be 2 A. Wire
lengths must be minimized to reduce losses in the wires. If any modification is done to the EVM design, an
input supply and load rated for the new design are required. Test point TP8 provides a place to monitor
the VIN input voltages with TP9 providing a convenient ground reference. TP3 is used to monitor the output
voltage with TP4 as the ground reference.

Table 3. EVM Connectors and Test points

Reference Designator Function
J1 2-pin header for VOUT voltage connections
J2 VOUT, 15 V at 2-A maximum
J3 2-pin header for GND connections
J4 2-pin header for optional VBIAS input voltage connections (see Section 1.3.5 )
J5 2-pin header for VIN input voltage connections
J6 VIN (see Table 1 for VIN range)
J7 2-pin header for GND connections
JP1 3-pin header for EN jumper. Install jumper from pins 1-2 to enable or pins 2-3 to disable.

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Table 3. EVM Connectors and Test points (continued)

Reference Designator Function
TP1 PGOOD test point for power good output voltage indicator
TP2 HDRV test point for high-side gate-drive voltage
TP3 VOUT test point at VOUT connector
TP4 GND test point at VOUT connector
TP5 SW test point for switch node voltage
TP6 Test point between voltage divider network and output used for loop response measurements.
TP7 LDRV test point for low-side gate-drive voltage
TP8 VIN test point at VIN connector
TP9 GND test point at VIN

2.2 Efficiency
The efficiency of this EVM peaks at a load current of about 2 A with VIN = 12 V, and then decreases as the
load current increases towards maximum load. Figure 1 shows the efficiency for the EVM brought to
current limit for each input voltage. Measurements are taken at ambient temperature of 25°C. The
efficiency may be lower at higher ambient temperatures due to temperature variation in the drain-to-source
resistance of the selected external MOSFETs.
100

95
Efficiency - %

90

85
VOUT = 15 V, fsw = 750 kHz
80
VIN = 6 V

75 VIN = 9 V
VIN = 12 V
70
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Output Current - A C001

Figure 1. Efficiency Versus Load Current

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2.3 Output Voltage Regulation

The load regulation for the EVM is shown in Figure 2. The line regulation for the EVM is shown in
Figure 3. Measurements are given for an ambient temperature of 25°C.

0.1 0.1
VOUT = 15 V, fsw = 750 kHz VOUT = 15 V, fsw = 750 kHz
0.08 0.08

Output VOltage Deviation - %

Output Voltage Deviation - %

VIN = 9 V IOUT = 2 A
0.06 0.06
0.04 0.04
0.02 0.02
0 0
-0.02 -0.02
-0.04 -0.04
-0.06 -0.06
-0.08 -0.08
-0.1 -0.1
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 6 7 8 9 10 11 12 13
Output Current - A C002 Input Voltage - V C003

Figure 2. Regulation Versus Output Current Figure 3. Regulation Versus Input Voltage

2.4 Load Transients and Loop Response

The EVM response to load transients is shown in Figure 4. The current step is from 25% to 75% of
maximum rated load at 9 V input. The current step-slew rate is 100 mA/µs. Total peak-to-peak voltage
variation is as shown, including ripple and noise on the output.
The EVM loop-response characteristics are shown in Figure 5. Gain and phase plots are shown for VIN
voltage of 9 V. Load current for the measurement is 2 A.

60 180
200 mV/div

C2: VOUT ac coupled 40 120

Phase
20 60

Phase - deg
Gain - dB

Gain
0 0

-20 -60

C4: IOUT -40 -120

VOUT = 15 V, VIN = 9 V
1.00 A/div

IOUT = 2.0 A
-60 -180
10 100 1000 10000 100000 1000000
Frequency - Hz C004

Time = 200 µs/div

Figure 4. Load Transient Response Figure 5. Loop Response

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2.5 Output Voltage Ripple

The EVM continuous conduction mode (CCM) output voltage ripple is shown in Figure 6. The output
current is the rated full load of 2 A and VIN = 9 V. The voltage ripple is measured directly across the output
capacitors.
The discontinuous conduction mode (DCM) output voltage ripple is shown in Figure 7. The output current
is 0.15 A and VIN = 9 V.
The pulse skip mode output voltage ripple is shown in Figure 8. There is no external load on the output
and VIN = 9 V.

1.00 A/div 20.0 mV/div

1.00 A/div 100 mV/div

C2: VOUT ac coupled C2: VOUT ac coupled

C4: IL
C4: IL

C1: SW C1: SW
10.0 V/div

10.0 V/div

Time = 1.00 µs/div Time = 1.00 µs/div

Figure 6. Output Voltage Ripple CCM Figure 7. Output Voltage Ripple DCM
1.00 A/div 20.0 mV/div

C2: VOUT ac coupled

C4: IL

C1: SW
10.0 V/div

Time = 500 µs/div

Figure 8. Output Voltage Ripple Pulse Skip Mode

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2.6 Input Voltage Ripple

The EVM CCM input voltage ripple is shown in Figure 9. The output current is the rated full load of 2 A
and VIN = 9 V. The voltage ripple is measured directly across the input capacitors.
The DCM input voltage ripple is shown in Figure 10. The output current is 0.15 A and VIN = 9 V.
20.0 mV/div

20.0 mV/div
C2: VIN ac coupled C2: VIN ac coupled

C4: IL C4: IL
1.00 A/div

1.00 A/div
C1: SW C1: SW
10.0 V/div

10.0 V/div
Time = 1.00 µs/div Time = 1.00 µs/div
Figure 9. Input Voltage Ripple CCM Figure 10. Input Voltage Ripple DCM

2.7 Start Up
The start up waveforms are shown in Figure 11 and Figure 12. The input voltage for these plots is 9 V and
the output has a 2-A resistive load. In Figure 11 the input voltage supply is turned on and VIN begins rising.
Both the VCC and VOUT rail initially rise with VIN. When the input reaches the undervoltage lockout
threshold set by the external resistor divider, the device can begin switching and the output ramps up to
the set value of 15 V with the slow-start voltage. PGOOD goes high when VOUT is in regulation.
In Figure 12 the input voltage is applied with EN held low. The output voltage is a diode drop below the
input voltage and VCC is disabled. When EN is released, the start up sequence begins with VCC coming
into regulation and the output ramps up to the set value of 15 V. PGOOD goes high when VOUT is in
regulation.
5.00 V/div

5.00 V/div

C1: VIN C1: EN

C2: VCC C2: VCC

5.00 V/div 5.00 V/div 5.00 V/div

5.00 V/div 5.00 V/div 5.00 V/div

C3: VOUT
C3: VOUT
C4: PGOOD C4: PGOOD

Time = 5.00 ms/div Time = 5.00 ms/div

Figure 11. Start Up Relative to VIN Figure 12. Start Up Relative to EN

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2.8 Shutdown
The shutdown waveforms are shown in Figure 13 and Figure 14. In Figure 13 the input voltage is
removed, and when the input falls below the undervoltage lockout threshold set by the EN resistor divider,
the TPS43061 shuts down, PGOOD is pulled low and the output falls to ground. The output has a 2-A
resistive load.
In Figure 14 the input voltage is held at 9 V with no load and EN is shorted to ground. When EN is
grounded, the TPS43061 is disabled, PGOOD is pulled low and the output voltage discharges to VIN.
5.00 V/div

5.00 V/div
C1: VIN C1: EN

C2: VCC C2: VCC

5.00 V/div 5.00 V/div 5.00 V/div

5.00 V/div 5.00 V/div 5.00 V/div

C3: VOUT C3: VOUT

C4: PGOOD
C4: PGOOD

Time = 5.00 ms/div Time = 200 ms/div

Figure 13. Shutdown Relative to VIN Figure 14. Shutdown Relative to EN

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2.9 Gate-Drive Signals

In Figure 15 the gate-drive signals for the high-side and low-side FETs can be seen with the switching
node are shown. The input voltage is 9 V and the output has a 2-A load.

10.0 V/div
C2: HDRV

10.0 V/div
5.00 V/div C1: SW

C3: LDRV

Time = 400 ns/div

Figure 15. Gate-Drive Signals

3 Schematic and Bill of Materials

This section presents the EVM schematic and bill of materials.

3.1 Schematic
Figure 16 is the schematic for the EVM.
NOTES
J5 For DCR sensing, open R14 and short R15, R16, and R17. For resistor sensing, open R15.
1
VIN For Split Rail application, open R11.
VIN 2
R16

20m
TP8
J6 VIN: 6V-12.6V R17 L1
1
VIN
2 20m 3.3uH
GND + J1
C13 C14 C15
R13 R14 R15 2
10uF 10uF 1 VOUT
TP9 1 10 10 1
J7
2
ISNS+ ISNS-
GND 1
TP3
J2
15V @ 2A
2
VOUT
TP4 1
VCC Q1 GND
CSD86330Q3D
R1 1 8
VIN
100k TP2 + C16
R3
2 7 C2 C3 C4 C5
TP1
R2 0
JP1 3 6 10uF 10uF 10uF 10uF
1 221k 1 J3
ON 4 5 2
2
EN TP5 1 GND
9
3
OFF R4
R6
R5 17 16 15 14 13 TP6
59.0k
C1 49.9
PGOOD
AGND

HDRV
PWPD

EN

76.8k
0.1uF
1 12
RT/CLK SW
2 11
SS BOOT C10
U1
3 10
COMP TPS43061RTE VCC VCC R8
4 9 TP7
FB FB PGND 1 124k
R7 C6
C7 7.50k FB
4.7uF
ISNS+

LDRV
ISNS-

C8
VIN

0.1uF R9
150pF 5 6 7 8
C9
11.0k
0.015uF C12 100pF

VIN
R12 1 C11 R10 0
0.1uF
R11
ISNS- ISNS+
J4 0
1

1 Not Populated
VBIAS (OPTIONAL)

Figure 16. TPS43061EVM-198 Schematic

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3.2 Bill of Materials

Table 4 presents the bill of materials for the EVM.

Table 4. TPS43061EVM-198 Bill of Materials

COUNT RefDes Value Description Size Part Number MFR
1 C6 4.7uF Capacitor, Ceramic, 16V, X5R, 10% 0603 STD STD
1 C8 150pF Capacitor, Ceramic, 50V, C0G, 5% 0603 STD STD
1 C9 0.015uF Capacitor, Ceramic, 50V, X7R, 10% 0603 STD STD
0 C10 Open Capacitor, Ceramic, 10V, X7R, 10% 0603 STD STD
1 C12 100pF Capacitor, Ceramic, 25V, X7R, 20% 0603 STD STD
3 C1 C7 C11 0.1uF Capacitor, Ceramic, 25V, X7R, 10% 0603 STD STD
5 C2-5 C14-15 10uF Capacitor, Ceramic Chip, 25V, X5R, 10% 1210 STD STD
0 C13 C16 Open Capacitor Multi sizes Engineering Only STD
5 J1 J3-5 J7 PEC02SAAN Header, Male 2-pin, 100mil spacing 0.100 inch x 2 PEC02SAAN Sullins
1 J2 ED555/2DS Terminal Block, 2-pin, 6-A, 3.5mm 0.27 x 0.25 inch ED555/2DS OST
1 J6 ED120/2DS Terminal Block, 2-pin, 15-A, 5.1mm 0.40 x 0.35 inch ED120/2DS OST
1 JP1 PEC03SAAN Header, Male 3-pin, 100mil spacing 0.100 inch x 3 PEC03SAAN Sullins
1 L1 3.3uH Inductor, SMT, 6.0A, 30-milliohm 0.255 x 0.270 IHLP2525CZER3R3M0 Vishay
inch 1
1 Q1 CSD86330Q3 MOSFET, Synchronous Buck NexFET QFN-8 POWER CSD86330Q3D TI
D Power Block
1 R1 100k Resistor, Chip, 1/16W, 1% 0603 STD STD
1 R3 221k Resistor, Chip, 1/16W, 1% 0603 STD STD
1 R4 59.0k Resistor, Chip, 1/16W, 1% 0603 STD STD
1 R5 76.8k Resistor, Chip, 1/16W, 1% 0603 STD STD
1 R6 49.9 Resistor, Chip, 1/16W, 1% 0603 STD STD
1 R7 7.50k Resistor, Chip, 1/16W, 1% 0603 STD STD
1 R8 124k Resistor, Chip, 1/16W, 1% 0603 STD STD
1 R9 11.0k Resistor, Chip, 1/16W, 1% 0603 STD STD
0 R12 R15 Open Resistor, Chip, 1/16W, 1% 0603 STD STD
2 R13-14 10 Resistor, Chip, 1/16W, 1% 0603 STD STD
2 R16-17 20m Resistor, Chip, 1/2W, 1%, 100ppm 1206 PF1206FRF070R02L Yageo
3 R2 R10-11 0 Resistor, Chip, 1/16W, 1% 0603 STD STD
1 SH1 Short jumper, 100mil 0.100 inch 929950-00 3M
2 TP4 TP9 5001 Test Point, Black, Thru Hole Color Keyed 0.100 x 0.100 5001 Keystone
inch
7 TP1-3 TP5-8 5000 Test Point, Red, Thru Hole Color Keyed 0.100 x 0.100 5000 Keystone
inch
1 U1 TPS43061RTE IC, Wide VIN Current Mode Synchronous VQFN TPS43061RTE TI
Boost Controller
1 -- PCB, 3.2 In x 1.8 In x 0.062 In PWR198 Any

Notes: 1. These assemblies are ESD sensitive, ESD precautions shall be observed.
2. These assemblies must be clean and free from flux and all contaminants.
Use of no clean flux is not acceptable.
3. These assemblies must comply with workmanship standards IPC-A-610 Class 2.
4. Ref designators marked with an asterisk ('**') cannot be substituted.
All other components can be substituted with equivalent MFG's components.

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4 Board Layout
This section provides a description of the EVM, board layout, and layer illustrations.

4.1 Layout
The board layout for the EVM is shown in Figure 17 through Figure 21. This design has 4 layers of 2-oz
copper.
The top layer contains the main power traces for VIN, VOUT, and SW. Also on the top layer are all other
components to allow the user to easily view, probe, and evaluate the TPS43061 control IC. The remaining
area is filled with ground. The remaining three layers have additional copper for VIN, VOUT, AGND, and
PGND connected with multiple vias. Additional copper is also connected to the sense resistor to aid with
thermal dissipation. The second internal layer and bottom layer contain signal routes. Five vias directly
under the TPS43061 device provide a thermal path from the top-side ground plane to the bottom-side and
internal AGND plane. Lastly, the layout guidelines should be followed for the CSD86330Q3D which
includes 12 vias beneath the device to the internal and bottom PGND planes to aid with thermal
dissipation.
All noise-sensitive analog circuitry are placed as close as possible to the IC. The voltage divider network
ties to the output voltage at the point of regulation on the bottom layer, near the output capacitors. Q1 is
also placed as close as possible to the IC to keep the gate-drive traces as short as possible. The output
capacitors are placed next to Q1 to limit the length of the high frequency switching current path. The SW
copper is kept as small as possible to limit radiated noise from the high-frequency switching voltage node.
The power pad is connected to the AGND pin and all noise-sensitive circuitry must use this as the ground
return path. The ground return for the power components are connected to the PGND pin. The AGND and
PGND are connected at one point near the PGND pin. The bypass capacitors for VIN and VCC are placed
next to their respective pins. The filter capacitor between ISNS+ and ISNS- is located next to the pins to
help filter out switching noise. An additional input bulk capacitor may be required (C13) depending on the
connection to the EVM from the input supply. See the product datasheet for all layout recommendations.

J4 JP1 TP1
J4 JP1 TP1
VBIAS ON EN OFF PGOOD
(OPTIONAL)
J5 J1
TP5
TP5 SW
VIN = VOUT =
J5 6V-12.6V
R3 R3 TP2 15V @ 2A J1
C13 TP2 HDRV
TP8
R5

TP3
R4 R4
+

J6
+

C9
C8
C7

VOUT J2
C5
C3

C2

C4

TP8 R1
GND VOUT

R2
R5
VIN

R1
C1 R2 Q1 TP3
C9
C8
C7

U1
1

J6 C1 1
C16
C13

J2
R10 C6

R7 R7
C4
C15

C14

U1
C3

C2

C5

C6 Q1
GND

R9

C12 TP4
C10

C11 R10
R9
R8
C15

C14
C10

C12 C11 TP7 TP4

R8

TP9 R12 R15 TP7 PGND

TP6TP6 R6 R6 R12
LDRV

R15 L1 C16
TP9 LOOP R13 R14 R14 L1
R11
R11

R13
J3 GND GND J7
R17

J3 R16 J7
R17
R16

PWR198 Rev. A
TPS43061EVM-198

Figure 17. TPS43061EVM-198 Top Assembly and Silkscreen

12 Using the TPS43061 Boost Evaluation Module (EVM) SLVU799 – November 2012
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Copyright © 2012, Texas Instruments Incorporated
www.ti.com Board Layout

Figure 18. TPS43061EVM-198 Top-Side Layout

Figure 19. TPS43061EVM-198 Layer 2 Layout

SLVU799 – November 2012 Using the TPS43061 Boost Evaluation Module (EVM) 13
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Copyright © 2012, Texas Instruments Incorporated
Board Layout www.ti.com

Figure 20. TPS43061EVM-198 Layer 3 Layout

Figure 21. TPS43061EVM-198 Bottom-Side Layout

4.2 Estimated Circuit Area

The estimated printed-circuit-board area by outlining the components used in this design and the routing
between them is 0.91 in2 (590 mm2). This area does not include test points or connectors. Also note, this
design uses 0603 components for easy modifications and places all components on one layer so this area
may be reduced.

14 Using the TPS43061 Boost Evaluation Module (EVM) SLVU799 – November 2012
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
 EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS
Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions:
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims
arising from the handling or use of the goods.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from
the date of delivery for a full refund. THE FOREGOING LIMITED WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO
BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH
ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES.
Please read the User's Guide and, specifically, the Warnings and Restrictions notice in the User's Guide prior to handling the product. This
notice contains important safety information about temperatures and voltages. For additional information on TI's environmental and/or safety
programs, please visit www.ti.com/esh or contact TI.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which such TI products or services might be or are used. TI currently deals with a variety of customers for products, and
therefore our arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described herein.

REGULATORY COMPLIANCE INFORMATION

As noted in the EVM User’s Guide and/or EVM itself, this EVM and/or accompanying hardware may or may not be subject to the Federal
Communications Commission (FCC) and Industry Canada (IC) rules.
For EVMs not subject to the above rules, this evaluation board/kit/module is intended for use for ENGINEERING DEVELOPMENT,
DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer
use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to part 15 of FCC or ICES-003 rules, which are designed to provide reasonable protection against radio frequency
interference. Operation of the equipment may cause interference with radio communications, in which case the user at his own expense will
be required to take whatever measures may be required to correct this interference.
General Statement for EVMs including a radio
User Power/Frequency Use Obligations: This radio is intended for development/professional use only in legally allocated frequency and
power limits. Any use of radio frequencies and/or power availability of this EVM and its development application(s) must comply with local
laws governing radio spectrum allocation and power limits for this evaluation module. It is the user’s sole responsibility to only operate this
radio in legally acceptable frequency space and within legally mandated power limitations. Any exceptions to this are strictly prohibited and
unauthorized by Texas Instruments unless user has obtained appropriate experimental/development licenses from local regulatory
authorities, which is responsibility of user including its acceptable authorization.

For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant

Caution
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause
harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the
equipment.

FCC Interference Statement for Class A EVM devices

This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the
instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to
cause harmful interference in which case the user will be required to correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment
generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause
harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If
this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and
on, the user is encouraged to try to correct the interference by one or more of the following measures:
• Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult the dealer or an experienced radio/TV technician for help.
For EVMs annotated as IC – INDUSTRY CANADA Compliant

This Class A or B digital apparatus complies with Canadian ICES-003.

Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the
equipment.

Concerning EVMs including radio transmitters

This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this
device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired
operation of the device.

Concerning EVMs including detachable antennas

Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain
approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should
be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication.

This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum
permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain
greater than the maximum gain indicated for that type, are strictly prohibited for use with this device.

Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada.

Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de
l'utilisateur pour actionner l'équipement.

Concernant les EVMs avec appareils radio

Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est
autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout
brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.

Concernant les EVMs avec antennes détachables

Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain
maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à
l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente
(p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante.

Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel
d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans
cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur.

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 【Important Notice for Users of this Product in Japan】
】
This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan

If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product:
1. Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and
Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of
Japan,
2. Use this product only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this
product, or
3. Use of this product only after you obtained the Technical Regulations Conformity Certification as provided in Radio Law of Japan with
respect to this product. Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note
that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan.
Texas Instruments Japan Limited
(address) 24-1, Nishi-Shinjuku 6 chome, Shinjuku-ku, Tokyo, Japan

http://www.tij.co.jp

【ご使用にあたっての注】

本開発キットは技術基準適合証明を受けておりません。

本製品のご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。
1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。
2. 実験局の免許を取得後ご使用いただく。
3. 技術基準適合証明を取得後ご使用いただく。

なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。

　　　上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。

日本テキサス・インスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
http://www.tij.co.jp

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 EVALUATION BOARD/KIT/MODULE (EVM)
WARNINGS, RESTRICTIONS AND DISCLAIMERS
For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished
electrical equipment and not intended for consumer use. It is intended solely for use for preliminary feasibility evaluation in
laboratory/development environments by technically qualified electronics experts who are familiar with the dangers and application risks
associated with handling electrical mechanical components, systems and subsystems. It should not be used as all or part of a finished end
product.

Your Sole Responsibility and Risk. You acknowledge, represent and agree that:
1. You have unique knowledge concerning Federal, State and local regulatory requirements (including but not limited to Food and Drug
Administration regulations, if applicable) which relate to your products and which relate to your use (and/or that of your employees,
affiliates, contractors or designees) of the EVM for evaluation, testing and other purposes.
2. You have full and exclusive responsibility to assure the safety and compliance of your products with all such laws and other applicable
regulatory requirements, and also to assure the safety of any activities to be conducted by you and/or your employees, affiliates,
contractors or designees, using the EVM. Further, you are responsible to assure that any interfaces (electronic and/or mechanical)
between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to
minimize the risk of electrical shock hazard.
3. You will employ reasonable safeguards to ensure that your use of the EVM will not result in any property damage, injury or death, even
if the EVM should fail to perform as described or expected.
4. You will take care of proper disposal and recycling of the EVM’s electronic components and packing materials.

Certain Instructions. It is important to operate this EVM within TI’s recommended specifications and environmental considerations per the
user guidelines. Exceeding the specified EVM ratings (including but not limited to input and output voltage, current, power, and
environmental ranges) may cause property damage, personal injury or death. If there are questions concerning these ratings please contact
a TI field representative prior to connecting interface electronics including input power and intended loads. Any loads applied outside of the
specified output range may result in unintended and/or inaccurate operation and/or possible permanent damage to the EVM and/or
interface electronics. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the
load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures
greater than 60°C as long as the input and output are maintained at a normal ambient operating temperature. These components include
but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors which can be identified using the
EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during normal operation, please
be aware that these devices may be very warm to the touch. As with all electronic evaluation tools, only qualified personnel knowledgeable
in electronic measurement and diagnostics normally found in development environments should use these EVMs.

Agreement to Defend, Indemnify and Hold Harmless. You agree to defend, indemnify and hold TI, its licensors and their representatives
harmless from and against any and all claims, damages, losses, expenses, costs and liabilities (collectively, "Claims") arising out of or in
connection with any use of the EVM that is not in accordance with the terms of the agreement. This obligation shall apply whether Claims
arise under law of tort or contract or any other legal theory, and even if the EVM fails to perform as described or expected.

Safety-Critical or Life-Critical Applications. If you intend to evaluate the components for possible use in safety critical applications (such
as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, such as devices
which are classified as FDA Class III or similar classification, then you must specifically notify TI of such intent and enter into a separate
Assurance and Indemnity Agreement.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
 IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
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