Comparator & Decoders

By
Dr. Nermeen Talaat
Lecture 11

1
 Comparator
The basic function of a comparator is to compare the
magnitudes of two binary quantities to determine the
relationship of those quantities. In its simplest form.
A comparator circuit determines whether two numbers
are equal.

2
 COMPARATORS
Equality:
As you learned in before the exclusive-OR gate can be used as a
basic comparator because its output is a 1 if the two input bits are
not equal and a 0 if the input bits are equal.
Figure shows the exclusive-OR gate as 2- bit comparator.

The output is 1 when the inputs are equal

Exclusive-OR gate as a 2-bit comparator.

 COMPARATORS

In order to compare binary numbers containing two bits each, an

additional exclusive- OR gate is necessary.
The two least significant bits (LSBs) of the two numbers are compared
by gate G1, and the two most significant bits (MSBs) are compared by
gate G2.

As shown in Figure :
If the two numbers are equal, their corresponding bits are the same,
and the output of each exclusive-OR gate is a 0.
If the corresponding sets of bits are not equal. a 1 occurs on that
exclusive-OR gate output.
 COMPARATORS

Logic diagram for equality comparison of two 2-bit numbers.

LSB

MSB

A A1A0
B B1B0
The output is 1 when A0 = B0 AND A1 = B1
 COMPARATORS

Example 1:
Apply each of the following sets of binary numbers to the comparator inputs in
Figure 3, and determine the output by following the logic levels through the circuit.
(a) 10 and 10 (b) 11 and 10

Figure 3
 COMPARATORS

Solution

Example 1, illustrates this operation for two specific cases. The exclusive-OR gate and
inverter are replaced by an exclusive-NOR symbol.
 COMPARATORS

4-Bit Comparator
 The 7485 is a standard comparator package with the
following attributes:
 One of three outputs will be HIGH:

 A greater than B (A > B)

 A equal to B (A = B)

 A less than B (A < B)

Useful MSI circuits
 Four common and useful MSI circuits are:
 Decoder
 Encoder
 Multiplexer
 Demultiplexer
 Block-level outlines of MSI circuits:

decoder encoder
code entity entity code

mux data data demux output

input
9
Useful MSI circuits

select select
Decoder background
 Given a n-bit binary number there are 2n things it can
represent or lines that can be activated
 A decoder detects the presence of a specified combination of
bits (code) on its inputs and indicates the presence of that
code by a specified output level.
 In its general form,, a decoder has n input lines to handle n
bits and forms one to 2n output lines to indicate the presence
of one or more n-bits combinations..
 n 2n decoder n inputs,, 2n outputs
 For each input, one and only one output will be active..

10
1-to-2-line decoders
 Circuit has n inputs and m outputs and m = 2n
 Start with n=1 and m=2
 This a 1-to-2 Line decoder – exactly one of
the output lines will be active.

11
n-to-m-line decoders
 A decoder when n=2 and m=4
 A 2-to-4 line decoder
 Note that only one output is ever active
F0 = X'.Y'

X Y F0 F1 F2 F3 F1 = X'.Y
0 0 1 0 0 0
0 1 0 1 0 0 F2 = X.Y'
1 0 0 0 1 0
1 1 0 0 0 1 F3 = X.Y

X Y
12
Can be seen to create structure
 For the 2-to-4 line 2x4
F0 Bulb 0
2-bit X Dec F Bulb 1
1
code Y
F2 Bulb 2
F3 Bulb 3
 Contains 2 (2-to-1)
line decoders and
the additional logic.

13
 Higher levels of structure
 A 3-to-8 line decoder

 Can be extended to even high levels

14
 Decoders
 Design a 38 decoder. F0 = x'.y'.z'

F1 = x'.y'.z
x y z F0 F1 F2 F3 F4 F5 F6 F7
0 0 0 1 0 0 0 0 0 0 0 F2 = x'.y.z'
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0 F3 = x'.y.z
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0 F4 = x.y'.z'
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0 F5 = x.y'.z
1 1 1 0 0 0 0 0 0 0 1
F6 = x.y.z'

F7 = x.y.z

 Application? Binary-to-octal
conversion. x y z
15
In General Decoder
 In general, for an n-bit code, a decoder could select up to
2n lines:

n-bit n to 2n up to 2n
code : decoder : output lines

16
 Decoders: Implementing Functions

 A Boolean function, in sum-of-minterms form a

decoder to generate the minterms, and an OR gate to form
the sum.
 Any combinational circuit with n inputs and m outputs
can be implemented with an n:2n decoder with m OR
gates.
 Good when circuit has many outputs, and each function is
expressed with few minterms.

17
 Decoders: Implementing Functions

x y z C S
 Example: Full adder 0 0 0 0 0
0 0 1 0 1
S(x, y, z) = S m(1,2,4,7) 0 1 0 0 1
0 1 1 1 0
C(x, y, z) = S m(3,5,6,7) 1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

3x8 0
Dec 1 S
2
x S2 3
y S1 4
5 C
z S0 6 18
7
Decoders: Implementing Functions

3x8 0 1
x y z C S
Dec 0 0 0 0 0
1 0 S 0 0 0 1 0 1
2 0
0 x S2 0 1 0 0 1
3 0 0 1 1 1 0
0 y S1 4 0 1 0 0 0 1
5 0 C 0 1 0 1 1 0
0 z S0 6 0 1 1 0 1 0
7 0 1 1 1 1 1

19
Decoders: Implementing Functions

3x8 0 0
x y z C S
Dec 0 0 0 0 0
1 1 S 1 0 0 1 0 1
2 0
0 x S2 0 1 0 0 1
3 0 0 1 1 1 0
0 y S1 4 0 1 0 0 0 1
5 0 C 0 1 0 1 1 0
1 z S0 6 0 1 1 0 1 0
7 0 1 1 1 1 1

20
Decoders: Implementing Functions

3x8 0 0
x y z C S
Dec 0 0 0 0 0
1 0 S 1 0 0 1 0 1
2 0
1 x S2 0 1 0 0 1
3 0 0 1 1 1 0
1 y S1 4 0 1 0 0 0 1
5 0 C 1 1 0 1 1 0
1 z S0 6 0 1 1 0 1 0
7 1 1 1 1 1 1

BRAVO!!!
21
 Decoders with Enable

 Decoders often come with an enable signal, so that the

device is only activated when the enable, E=1.
 Truth table: F0 = EX'Y'

E X Y F0 F1 F2 F3 F1 = EX'Y
1 0 0 1 0 0 0
1 0 1 0 1 0 0 F2 = EXY'
1 1 0 0 0 1 0
1 1 1 0 0 0 1
0 X X 0 0 0 0 F3 = EXY

 Circuit:
22
X Y E
 Decoders with Enable

 In the previous slide, the decoder has a one-enable signal,

that is, the decoder is enabled with E=1.
 In most MSI decoders, enable signal is zero-enable,
usually denoted by E’ (or E). The decoder is enabled
when the signal is zero.

E X Y F0 F1 F2 F3 E' X Y F0 F1 F2 F3
1 0 0 1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 1 0 0 0 0 1 0 1 0 0
1 1 0 0 0 1 0 0 1 0 0 0 1 0
1 1 1 0 0 0 1 0 1 1 0 0 0 1
0 X X 0 0 0 0 1 X X 0 0 0 0
23
Decoder with 1-enable Decoder with 0-enable
 Larger Decoders
 Larger decoders can be 3x8
Dec 0 F0 = w'x'y'
w S2 1 F1 = w'x'y
constructed from x S1 : :
smaller ones. y S0 : :
7 F7 = wxy

 For example, a 3-to-8

decoder can be
constructed from two w
2x4
Dec 0 F0 = w'x'y'
S1
2-to-4 decoders (with x
y S0
1
2
F1 = w'x'y
F2 = w'xy'
one-enable), as E 3 F3 = w'xy

follows:
2x4
Dec 0 F4 = wx'y'
S1 1 F5 = wx'y
S0 2 F6 = wxy'
E 3 F7 = wxy
24
Larger Decoders

3x8
Dec 0 F0 = w'x'y'
w S2 1 F1 = w'x'y
2x4
0 w
Dec 0 1 F0 = w'x'y' x S1 : :
0 x S1 1
0 F1 = w'x'y y S0 : :
S0
0 7 F7 = wxy
0 y 2
0
F2 = w'xy'
E 3 F3 = w'xy

1 = enabled
2x4 0
Dec 0 F4 = wx'y'
S1 1
0 F5 = wx'y
S0 2
0 F6 = wxy'
0
E 3 F7 = wxy

0 = disabled
25
Larger Decoders

3x8
Dec 0 F0 = w'x'y'
w S2 1 F1 = w'x'y
2x4 0 : :
0 w 0 F0 = w'x'y' x S1
Dec 1 : :
0 x S1 1 F1 = w'x'y y S0
S0
0 7 F7 = wxy
1 y 2
0
F2 = w'xy'
E 3 F3 = w'xy

1 = enabled
2x4 0
Dec 0 F4 = wx'y'
S1 1
0 F5 = wx'y
S0 2
0 F6 = wxy'
0
E 3 F7 = wxy

0 = disabled
26
Larger Decoders

3x8
Dec 0 F0 = w'x'y'
w S2 1 F1 = w'x'y
2x4 0 F = w'x'y' x S1 : :
1 w 0 0
1 x S1
Dec
1
0 = disabled
0
F = w'x'y y S0 : :
S0
0 F1 = w'xy' 7 F7 = wxy
0 y 2
0 2
E 3 F3 = w'xy

2x4 0 F = wx'y'
Dec 0 4
S1 1
0
1 = enabled
F = wx'y
S0 2
1 F5 = wxy'
6
0
E 3 F7 = wxy
BRAVO!!!
27
Larger Decoders
 Construct a 4x16 4x16
Dec 0 F0
w S3
decoder from two x S2
1 F1
3x8 decoders with : :
y S1
: :
1-enable. z S0 15 F15

3x8
w Dec 0 F0
x S2
1 F1
y S1 : :
z S0 7 F7
E

3x8
Dec 0 F8
S2
1 F9
S1 : :
S0 7 F15
E 28
 Larger Decoders

 Note: The input, w and its complement, w', is used to

select either one of the two smaller decoders.
 Decoders may also have zero-enable and/or negated
outputs. (Normal outputs = active high; negated outputs
= active low.)
 Exercise: What modifications must be made to provide an
ENABLE input for the 3x8 decoder (2 slides ago) and the
4x16 decoder (previous slide) created?

29
Decoders: Implementing Functions (2)
 Example: Implement the following logic function using
decoders and logic gates
f(Q,X,P) =  m(0,1,4,6,7) =  M(2,3,5)
 We may implement the function in several ways:
 Use a decoder (with active-high outputs) with an OR gate:
f(Q,X,P) = m0 + m1 + m4 + m6 + m7
 Use a decoder (with active-high outputs) with a NOR gate:
f(Q,X,P) =  M(2,3,5) = M2.M3.M5

30
Decoders: Implementing Functions (2)

0 f(Q,X,P) =  m(0,1,4,6,7)
3x8 1
Dec 2
Q A 3 f(Q,X,P)
B 4
X
5
P C 6
7

(a) Active-high decoder with OR gate. f(Q,X,P) =  M(2,3,5)

0
3x8 1
Dec 2 f(Q,X,P)
Q A 3
B 4
X
5
P C 6
7

31
(d) Active-low decoder with AND gate.