Sequential Module 3 DSD
Sequential Module 3 DSD
Comprises both logic gates and the state of storage elements such as flip-
flops.
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Combinational Vs Sequential circuits
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SR LATCH USING NAND GATES
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Difference between Latch and Flip-Flops
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» Flip-Flops
A flip flop is an electronic circuit with two stable states that can be used to store
binary data.
• SR Flip-Flop
• D flip-flop
• JK flip-flop
• Master slave JK flip-flop
• T flip-flop
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» SR Flip-Flop
• SR flip-flop operates with only positive clock transitions or negative clock transitions
• Circuit has two inputs S & R and two outputs Q and Q’.
• The operation of SR flip-flop is similar to SR Latch. But, this flip-flop affects the outputs only
when positive transition of the clock signal is applied instead of active enable.
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• Truth Table
• S = R = 0 then output of NAND gates 3 and 4 are forced to become 1.
• Since S' and R' are the inputs of the basic S-R latch using NAND gates, there
will be no change in the state of outputs.
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CHARACTERISTIC AND EXCITATION TABLE
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» D flip-flop
• D flip-flop operates with only positive clock transitions or negative clock
transitions.
• This means, the output of D flip-flop is insensitive to the changes in the
input.
• The circuit diagram of D flip-flop is shown below.
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» Truth Table
E = 0:
• Latch is disabled. Hence no change in output.
E = 1 and D = 0:
• If E = 1 and D = 0 then S = 0 and R = 1. Hence, irrespective of the
present state, the next state is Qn+1 = 0 and Qn+1 bar = 1. This is the
reset condition.
E = 1 and D = 1
• If E = 1 and D = 1, then S = 1 and R = 0. This will set the latch and
Qn+1 = 1 and Qn+1 bar = 0
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JK FLIP-FLOP
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MASTER-SLAVE JK FLIP-FLOP
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T-Flip Flop
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TRUTH TABLE & CHARACTERISTIC TABLE
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Frequently Asked Questions