|7610

Technical Report
Volume 2
 ~ Introduction ~

In the IC-7610 Technical Manual Volume 1, we outlined the attraction of

the IC-7610. In Volume 2, we will explain the RF direct sampling system
used in the IC-7610 and RMDR which Icom has been using as the evaluation
standard for receiver performance in recent years.
Table of contents
Section 01 About the RF Direct Sampling System………………………………01~04
What is the RF direct sampling system?………………………………………… 01
The advantage of the RF Direct Sampling system……………………………… 02
About the direct conversion system…………………………………………………………………… 02
Benefits of RF direct sampling method………………………………………………………………… 02
A/D conversion………………………………………………………………………… 03
A/D conversion of the RF signal…………………………………………………… 03
FPGA internal processing…………………………………………………………… 04
Conversion to I/Q signal and detection (I/Q = in-phase/quadrature)……………………………… 04
Scope signal generation………………………………………………………………………………… 04
Various signal processing features…………………………………………………………………… 04

Section 02 About RMDR………………………………………………………… 05~07

Basic of RMDR………………………………………………………………………… 05
What is RMDR?………………………………………………………………………………………… 05
Reason for evaluating receiver performance with RMDR…………………………………………… 05
A case study where you can experience RMDR……………………………………………………… 05
The relationship between RMDR and phase noise……………………………… 06
About Phase Noise……………………………………………………………………………………… 06
About Jitter………………………………………………………………………………………………… 06
Comparison with conventional transceivers……………………………………… 07
Comparison of RMDR…………………………………………………………………………………… 07
Comparison of transmission C/N and transmission phase noise characteristics………………… 07

Section 03 Block Diagram……………………………………………………………08~11

Section 01 About the RF direct sampling system

What is the RF direct sampling system?

The RF direct sampling system is used in the IC-7610, As you can see in the receiver block diagram, shown in
following the IC-7300 and the IC-R8600 (the latter limited Figure 01-01, the design from the antenna, through the
to 0.01~29.999999 MHz). We can imagine that someone bandpass filter (BPF), to the RF preamplifier is equivalent
who is interested in, or has doubts, may well ask “what to a conventional (superheterodyne) radio. However, after
is this RF direct sampling system?” Here, we will briefly the RF amplifier, there is an A/D converter instead of a
explain it. mixer. Thus, as mentioned above, the RF signals are
In short, as described in Volume 1, the received analog RF converted to a digital bit stream as is, without converting
signal is converted to a digital signal in the A/D converter the RF signals to an intermediate frequency (IF). This
(ADC) and batch processed by the Field-programmable is the reason why this architecture is called RF direct
Gate Array (FPGA). sampling.

1.8MHz
ANT2 ANT1
BPF AMP A/D

DIGISEL 3.5MHz
MAIN
BPF
AF
D/A AMP INT
SP
SPLITTER 50MHz
FPGA
BPF

Main band AF
D/A AMP
Sub band
1.8MHz

BPF AMP A/D

DIGISEL
3.5MHz
SUB

BPF

50MHz

BPF
Figure 01-01 Receiver Overview

In addition, the reception method is described as "Direct Figure 01-02 is a block diagram roughly describing
Sampling Super Heterodyne Method" in the product the inside of the FPGA. The signal from the external
brochure, and in Volume 1 of the Technical Report A/D converter is input to the FPGA, and it is seen that
(published earlier). We will also briefly explain this point. it is input to a mixer (I/Q). This mixer (I/Q) converts the
The reason for the terminology "direct sampling digitally converted RF signal to an I/Q signal. Since this
superheterodyne" is found in the architecture of the FPGA. conversion process also includes frequency conversion,
there is a difference between analog and digital, but since
it follows the superheterodyne principle, we are calling this
architecture a "direct sampling superheterodyne system".

RX A/D MIXER
(IQ)
FILTER DET SP
RX(MAIN)
D/A

RX A/D MIXER
(IQ)
FILTER DET
RX(SUB)

TX
TX
D/A MIXER
(IQ)
FILTER MOD A/D MIC

DDS MIXER DATA

FILTER FFT SUB
(IQ) DRAW
CPU
Master
Clock

DDS
SCOPE(MAIN)

MIXER DATA
FILTER FFT
(IQ) DRAW

Flash
ROM

SCOPE(SUB)
DDS
RF-FPGA

Figure 01-02 FPGA Internal Block Diagram

01
Section 01 About the RF direct sampling system

The advantage of the RF Direct Sampling system

About the direct conversion system Benefits of RF direct sampling method

Let's talk about a general direct conversion system, We have explained that the superheterodyne method
before explaining the reason why Icom chose the RF direct overcomes the problems of the direct conversion method,
sampling system. and the limits it sets to the "3-S" of receivers. So let us
The direct conversion system is a method of generating consider the RF direct sampling system.
a signal equal to, or very close in frequency to the desired The biggest merit of the RF direct sampling method is
RF signal, with a local oscillator, and demodulating the that all processing takes place in the digital domain. In
RF signal by mixing it with the oscillator output. The the superheterodyne system, analog signals are processed
number of parts used is small, and the design is very in the frequency conversion (mixing) process. Since this
simple. For that reason, it is easy to make one chip offering frequency conversion uses the nonlinear distortion region
miniaturization, low power consumption and low cost. of the analog element in the mixer, unnecessary nonlinear
Direct conversion is suitable for various applications, such distortion occurs. On the other hand, with the RF direct
as mobile phones. sampling system, there is no analog mixer, as shown in
However, an analog mixer is used for frequency conversion; figure 01-01 on the previous page. In other words, it is a
it can present problems such as frequency drift in the circuit that generates no unnecessary nonlinear distortion.
local oscillator, spurious signals caused by local oscillator Also, in analog signal processing, the noise from within
leakage, DC biasing of the mixer caused by a powerful and outside the radio equipment has various influences.
interfering signal and second-order intermodulation By contrast, digital signals are not affected by noise at
distortion. Furthermore, other problems such as 1/f noise all. That is, there is no deterioration of the signal in the
and I/Q mismatch (imbalance) can arise. It is also said process after A/D conversion. If the signal processed inside
that it is difficult to improve sensitivity, stability, and the radio device does not deteriorate, the sound finally
selectivity, termed the "3-S" of receivers, beyond certain heard from speakers and headphones will be a faithful
limits. reproduction of the signal being received.
There are other problems such as noise and I/Q mismatch In the IC-7610, these digital signal processing (DSP)
(imbalance). It is also said that it is difficult to improve tasks are collectively performed within the FPGA,
sensitivity, stability and selectivity, beyond certain described later.
limits. The superheterodyne system, widely adopted in
high performance receivers, has largely overcome these
problems.

02
Section 01 About the RF direct sampling system

A/D conversion

A signal from the antenna is converted into a digital After that, we convert the quantized value to a binary
signal by an A/D converter after the target signal has been number. (Fig. 01-05) This is called encoding. As a result,
selected by the Digi-Sel (tracking preselector) circuit and a when the analog signal shown in Fig. 01-03 is divided into
band pass filter (BPF: Band Pass Filter). So, how do you 16 stages of t second periods and digital conversion with 4
convert analog signals to digital signals? Here we briefly bits, it is encoded as "10001110111110010010010010111001
explain the principle. 01001001101000100010100011101101".
First, as shown in Figure 01-03, we divide the analog Generally, it is possible to digitize an analog signal
signal into fixed time intervals (t seconds). Then, we read faithfully by decreasing the sampling interval, and by
the value for each fixed time slot. (Fig. 01-04) This is called increasing the number of levels when quantizing. On the
sampling. other hand, as the amount of data increases, we need
Next, we convert the sampled value to an integer that can enough processing power to handle a considerable amount
be handled with digital signals. of data.

Next we map input values from a large, often continuous In general, Hertz (Hz) is used as a unit indicating the
set, to output values into a countable smaller set. sample rate. 44.1 kHz is used in music CD's. This means
that a 1 second sound is sampled by dividing it by 44,100.
This is called quantization. (In this case, processing is
done by rounding and truncating the decimal part.)

15 15
14 14
13 13
12 12
11 11
10 10
9 9
Level

Level

Level

8 8
7 7
6 6
5 5
4 4
3 3
2 2
14.3
15.8

11.8

10.2

13.4

1 1
8.1

9.2
2.1
4.1

9.7
4.9
9.7

2.2
2.1
8.8
14

0 0
“t” second Time Time
8 14 15 9 2 4 11 9 4 9 10 2 2 8 14 13
=1000
=1110
=1111
=1001
=0010
=0100
=1011
=1001
=0100
=1001
=1010
=0010
=0010
=1000
=1110
Figure 01-03 Figure 01-04 =1101 Figure 01-05

A/D conversion of the RF signal

To convert an analog RF signal to a digital signal, it is Previously, a fast A/D converter capable of sampling
necessary to have a high-speed A/D converter capable of RF signals was not practical. However, with the recent
sampling at more than twice the frequency of the RF signal spread of mobile phones, smart phones, personal computer
to be converted. This is stated in the sampling theorem. networks, and so on, the availability of devices that can
sample at higher frequencies has increased. As a result,
What is the sampling theorem? A/D converters capable of sampling the RF signal have
Assuming that the maximum frequency component of become practical, so RF direct sampling has been realized.
the signal band to be converted is F, a signal sampled Since the upper limit of the frequency that can be
at a frequency (Fs) higher than twice (2 F) thereof, operated with the IC-7610 is 60 MHz, in order to sample
removes high frequency components with a low pass the RF signal, an A/D converter capable of sampling at 120
filter (LPF: Low Pass Filter) so that the original signal MHz or more is required. For that reason, the IC-7610's
can be completely restored. A/D converter employs a device capable of sampling at 130
MHz.

03
Section 01 About the RF direct sampling system

FPGA internal processing

The signals digitally converted by the A/D converter are Conversion to I/Q signal and detection
subjected to the following processing operations inside the (I/Q = in-phase/quadrature)
FPGA.
The RF signal digitally converted by the A/D converter is
• Conversion to I/Q signal
converted to an I/Q signal in this mixer (I/Q) section. The
• Detection (demodulation)
converted I/Q signal is subjected to filtering and detection
• Signal processing such as noise reduction, noise blanker,
processing within the FPGA according to the operating
selectivity filtering, NOTCH, PBT
mode selected on the IC-7610 main unit. If it is a voice
• Scope signal generation
mode (SSB, AM, FM), the I/Q signal is converted from
• Squelch control, and so on.
analog to digital by a separate D /A converter, then it is
output from the speaker or headphone through the audio
RX MIXER

amplifier circuit. If it is a digital data mode (RTTY, PSK),

A/D
(IQ)
FILTER DET SP
RX(MAIN)
it is displayed on the display of the IC-7610, or the data is
D/A

output from the USB 2 port on the rear panel, depending

RX A/D MIXER
(IQ)
FILTER DET
RX(SUB)
on the operating mode, after processing and decoding.
TX
TX D/A MIXER
(IQ)
FILTER MOD A/D MIC Also, demodulated sounds are output from the speaker
and headphone jacks, for data as well as voice modes. This
DDS MIXER FILTER FFT DATA
DRAW SUB
I/Q signal is scheduled to be output from the USB 3 port
on the rear panel in a future firmware upgrade. (As of May
(IQ)
CPU
Master
Clock

DDS
SCOPE(MAIN)
2018)

MIXER DATA
FILTER FFT
(IQ) DRAW

Flash
ROM Scope signal generation
SCOPE(SUB)
DDS
RF-FPGA At the same time, the digitized received signal undergoes
the FFT processing necessary for display of the spectrum
Fig 01-06 FPGA Internal Block Diagram scope, in the FPGA. The FFT-processed signal is sent to
the CPU and displayed on the Scope screen.

Various signal processing features

Signal processing features such as Noise Reduction (NR),
Noise Blanker (NB), NOTCH, PBT, and so on, which had
formerly been implemented in the IF DSP, have now also
been incorporated in the FPGA.

04
Section 02 About RMDR

Basic of RMDR
What is RMDR? At the same time, it has become established that RMDR
performance is more important in high- performance
RMDR = Reciprocal Mixing Dynamic Range. Reciprocal receivers with IP3 specifications at a certain level.
mixing in a receiver occurs when, during the reception of Therefore, when the IC-7850 and IC-7851 were released
a wanted signal, a strong out-of-band interfering signal in 2014, RMDR was highlighted as a key performance
mixes with out-of-band skirt noise from the local oscillator parameter.
(or A/D clock), producing mixing products that fall into
the receiver's detection band, causing the receiver output On the other hand, in a receiver using the RF direct
signal-to-noise ratio to be degraded. RMDR is the ratio of sampling method, as mentioned above, there is no analog
the interfering signal level required to double the audio mixer circuit, so using IP3 as an index of performance does
power output, minus the receiver's noise floor (in dB). not make much sense. For these reasons, we at Icom have
identified RMDR as an indicator of receiver performance,
replacing IP3.
Reason for evaluating receiver
performance with RMDR
A case study where you can experience
Conventionally, it was common to express the performance RMDR
of the receiver by the third order intercept point (IP3)
value. However, when comparing receivers with excellent Ham stations with local stations that transmit powerful
IP3 performance, even if the values are the same, there is radio signals, and when participating in contests with
a difference in actual operation. While investigating and many stations on adjacent frequencies, have experienced
studying the difference, we have focused on the RMDR that weak signals that are barely received by local stations
that various institutions cite as one of the items for receiver are drowned out. Are many people not experiencing this?
performance evaluation. Receivers with excellent RMDR characteristics will be be
much less affected by these problems. Analyzing the sound
output in this interference situation, and in situations that
can be avoided by using the FFT scope, is shown in the
figure below.

Signal is buried in noise Target signal

Figure 02-01 FFT analysis image of received voice output Figure 02-02 FFT analysis image of received voice output
(Receiver with poor RMDR characteristics) (Receiver with good RMDR characteristics)

05
Section 02 About RMDR

The relationship between RMDR and phase noise

About Phase Noise About Jitter

From here we will explain the basic points about RMDR. There is no analog mixer circuits in the IC-7610.
RMDR indicates that the higher the value, the stronger the Why does the same question arise as the conventional
nearby interfering signal is. For this RMDR characteristic, superheterodyne receiver? This is because, in RF direct
the phase noise characteristic of the local oscillator signal sampling, the A/D converter and analog mixer circuit are
is related to the conventional superheterodyne system. considered to be equivalent, and phase noise characteristics
Phase noise is the noise component spreading like the foot and jitter are closely related.
of a mountain. It creates a noise pedestal above and below Jitter is one of the items indicating the performance of
the fundamental frequency signal. This is illustrated in the oscillator used for the reference frequency, the clock for
Figure 02-03. each device, and so on. This is a deviation or fluctuation of
the oscillator output signal in the time domain.
dB dB
Local oscillator Phase noise The clock signal necessary for sampling is applied to the
frequency spreads like a A/D converter. If jitter is included in this clock signal, an
component only
Level

Level

skirt error occurs in the sample value because the sampling

point is shifted. This error acts as phase noise, and its
noise spectrum forms "supersonic" components like the
phase noise of the LO signal as encountered in the analog
mixer circuit.
Frequency Frequency
dB
(a) Ideal signal (b) Actual signal
Input signal
Level

Figure 02-03 Ideal signal and actual signal The point

sampled by the
jitter fluctuates
So why is the phase noise characteristic greatly related to
the RMDR characteristic?
Clock
Original points
In a superheterodyne receiver with a conventional analog to be sampled
mixer circuit, two signals, the target signal and the LO
signal, are input to the mixer circuit. If the phase noise
characteristic of the input LO signal is poor, even if we
try to receive a weak signal below the phase noise level, it Time
will be drowned out by the phase noise itself, so the weak Jitter width
signal will not be recoverable from the mixer. On the other
hand, suppression of phase noise means that the received Figure 02-05 Jitter ~ Relationship between clock and
sampling, as seen in the time axis
signal will start to emerge from the noise, so it will become
audible.
Under this condition of forming "supersonic" components,
dB when weak target signals and strong nearby interfering
: High LO Phase Noise signals are simultaneously input to the A/D converter,
these three signals are "superimposed". Consequently, the
Level

: LO with less phase noise

LO conversion processing of a powerful adjacent interfering

Buried in phase noise
signal takes precedence and weak target signal cannot be
processed. As a result, the RMDR characteristics of the
Received signal
receiver will be affected.
Received signal starts
to appear when phase dB
Master clock : High jitter Master clock
noise decreases
: Master clock with less jitter
Level

Received signal buried

in “foothills” by jitter
Frequency

Figure 02-04 Phase noise and received signal If there is little jitter,
Received signal "foothills" go down,
and the received
signal starts to appear

Frequency

Figure 02-06 Jitter and received signal

06
Section 02 About RMDR

Comparison with conventional transceivers

Comparison of RMDR Comparison of transmission C/N and

As shown in the brochure and product literature, the transmission phase noise characteristics
RMDR of the IC- 7610 is about 110 dB. On the other hand, The low-jitter oscillator is the heart in the master clock
the RMDR of IC-7600 (a conventional transceiver) is about in the IC-7610. As for the C/N characteristic of this master
80 dB, as explained in Volume 1, so here we have an clock, there is no noise pedestal as seen with a conventional
amazing improvement of about 30 dB. Although the classes oscillator. The noise floor is also extremely low, and only the
are different, even if comparing about 102 dB of the IC-7300, target signal can be seen.
which pioneered RF direct sampling, with the conventional
IC-7600 model, the benefit that RF direct sampling has
RBW 30 Hz RBW 30 Hz
Ref 0 dBm VBW 10 Hz Ref 0 dBm VBW 10 Hz
0 0

on RMDR is tremendous, about 22 dB. This should be

-10 -10

-20 -20

abundantly clear to the reader. -30

-40
-30

-40

-50 -50
130 -60 -60

-70 -70

-80 -80

-90 -90
120 -100 -100
Center 14.2 MHz Span 20 kHz Center 14.2 MHz Span 20 kHz

IC-7600 IC-7610
110
Figure 02-08 Transmit C/N Characteristics Comparison
RMDR (dB)

100 In addition, the transmitted signal generated in the FPGA

from the master clock with excellent C/N and phase noise
characteristics will also have excellent C/N characteristics
90
comparable to the receiver, and it is possible to obtain an
IC-7610 extremely clean transmitted signal with minimized phase
80 IC-7300 noise.
IC-7600 0

-10

70 -20
2 10 20 -30
Frequency offset (kHz) -40

-50

Figure 02-07 Comparison of RMDR -60

-70

-80

-90
-100

Expanding this area

↓
–70

Signal Frequency: 14.200 MHz

–80
Signal Level: 0 dBm
IC-7600
–90 IC-7300
IC-7610
–100

–110

–120

–130

–140

–150

–160

100 Hz 1 kHz 10 kHz 100 kHz 1 MHz

Frequency Offset

Figure 02-09 Transmit Phase Noise Characteristics

Comparison

07
Section 03 Block Diagram
ANT1 ANT2

TO RF
RL
RX_B
IC251 IC351

DID1V BUFF FID1V BUFF Q561, D561, D562

RL TUNER
IC151 IC351 RX_A MUTE
IC251 NET
PDIDV BUFF DID2V BUFF FID2V BUFF

T8V
ANTS
NATT1S NATT2S NL0S~NL9S, NL0R~NL9R
3 dB 1.8 MHz D301, D302 NATT1R NATT2R NC1S~NC9S, NC1R~NC9R
TO RF Q101 Q201, Q202 RL402 RL401 NCINS, NCINR, NCOUTS IC2811, IC2821
Q301, Q302
PRE DRIVE PWR PWR/SWR NCOUTR, NCREDS, NCREDR IC2831, IC2841
YGR ATT LPF
DRIVE AMP AMP DET TDAT, TCLK, TOE
SHIFT TSTB1~TSTB4
REGISTER
L1S
3.5 M/3.8 M/4.63 MHz 30 dB Q503
HEAT
IC411 RL352 RL351
SENS
M/M T/R 10 dB D1505, D1506
LPF
CURRENT COUPLER CTRL
DET SWR
THML ATT
DET
L2S
5 M/7 MHz
RL252 IC1901
RL251
DIDL IC401 24 dB T8V
LPF BUFF SWRL

CURRENT
ATT
DET D1201
L3S IC1901
10 M/14 MHz
RL152 RL151 POWER
BUFF TPWRL
DET
FIDL LPF
F2 TO MAIN
1 2 HV
DC 13.8 V RFMON IC351
Q431 L4S
18 M/21 MHz
BUFF FORLP
RL302 RL301 IC1701, D1311, D1312
+14V Q1621 Q1611
LPF
PHASE
BUFF BUFF
DET
IC351
Q432
L5S
24 M/28 MHz
BUFF REFLP
RL202 RL202 D1271, IC1701
PWRS CTRL
LPF
POWER
IMPI
DET
IREFV
PSTB L1S L6S
1 MCK IC941 50 MHz
KEY L2S PHASEI
2 MDAT RL102 RL101
START L3S
TUNER 3 +14V DRESL SHIFT
L4S LPF
4 REGISTER
L5S
L6S

PA UNIT L7S L7S

TUNER UNIT

Q2014, Q2061, Q2062 IC1301 IC1001 IC1101

IC2405 +5V H4V

ALC NASBS HV H3R3V
+14V USA5V HV H3R3V
ALC CTRL DC-DC DC-DC REG
ALC
AMP
IC1251

IC1111 H1R18V
IC2405 IC2405 IC1051 H1R18V
DC-DC
FORLP
ALC ALC BACK-UP TO RF
–12V USA5V
AMP AMP +3R3V CTRL
POCV +3R3V RX-IN [RX-ANT IN]
DC-DC
IC1191
IC1171
IC2407 CAPONS
+2R5V
IC2405 H2R5V
ALC +2R5V REG
ALCL +2R5V
AMP ALC REG
AMP TO RF
RX-OUT [RX-ANT OUT]
Q1122
IC2407 IC1181
ALC
DPALCL Q2012, Q2016 SW SD3R3V
AMP +1R5V
+1R5V
REG
ALC
AMS
CTRL
IC1401 SDPWS

H4V
+8V
+8V
DC-DC TO RF

IC1351 IC1131 X-VERT [X-VERTER]

IC2407
REFLP
ALC –12V USB3R3V
–12V USB3R3V
AMP DC-DC REG
+8V

UPWS TO MAIN
IC2407 IC1241
PFIDL IC1141 REF-IN [REF IN]
ALC
AMP +5V
ICCV +5V
REG F3R3V
F3R3V
REG

Q2010
ALC
EALC FPWS
AMP
IC1161

AD3R3V
AD3R3V
REG

PWRS
IC1201

+1R1V
+1R1V
DC-DC

MAIN UNIT (ALC BLOCK) MAIN UNIT (REG BLOCK) PWRS

CHASSIS UNIT

08
Section 03 Block Diagram

0.03~0.499 MHz 24 dB 12 dB 6 dB 3 dB
TO MAIN fc=1.6 MHz RL RL
RL RL RL RL RL RL
RL RL TO TUNER
ATRRF LPF LPF ATT ATT ATT ATT
HPF RX_A
POFAS BA0AS D1023
RL RL RL RL
Q3335, Q3336 0.5~1.599 MHz REV-PWR
SPLOFS HPFAS
PRE DET
RXS DSELAS RANTAS
2 dB AMP
Q3475 LPF AT24AS AT12AS AT6AS AT3AS
PR1AS
ATT AMP BA1AS RMUTAS TRVRAS
Q3364 Q201 TO CHASSIS
1.60~1.999 MHz RF SPLIT
PRE
BPF RX-IN
AMP AMP
SPLONS
PR2AS BPF RX-OUT
DSRES
BA2AS IC4, IC5 DSCK

DIGISEL-A
fc=60 MHz D3401 DSDAT
2.00~2.999 MHz D_S DSTBA RL
PIN CTRL RL RL
LPF
ATT
BPF UNIT RL RL TO RF
RX_B
TO MAIN
BA3AS IC1 D1012
DRIVE
DSCLA
SPLTRS
3.00~3.999 MHz DSDAA REV-PWR

D3402
IC3421
2.6 dB D3431
BPF-A BOARD EEPROM
DET
RANTBS
BPF
15.00~21.999 MHz
PIN RF PIN
ATT BA4AS RMUTBS TRVRBS
ATT AMP ATT
BPF
4.00~5.999 MHz
BA9AS
DPGV
TO CHASSIS
BPF
22.00~29.999 MHz
ALC X-VERT
T8V BA5AS
BPF
6.00~7.999 MHz RXS
BA10AS T5V DSELADJ RANTBS HPFBS
BA6AS TRVRBS DSELBS
IC1201, IC1202
SPLONS BA7AS BPF RMUTBS DSELAS
IC3502, IC3503 30.00~60.00 MHz
BA0AS BA8AS SPLTRS HPFAS
MCK, MDAT, RSTB1, DRESL SHIFT
MCK, MDAT, RSTB4, DRESL BA1AS BA9AS BA6AS TRVTS AT3BS PW2RLS
SHIFT REGISTER
BA2AS BA10AS BPF AT6BS
REGISTER 1.8 dB IC1091 fc=60 MHz 1.8 dB
BA3AS BA11AS AT12BS
8.00~10.999 MHz
BA4AS BA12AS BA11AS TO PA AT24BS
YGR
BA5AS BA12TXS ATT LPF ATT YGR
AMP
BPF
50.00~54.00 MHz(RX)
BA7AS TRVTS
BPF
POFAS T5V RANTAS
IC3504 11.00~14.999 MHz IC1203
PR1AS TRVRAS
PR2AS RMUTAS
MCK, MDAT, RSTB5, DRESL SHIFT MCK, MDAT, RSTB2, DRESL SHIFT
POFBS BPF BA12AS AT3AS
REGISTER 50.00~54.00 MHz(TX) REGISTER
PR1BS AT6AS
PR2BS BA8AS AT12AS
ASQLS BPF AT24AS
SPLOFS

fc=1.6 MHz Q1091, Q1092

BA12TXS
0.03~0.499 MHz 24 dB 12 dB 6 dB 3 dB
HPF T8V CTRL T5V
TO MAIN RL RL RL RL
BRRF LPF LPF ATT ATT ATT ATT

POFBS BA0BS
DSELBS
RL RL RL RL
Q2335, Q2336 HPFBS
0.5~1.599 MHz
SPLOFS
PRE
2 dB AMP
Q2471 LPF AT24BS AT12BS AT6BS AT3BS
PR1BS
ATT AMP BA1BS
Q2364
PRE 1.60~1.999 MHz Q201
AMP RF
SPLONS BPF
AMP
PR2BS BPF
DSRES
BA2BS DSCK Q4003
IC1 IC4, IC5 DSDAT
DSTBB EPAD1L
2.00~2.999 MHz [EXT KEYPAD]
ASQLS CTRL
D_S
EEPROM EPAD2L
CTRL
BPF
DSCLB TO MAIN
BA3BS DSDAB 14V IC4002
Q4005
METAV BUFF
DIGISEL-B UNIT
3.00~3.999 MHz
RTKI CTRL
BPF IC4002
[ACC (1)] [METER]
6

BPF-B BOARD
BA4BS 1: RTTY METBV BUFF
7
Q4004, Q4006, Q4007 1 7 6 2: GND
4.00~5.999 MHz 15.00~21.999 MHz 8 3: SEND
SENI 4: MOD
3
BA6BS CTRL 3 8 1 5: AF
4
IC2502, IC2503 BA7BS BPF BPF TRAS 6: SQLS
2
BA0BS BA8BS 7: 14V KEYI
5 5 4 [KEY]
MCK, MDAT, RSTB3, DRESL BA1BS BA9BS BA5BS BA9BS 8: ALC
SHIFT 2
REGISTER BA2BS BA10BS Q4008
BA3BS BA11BS 6.00~7.999 MHz 22.00~29.999 MHz TO MAIN TO MAIN
BA4BS BA12BS
BA5BS TRVI CTRL
BPF BPF CIVE
CIV
[REMOTE]
BA6BS BA10BS [ACC (2)]
IC4001
6
8.00~10.999 MHz 30.00~60.00 MHz 7
ACC5V BUFF 7 6 1: 8V PW2RLS
1
2: GND
BPF BPF 3: SEND PW2FB
3
IC4001 3 1 4: BAND
4
BA7BS BA11BS 5: ALC EALC RL [ALC]
2 Q341, Q342
BANDV BUFF 6: TRV
5 5 4 7: 14V
11.00~14.999 MHz 50.00~54.00 MHz 2 EXRL1S RELAY
[SEND]
BPF BPF EALC
IC4003
BA8BS BA12BS AMOD

AAF EXRL2S MOS-FET

RF UNIT

09
Section 03 Block Diagram

REFULK IC9021 IC9031 U3_D00~D31, U3_BE0~BE3, U3_RXE,U3_TXE, U3_SIWU, U3_WR IC9401

13
6 dB
Q2410 IC2451 U3_DB, U3_CLK,U3_RESET, U3_WKUP, U3_RD, U3_OE
1
BUFF BUFF VBUS
REFCK, REFDT, REFLE IC2511 CH0 USB3.0 2
EXT-REF IN ATT AMP BUFF REFLVL D-
I/F 3 IC3201
D+
4
GND IC3151
5 USB 2
BUFF & IC9041 SSTX-
Distribution 6 AF AF L
Q2431 Q2302 SSTX+ PHOL
X2302 CH1 IC9481 7 AMP AMP
IC2412 IC2411 BUFF GND DRAIN
X2401 PLL LOOP ALCS 8
AMP AMP SSRX-
IC FIL ALCK IC9501 X9401 9
REFV BUFF BUFF EEPROM SSRX+
ALDO 30.0 MHz 10
DPWR IC3151
IC2301 11 TO FRONT (DISPLAY)
A/D DPALCL DGND
CH3 CH2 AF AF R
REFSEL PHOR
AMP AMP

12
DCLK AFO
DCLK#
D8051~D8055 IC8201 FPCAL IC3001
IC8101
TO RF FPX_SPK RL [EXT-SP A]
MCLK, FRM, BCLK FPR_MOD IC3011 IC3031 IC3061 SPAK
PIN
ATRRF AMP A/D
ATT L AF AF AF
D/A LPF SW
AMP AMP AMP
LTC2208
RBT_CK, RBT_DO, RBT_CFG
RXS AGCAV SPONAS
RSC_CS, RSC_CK, RSC_DO
ADJA FC_BCLK, FC_CS, FC_RD, FC_WE, FC_A1~A4, A7

IC8901
RF-FPGA RL [EXT-SP B]
FC_D0~D15 IC3011 IC3031 IC3051 SPBK
D8551~D8555 IC8701
IC8601
TO RF R AF AF AF
D/A LPF SW
PIN AMP AMP AMP
BRRF AMP A/D
ATT RSC_DI, FC_WAIT, FC_DREQ RL

LTC2208
RXS RXS SPONBS SW
ADJB AGCBV INT SP
TXS

ISPBS
IC9101 IC3101
TXS IC3111 IC3102
ADJB AMOD
R MIC MIC Q3122
LPF D/A A/D
AMP AMP
UMOD MIC8V
SW
ISL5961
MIC8VS
DR_PLY, DR_MOD
ADJA UMODS
X4021 FPSX, DCSAX, DCSAR
12.5 dB IC4521 48 MHz DCSBX, DCSBR, IC3121 IC3102
TO TUNER DSPCK1, DSPR L MIC MIC
SCPSEL A/D AMP AMP MICI TO FRONT (DISPLAY)
RTC_IRQ,RTC_SCL,RTC_SDA
RFMON ATT RTC

BT4221 DSPAX, DSPBX,

DX_AF, DX_REC,DX_MIC, IC3301
PW2FBS
12.5 dB DX_FMT, DX_IF, FPDX,
TO RF USB1HM,USB1HP,USB2HM,USB2HP MCLK, FRM, BCLK FPX_DET IC3311
FRM, BCLK
IC4211 L AF
PW2FB ATT D/A UAFA
AMP
IC4171 USB2PENC, USB2OVC ECK, EDT
TO FRONT (USB) EEPROM
USB1_5V USB1PENC, USB1OVC
USB2_5V VBUS
SW VBUS0, VBUS1 IC3311
Q9156 RZM_SFLD0~SFLD3 IC4201 R AF
RZM_SFLSS, RZM_SFLCK D/A UAFB
TO RF AMP
ADJA
REFSEL, REFULK, REFCK, REFDT, REFLE FLASH
DSELADJ CTRL
ROM
ADJB
SD_WP, SD_CD, SD_D1, SD_D0 IC4361 IC3341
SD_CLK, SD_CMD, SD_D3, SD_D2
IC431 TO FRONT (SD) HV FPX_DPD IC3351
PDV VDET
IC4001 L AF
PFIDL BUFF D/A AAF
LTXD, LRXD, PWRK, FRES, FSENI, FTRAS MAIN CPU AMP
TO FRONT (DISPLAY) IC5151
IC4231
IC431 TPWRL, IMPI, SWRL, PHASEI
TO TUNER H3R3V SDRAM IC3351
RESET RESET
PDIDL BUFF IC5001 R
COMM-FPGA D/A AMP DPGV
FIDL
DIDL RZM_BUS
VDL
VDL
HSK1, FRWT, DRESD, SCPCK, SCPSS, SCPR, SCPX IC9202
CAPONS
IC1021 IC9201, Q9201
UPWS
FPX_AGC
SDPWS
FAN UDRXD1, UDBSY, UDTXD1 IC5101 L DC
IDET FANI FPWS D/A AGCBV
AMP
PWRS
RXS SDRAM
CTXD RFL_DI
TXS
Q451, Q452 CRXD, CBSY RFL_DO IC9651 IC9201, Q9202
IC1021
RFL_CK
FAN FANV LAN_BUS RFL_CS FLASH R DC
FAN CTRL BUFF D/A AGCAV
ROM AMP
X6021
48 MHz
IC421
UDRXD1,UDBSY,UDTXD1
FORLP BUFF
IC6211
RZD_SFLD0~SFLD3 IC7101
RZD_SFLSS/RZD_SFLCK FLASH
IC421 FORL ROM IC7001 Q7012, Q7011 Q7002, Q7001 IC7001 IC7021 IC7051
26

1
REFL CTXD PWRON2
2 REFLP BUFF RTAD, PSKAD, RTBD, PSKBD CI-V CI-V UCRXD, UCTXD USB
3 BUFF BUFF SW
CRXD, CBSY I/F I/F BRIDGE DP2, DM2
4
5 REFV ALCL
RZD_BUS
6 UMODS REFLVL
7 MIC8VS KEYI CIV UCLKS
8 METAV TRVI
USSPD1, USKI1, USSENI1, USSPD2, USKI2, USSENI2, UDRXD2, UDTXD2, UDRES USSPD1, USKI1, USSENI1
9 METBV RTKI USB 1
10 EXRL2S SPAK
11 EXRL1S SPBK
EXT-DISPLAY TRVTS
12 FID1V
IC501 IC7071

3
4
13 IC6001 FID2V
MP1XL, MP1YL PWRON3
14 SUB CPU THML DID1V
MPSA, MPSB MULTI USSPD2, USKI2, USSENI2, UDRXD2, UDTXD2, UDRES USB USB HUB
15 IC7001, Q7021, Q7022 PLEXER FANI DID2V BRIDGE DP3, DM3
16 EPAD1L PDIDV
START, KEY TCON, ESTA, EKEY

2
1
17 EPAD2L IREFV
TO PA TUNER
18 POCV
I/F IC401
19 DRIV UMOD VBUS
TMDS_D2+, TMDS_D2- IC7031
20 MCK, MDAT, RSTB1~RSTB5, DRESL ICCV
TMDS_D1+, TMDS_D1- IC6201 DVIPD, DVIMSEN, DVIDT, DVICK, ELCD_RST DSTB PWRON4
21 D/A BANDV
TMDS_D0+, TMDS_D0- ELCD_R3~R7, ELCD_G2~G7, ELCD_B3~B7 TO RF USB
22 UAFA CODEC
TMDS_CLK+, TMDS_CLK- DVI ELCD_DE/ELCD_CLK/ELCD_HS/ELCD_VS LAN_MDIO, LAN_MDC, LAN_RSTL DP4, DM4
23 XMITER UAFB
MCK, MDAT, PSTB, DRESL LAN_TXD0~TXD3, LAN_TXER, LAN_TXEN

9
24 1
25

TO PA LAN_CRS, LAN_COL, LAN_RXDV, LAN_TXCLK

SPONAS LAN_RXCLK, LAN_RXD0~RXD3, LAN_RXER 2
IC7401 X7111
SPONBS 3 (6.000 MHz)
CLKM, CLKP TCLK, TDAT, TSTB1~TSTB4, TOE TX+, TX-, RX+, RX- IC7032
PHONS 4
LK0M, LK0P IC6301 TO TUNER IC411 LAN LAN
ISPBS DRIVER 5 X7031
LK1M, LK1P LCD_R3~R7, LCD_G2~G7, LCD_B3~B7 BIAS
ANTS 6 (12.000 MHz)
LK2M, LK2P LVDS LCD_DE, LCD_CLK, LCD_HS, LCD_VS MCK, MDAT, DRESL MSTB SHIFT CTRL
XMITER REGISTER AMS 7
TO FRONT (DISPLAY)
NASBS 8

10
MAIN UNIT
PW2FBS X7401
25.0 MHz

10
Section 03 Block Diagram

FRONT UNIT
PBT
PUSH SW,
VR, ENCODERs
F3R3V
BOARD
Q505 Q752

JACK BOARD TIMER

NB
NR MP-W
[TRANSMIT]
SBYDS
CTRL
STAND BY MAINDS
CTRL
MAIN PBAAK
PBABK
TUNER
[PHONES] SUB AF MP-R TRSK
MAIN AF
(AFSK) AUTO TUNE PBBAK
(AFMK)
MENU PBBBK
[M.SCOPE] Q506 Q751
MSCK MAIN PBTK
PWRDS POWER MAINTDS TRACKING

KI0

KI1

KI2
CTRL CTRL PBT

[QUICK] [KEY SPEED]

[ELEC-KEY] 1.8 3.5 7 QUICKK KSPDL
10 14 18 SPLIT
21 24 28 DUAL-W Q507 Q753
GENE 50 MAIN/SUB [XFC]
[PITCH]
XFCK TMRDS TIMER SUBDS SUB PTCHL
CTRL CTRL

KI3

KI4

KI5

KI6
[CHANGE]
EXIT PBT CHGK Q509 Q754
RIT
REC (PBTK) SUB
∆TX TUNER ON
MIC BOARD
Q581, Q582 PLAY FILTER TUONDS SUBTDS TRACKING
RIT CLEAR CTRL CTRL
SPEECH,LOCK APF, TPF
RIT DIAL
CURRENT USA5V
LIMIT

KI7

KI8

KI9
1 MIC FSQS Q508 Q861
FSQS
7 MICE
1 7 2 +8V TUNEDS TUNE PBTDS PBT RITAK
CTRL CTRL
8 AF OUT
6 GND RITBK
2 8 6
3 MIC U/D
4 SQL
3 5 5 PTT Q502 Q862 EX-3956
4 Q571~Q573 MULTIPLEXER EXPANDER
IC451, IC452 IC401~IC403 TMDS MAIN TX FILDS FILTER
CTRL CTRL

MULTI
SEND
SW

Q501 Q863 BOARD

Q521
AS0, AS1 FCK, FDAT RMDS MAIN RX APFDS APF/TPF MFDAK
ASL0, ASL1, ASL2 FSTB, FOE CTRL CTRL

F3R3V

F3R3V
SQL FSQS

VR BOARD
MFDBK

Q511 MFK
F3R3V
PHK
AFMK DOTK NBDS NB
MAIN AF CTRL
DSHK

MAIN DIAL
[AF GAIN] USA5V
AFML FUDL
Q510
MAINDAK
[RF/SQL] FRONT CPU NRDS NR MAINDBK
RFML CTRL
IC101

MAIN EX-3210

Q504 DISPLAY BOARD

TSDS SUB TX
CTRL

USB BOARD
AFSK SUB AF

[AF GAIN] Q503

BKLV

FLRXD
FLTXD
FRES
AFSL
RSDS SUB RX
F3R3V CTRL

6
TWCS, TWBUSY 4
[RF/SQL] TWDTX, TWDRX 3
RFSL
TWDCLC, TWPIRQ 2
1
SUB Q512 D+1, D-1, VBUS1

5
D+2, D-2, VBUS2
SDDS SD ACCESS
CTRL

6
DS1 (LCD) 4
3
2
IC221, IC222
1
VLED-

5
LCD USA5V
LCD VLED+
LIGHT
LIGHT CTRL

SD BOARD
R3~R7, G2~G7, B3~B7 IC453
LCK, HS, VS, DE Q303, Q304
LVDS
RECEIVER DIM LDPS
LCD IC301 CTRL SDDAT0, SDDAT1, SDDAT2,
LEDV SDCMD, SDCLK, SDCD, SDWP,
#9:DAT2
SD3R3V
BUFF #1:CD/DAT3
STBV
#2:CMD
IC251
#3~#1:VSS
XR, YD, XL, YU
Q301, Q302 #3~#2:VSS
LCD-TW TW-CTRL #4:VDD
POWER KEY #5:CLK
DIM
CTRL CD
D3R3V
#6:VSS
#7:DAT0
#8:DAT1
WP1
WP2
D3R3V

LCD_ON

LK0M,LK0P
LK1M,LK1P
LK2M,LK2P
CLKM,CLKP

FSENI

FTRAS

AFO
MICE
MICI
+8V

PHOL

PHOR

PHE

FLRXD
FLTXD
FRES

PWRK

USA5V

F3R3V

HV

MAIN UNIT
LVDS

11
1-1-32 Kamiminami, Hiranoku, Osaka 547-0003, Japan