A 4th-Order Continuous-Time Delta-Sigma Modulator

with Hybrid Noise-Coupling

<Author Placeholder>
<Affiliation Placeholder>

Abstract—A hybrid noise-coupling (HNC) technique is Digital NC Filter (HD)

proposed to mitigate the issues with a digital noise-coupling
(DNC) structure. In the proposed technique, the unwanted
quantization noise that is generated from the noise-coupling ADC NC-DAC NC-ADC EQ2
is injected into the input of the quantizer with one-clock cycle
delay, thus increasing the order of noise-shaping of this error. EQ1

Behavioral simulation shows that the HNC is highly robust U L(S) DDNC
against gain variation. The proposed fourth-order CT DSM with
HNC scheme was fabricated in a 28-nm CMOS technology with a Main-ADC
core size of 0.3mm2. With an OSR of 32, the proposed design Single SAR ADC
achieves a SNDR of 97.20-dB at a signal bandwidth of 15.625-
Main-DAC
kHz, which has a 7-dB improvement in comparison to DNC only
without introducing significant hardware complexity.
Fig. 1. Block diagram of DNC structure.
Keywords—Analog-to-digital converter (ADC), continuous time To further enhance the performance of the DSM with the
delta-sigma modulator (CT DSM), digital-domain noise coupling DNC scheme, in this paper, a hybrid noise-coupling (HNC)
(DNC), analog-domain noise coupling (ANC), hybrid noise structure is proposed for which a simple ANC filter is
coupling (HNC). constructed with simple buffers.
The remainder of this paper is organized as follows.
I. INTRODUCTION
Section II briefly reviews the previous DNC scheme and also
In recent biomedical systems, continuous-time delta-sigma presents the proposed HNC technique. Section III describes the
modulators (CT DSM) are often employed due to their detailed circuit implementation of a fourth-order CT DSM with
advantages such as inherent anti-aliasing characteristics and HNC while its post-layout simulation results are shown in
high-resolution performance [1-2]. In conventional DSMs, the Section IV. Conclusions follow in Section V.
order of the noise-shaping is determined by the number of
integrators used. This means that the number of power- II. NOISE-COUPLING STRUCTURE
consuming operational amplifiers (opamps) should be
increased to improve the performance. To circumvent the A. Previous Digital Noise-Coupling
opamp-related power overhead, noise-coupling structures can
be utilized without increasing the number of opamps. Fig.1 shows a simplified block diagram of the DNC
structure in [4]. In this structure, the EQ1 is converted first to
However, a high-order noise-coupling (NC) structure digital code through the NC-ADC and then processed in the
implemented in the analog domain has several disadvantages. digital filter (HD). Then, the output of the digital filter is fed to
These include such as circuit complexity and sensitivity to the NC-DAC and injected back to the input of the quantizer,
process, voltage, and temperature (PVT) variations [3]. A completing the loop for the digital noise-coupling. As
digital domain filter [4] was proposed to address the issues previously mentioned, the circuit implementation of the digital
with the analog noise-coupling (ANC) structure. The digital filter consists only of registers and adder. Moreover, the main-
noise-coupling (DNC) in [4] eliminates the power-consuming ADC, NC-ADC, and NC-DAC are embedded in a single SAR
analog circuits and sensitivity to PVT variations, and realizes a ADC which makes the overall circuit implementation very
simple noise-coupling filter just by using delays and an adder. efficient. However, an unwanted quantization error, EQ2, is
Furthermore, DNC also allows the use of a lower resolution for generated. The output of the DNC structure can be derived as
the feedback digital-to-analog converter (FB DAC) which
reduces the complexity of the data-weighted averaging (DWA)
logic. However, the quantization error produced by the main DDNC = STF·U + NTF·(1 – HD)·EQ1 – NTF·HD·EQ2 (1)
analog-to-digital converter (ADC), EQ1, needs to be converted
first to digital code before it is injected into the DNC filter. where STF and NTF are L(s)/(1+L(s)) and 1/(1+L(s)),
This conversion generates an unwanted quantization error, EQ2. respectively. It can be seen in (1) that EQ1 is shaped by the
This EQ2 limits the performance in the low-frequency band DNC path as well as the main loop. For example, if the DNC
because it is only shaped by the loop filter (LF). filter is set to 2z-1 – z-2, then 1 – HD becomes a second-order
high-pass filter which gives additional second-order noise- HD = 2z-1 – z-2
shaping to EQ1. On the other hand, EQ2 is only shaped by the
main loop because the frequency response of HD is only flat at Digital
NC-DAC NC-ADC EQ2
low frequency. Therefore, the overall frequency response of Analog Proposed
ANC Path
the noise-shaping in the DNC architecture will show two EQ1
slopes where EQ1 dominates the high-frequency region while Z-1

EQ2 dominates the low-frequency region. This implies that EQ2 U L(S) DHNC
may limit the performance in the signal band. 2nd-Order
Main ADC

B. Proposed Hybrid Noise-Coupling

Main-DAC
The residue (EQ2) remaining after the NC-ADC operation in
the DNC technique can be further suppressed by combining it Fig. 2. Block diagram of the proposed fourth-order CT DSM with HNC.
directly with the next input signal to the quantizer. The result
of merging this simple ANC path with the existing DNC path,

Normalized Power (dB)

Normalized Power (dB)

0 0
is the HNC scheme. BW EQ1 BW EQ1
–20 –20
EQ2
Fig. 2 shows a simplified block diagram of the proposed –40 EQ2 –40

fourth-order CT DSM with HNC scheme where EQ2 is coupled –60

40 dB/dec
–60
60 dB/dec
in the input of the quantizer with a one-clock cycle delay. This –80 –80

simple analog path becomes a first-order noise-coupling filter –100 80 dB/dec –100 80 dB/dec
that increases the order of the noise-shaping of EQ2, thereby –120 –120

improving the SQNR performance. Based on the block 10 -3 10 -2 10 -1 10 0 10 -3 10 -2 10 -1 10 0

diagram of HNC, the output can be expressed as Normalized Frequency Normalized Frequency

(a) (b)
DHNC = STF·U + NTF·(1 – HD)·EQ1 – NTF·(HD – z-1)·EQ2 (2) Fig. 3. Frequency Response of HNC Structure: (a) ANC is disabled and (b)
ANC is enabled.
It is shown in (2) that EQ1 is still shaped by the main loop
unit capacitor.
and the DNC path while EQ2 is now shaped not just by the
main loop but also by the ANC path. In DNC only, EQ2 is The detailed SAR operation is shown in Fig. 5. During the
multiplied by HD, which is flat on the low frequency. In the sampling phase (Step 1), the bottom nodes of the NC-DAC are
proposed architecture, owing to the added analog path, EQ2 is connected to the reference voltages depending on the output of
now multiplied by HD – z-1, which is equivalent to a first-order the DNC filter. Furthermore, the odd residue capacitor
high-pass filter, where HD is 2z-1 – z-2 for a second-order DNC transfers the previous EQ2 in the buffer while the even residue
and HD – z-1 is z-1(1 – z-1). This means that the noise floor capacitor is connected in the top node of the CDAC. When the
limited by EQ2 in the signal band is pushed down further, as sampling is done, the NC-DAC switches back to the common
illustrated in Fig. 3, increasing the overall performance. level to perform the subtraction to realize the noise-coupling
(Step 2). Then, a 4-bit main A/D conversion is made with the
III. CIRCUIT IMPLEMENTATION hybrid noise-coupled input (Step 3). As soon as the conversion
is done, EQ1 is left at the top node of the CDAC and this
In order to determine the resolution of the ADC, the design becomes a direct input for the next NC A/D conversion. As
target was specified first. In this work, the target SNDR was 90 also explained in [4], after the NC A/D conversion is done, EQ2
dB. For the signal bandwidth of 15.625 kHz, the oversampling is now readily available in the top-plate of the CDAC (Step 4).
ratio (OSR) was chosen to be 32, which results in a 1 MHz This residue voltage is now stored in the even residue capacitor
clock frequency. The DNC filter and LF were both set to be and will be used in the next cycle.
second-order. As a result, an overall fourth-order noise-shaping
was obtained. One possible issue with the proposed structure is the gain
variation within the ANC path and its effect on the noise-
A. SAR-Assisted Hybrid Noise-Coupling shaping performance. Fig. 6 shows behavioral simulations of
the SNDR of the proposed architecture with respect to the gain
The detailed implementation of the proposed SAR-assisted
variation in the ANC path. It can be seen that the proposed
HNC structure is shown in Fig. 4. Single-ended representation
structure is highly robust against the gain variation in the ANC
is shown for simplicity. In this design, a 7-bit asynchronous
path with degradation of only 1.5 dB within ± 20% variation.
SAR ADC was used with a 4-bit main-ADC, a 3-bit NC-ADC,
This allows the design requirements for the buffer and for the
and a 4-bit NC-DAC. For the ANC, two residue capacitors
capacitor ratio (CANC/CINT2) to be relaxed.
were added that operate in a ping-pong fashion (odd and even
samples). One residue capacitor stores the present EQ2 while
the other residue capacitor holds the previous EQ2 which will B. Fourth-Order CT DSM With HNC
be transferred through a buffer and capacitor (CANC) and then Fig. 7 shows the detailed implementation of the DNC filter.
to the summing node of the last integrator. This single SAR Due to the structural advantages of the CDAC-based SAR
ADC was implemented with a split-capacitor DAC (CDAC) ADC, the implementation of the DNC filter can be made
[5]. The total size of the SAR CDAC was 128 fF with a 500 aF simpler than in [4] by removing the adder block and by
 ƀODD ANC PATH
CINT2 CANC 1

HD = 2z-1 – z-2 RINT2 1

 ƀEVEN

4b
NC-DAC NC-ADC EQ2 HD = 2z-1 – z-2
DEQ1
HD·D EQ1
NC-DAC RES CAP
EQ1 ƀCOMP
ƀSAMP

Asynchronous
ƀSAMP Z-1

Digital Logic
LF_OUT ƀODD ƀEVEN
DOUT
DOUT
MAIN-ADC NC-ADC
3b LSBs
MAIN-ADC
4b MSBs

Fig. 4. Detailed implementation of HNC architecture with 7b SAR ADC.

Ts Ts
Step 1: Sampling and ANC ƀCLK Step 3: Main A/D Conversion ƀCLK
ƀODD ƀODD
CINT2 CANC 1
ƀEVEN CINT2 CANC 1
ƀEVEN
z-1·EQ2
RINT2 1 ƀODD RINT2 1 ƀODD
ƀEVEN ƀEVEN
- -
HD·D EQ1 4b 4b
HD = 2z-1 – z-2 HD = 2z-1 – z-2
EQ1
NC-DAC
ƀCOMP ƀCOMP

Asynchronous
Asynchronous

ƀSAMP ƀSAMP

Digital Logic
Digital Logic

ƀODD ƀEVEN DOUT ƀODD ƀEVEN DOUT

Main-ADC
3b LSBs 3b LSBs
4b MSBs 4b MSBs

Ts Ts
Step 2: Subtraction ƀCLK Step 4: NC A/D Conversion and DNC ƀCLK
ƀODD ƀODD
CINT2 CANC 1
ƀEVEN CINT2 CANC 1
ƀEVEN

RINT2 1 ƀODD RINT2 1 ƀODD

ƀEVEN ƀEVEN
- -
4b 4b DEQ1
HD = 2z-1 – z-2 HD = 2z-1 – z-2
EQ2
VLF_O UT – HD·DEQ1
ƀCOMP ƀCOMP

Asynchronous
Asynchronous

ƀSAMP

Digital Logic
ƀSAMP
Digital Logic

ƀODD ƀEVEN ƀODD ƀEVEN DOUT

DOUT
NC-ADC
3b LSBs 3b LSBs

4b MSBs 4b MSBs

Fig. 5. Detailed SAR operation.

IV. SIMULATION RESULTS
performing addition directly in the charge-domain through the
CDAC. Thus, the DNC filter is implemented only by registers The proposed 15.625-kHz BW fourth-order CT DSM with
and the output is directly fed into the driver of the CDAC, HNC was designed with 28 nm CMOS technology. The core
reducing the propagation delay. This is preferable in a high- layout is shown in Fig. 9. The total active area is 0.3mm2 while
speed application. the total power consumption is 255 μW under a supply voltage
of 1.8 V utilizing only thick-gate transistors.
Fig. 8 displays the overall implementation of the proposed
fourth-order CT DSM with the HNC technique. Excess-loop Fig. 10 shows the post-layout FFT spectrum to illustrate the
delay (ELD) was compensated through ELD-CDAC, of which effect of the HNC with transient noise included. When the
the output is injected into the summing node of the last ANC path is disabled (only the DNC is enabled), EQ2 has only
integrator. On the other hand, the LF was implemented using second-order noise-shaping characteristic, limiting the entire
an active-RC integrator. The amplifier used in the first performance in the signal band. When the HNC works with the
integrator is a two-stage opamp with feedforward ANC enabled, EQ2 has now a third-order noise-shaping
compensation while the second integrator utilizes a characteristic. The flat noise floor within the signal band
conventional two-stage opamp. Chopping with a frequency of implies that performance is now only limited by thermal noise.
Fs/2 is implemented in the first integrator to mitigate the 1/f Thus, the overall performance is significantly improved,
noise. increasing the SNDR by 7 dB, from 90.62 dB to 97.20 dB.
The overall performance of the modulator is summarized in
 0
HNC OFF
SNDR = 90.62 dB
1.5 dB -20 SNDR = 97.20 dB
BW HNC ON

Normalized Power (dB)

-40

-60 EQ1

-80

-100
Fig. 6. SNDR vs gain variation of ANC path.
-120

HD = 2z-1 – z-2 80 dB/dec

-140
DZ1 3b
ƀCOMP 103 104 105
LSBs
ƀSAMP
Asynchronous
Digital Logic
Frequency (Hz)
4b DZ2[2:0]
DEQ1[2:0] DZ1[2:0]
MSBs
D Q D Q Fig. 10. Simulated output FFT spectrum with 5-kHz input frequency.
DZ2
CLKDNC
NC-DAC TABLE I. PERFORMANCE COMPARISON
This
Fig. 7. Detailed implementation of DNC filter. [6] [7] [8] [9] [10]
work*
CANC ANC EQ2
Tech. (nm) 180 65 28 65 160 28**
1
Supply (V) 1.8 1.0 3.3/1.0 1.0 1.6 1.8
CINT1 CINT2 DNC Filter
CFF BW (kHz) 24 25 24 25 20 15.625

RINT1 RINT2
LSBs Power (μW) 280 175 1130 800 390 255
VIN MSBs SNDR (dB) 98.5 94.6 98.5 95.2 91.3 97.2
DOUT
FoMS*** (dB) 177.8 176.2 171.8 170.1 168.4 175.1
FB ELDC
7b SAR ADC
* Post-layout simulation ** Thick-gate transistors only *** FoMS=SNDR (dB) + 10log(BW/Power)
RDAC CDAC

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Fig. 8. Overall implementation of the proposed architecture.
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