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Sri Indu College of Engineering & Technology: Setno1 Code No.: R20Ece2102

The document contains a sample question paper for the subject "Digital Logic Design". It has 15 questions divided into 5 units. The questions assess students' understanding of digital logic concepts like Boolean algebra, logic gates, flip-flops, counters, finite state machines and sequential circuits. Students are evaluated on their ability to apply concepts to problems involving number conversions, logic simplification, circuit design and analysis of sequential elements. The paper also aims to test higher-order skills like critical thinking and design.

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mohan
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60 views

Sri Indu College of Engineering & Technology: Setno1 Code No.: R20Ece2102

The document contains a sample question paper for the subject "Digital Logic Design". It has 15 questions divided into 5 units. The questions assess students' understanding of digital logic concepts like Boolean algebra, logic gates, flip-flops, counters, finite state machines and sequential circuits. Students are evaluated on their ability to apply concepts to problems involving number conversions, logic simplification, circuit design and analysis of sequential elements. The paper also aims to test higher-order skills like critical thinking and design.

Uploaded by

mohan
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Set NO 1

Code No.: R20ECE2102

SRI INDU COLLEGE OF ENGINEERING & TECHNOLOGY


(An Autonomous Institution under UGC, New Delhi)

Recognized under 2(f) and 12(B) of UGC Act 1956

DIGITAL LOGIC DESIGN

Time: 3 Hours Max Marks: 70

Part - A (5Q X 4M = 20 marks)

Marks Course BT
outcome . Level
1 Implement the function with only NAND gates: F(x,y,z) = Σ(0,6). (4) Postulates of 5
Boolean algebra
2 What are Hazards? List their types. (4) Known about 1
the Hazards
3 Differentiate combinational and sequential circuits? (4) Known about 3
the different
circuits.
4 What is a Ring Counter? What are applications of Ring counters? (4) Analyzing the 2
sequential
circuits
5 Write capabilities and limitations of Finite-State machine. (4) Known about 4
the FSM
Part – B (5Q X 10M = 50 Marks)

UNIT-I Understand the


numerical
6. a) i) Convert the given Octal number (2564. 603)8 to Hexadecimal Number. (10) information in 3
different forms.
ii) Given that (81)10 = (100)X , Find the value of X.

b) Encode data bits 1101 into 7 bit even parity Hamming Code.

(OR) 5

7. a) Expand min-term and maxterm AB′+ABD′+A+ABC′D.

b) Prove that AB'C + B + BD'+ ABD'+ A'C = B + C.

UNIT - II Realization of
K-map and
8. a) Simplify the following Boolean expression using K- map and implement (10) designing of 4
them with NOR logic gates F(A,B,C,D)=  m ( 1,3,7,11,15 ) + d(0,2,5) combinational
circuits
b) Draw and explain the full adder circuit using two half adder circuits.

( OR)

9. a) Design a digital system to compare two binary numbers of 1 bit by using


logic gates. 6
b) Design and explain a 3 to 8 decoder with necessary truth table and logic
diagram.

UNIT - III (10) Analysing the


different
10. a) Derive the characteristic equation for JK flip-flop and T flip-flop. flipflops. 1

b) Discuss about binary cell in detail.

(OR) (10)

11. a) With the aid of external logic, convert D type flip-flop to a SR flip-flop. 3

b) Explain master slave JK flip-flop with neat timing diagram.

UNIT - IV (10) Designing of


sequential
12. Draw the circuit of mod-12 asynchronous up and down counter using JK circuits. 4
flip-flop.

(OR)

13. a) Construct a Johnson counter for 10 timing signals.


2
b) What are the fundamentals of Sequential machine operation?

UNIT-V (10) Analyse ASM


charts and
14. a) Draw the State diagram, State table and ASM chart for a D flip-flop. Moore model. 4

b) With a neat block diagram, explain the Moore model of a clocked


synchronous sequential circuit.

( OR)
6
15. Design a sequential logic circuit of a 4 bit counter to start counting from
0000 to 1000 and this process should go on. Draw the ASM chart and design
the Data processing unit and the control unit.

Note: Subdivisions if required can be added Eg: 6(a), 6(b)… and suitable marks need to be mentioned

Summary (to be filled by the question paper setter):

Indicate the percentage for each of the following criteria from the questions framed; Total no of questions
given:

Bloom Taxonomy level No.of


question % Name of Paper setter
s
1. Fundamental knowledge from Level I & II 4 27

2.Knowledge on application and analysis from Level III & IV 7 46

3.Critical thinking and ability to design from Level V & VI 4 27

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