Design and Implementation of

VLSI Systems
Lecture 03

Thuan Nguyen
Faculty of Electronics and Telecommunications,
University of Science, VNU HCMUS
Spring 2012
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Ref: Neil H.E. Weste, David Money Harris; CMOS VLSI Design: A Circuit and Systems Perspective 4th
CONTENT

1 Semiconductor Fabrication

2 Layout & Design Rule

3 Stick Diagram

4 Euler path

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CONTENT

1 Semiconductor Fabrication

2 Layout & Design Rule

3 Stick Diagram

4 Euler path

3
SEMICONDUCTOR MANUFACTURING
 Chips are built in huge factories called fabs
 Contain clean rooms as large as football fields

Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.
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BASIC PROCESSING STEPS

 Wafer Preparation
 Oxidation

 Photolithography

 Deposition (create thin films)

 Evaporating/ Sputtering
 Chemical Vapor Deposition (CVD)
 Epitaxy

 Doping (create diffusion layer)

 Diffusion
 Ion Implantation

 Etching 5
NMOS & PMOS FABRICATION

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NMOS & PMOS FABRICATION

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SUMMARY OF TERMINOLOGY

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CONTENT

1 Semiconductor Fabrication

2 Layout & Design Rule

3 Stick Diagram

4 Euler path

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LAYOUT

 IC layout (IC mask layout) is the representation of

an integrated circuit in terms of planar geometric
shapes called photomasks (a.k.a masks)

 Each mask defines a specific photolithographic step

in the semiconductor fabrication process

 Minimum dimensions of masks determine transistor

size (and hence speed, cost, and power)

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FABRICATION MASK OF INVERTER
A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

well
substrate tap
tap

contact

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap 11
FABRICATION MASK OF INVERTER

 Six masks
n well

 n-well
 Polysilicon
 n+ diffusion Polysilicon

 p+ diffusion
 Contact n+ Diffusion

 Metal
p+ Diffusion

Contact

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Metal
N-WELL PROCESS
 MOS Layers in an n-well process

 Top view of FET pattern

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GENERAL LAYOUT GEOMETRY

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DESIGNING
MOS ARRAYS

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PARALLEL CONNECTED MOS PATTERNING

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ALTERNATE LAYOUT STRATEGY

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THE CMOS INV GATE

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ALTERNATE LAYOUT OF INV GATE

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NAND2 LAYOUT

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NOR2 LAYOUT

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HOW TO CHOOSE ???

NOR2
Schematic

NOR2 layout

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DESIGN RULE

• Design rules
change from fab to
fab

• Fab examples: IBM,

Intel, TI, TSMC,
UMC, MOSIS

• Design rules
change according
to the process
technology

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LAMBDA RULES

o Feature Size: minimum distance between source and

drain of transistor (a.k.a minimum length L of the
transistor)

o Feature size = 2λ (@ 90nm feature size λ=45)

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DESIGN RULES
AND GATE LAYOUT

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o Lambda rules are conservative
WELL SPACING
o Wells must surround transistors by 6 lambda
 Implies 12 lambda between opposite transistor flavors
 Leaves room for one wire track

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WIRING TRACKS

o A wiring track is the space

required for a wire
 4 lambda width, 4
lambda spacing from
neighbor = 8 lambda
pitch
o Transistors also consume
one wiring track 27
MORE AND MORE DESIGN
RULES

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INVERTERS WITH TAPS

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LAYOUT OF
A 3-INPUT NAND GATE

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GATE AREA ESTIMATION

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CONTENT

1 Semiconductor Fabrication

2 Layout & Design Rule

3 Stick Diagram

4 Euler path

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STICK DIAGRAMS

o Stick diagrams help plan layout quickly

 Need not be to scale 33
STICK DIAGRAMS (CONT.)
 Designing complete layout in terms of rectangles
can be overwhelming.
 Stick diagram: abstraction between transistor
schematic and layout
 Cartoon of a chip layout
 Replace rectangles by lines

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STICK DIAGRAMS (CONT.)

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EXAMPLE

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CONTENT

1 Semiconductor Fabrication

2 Layout & Design Rule

3 Stick Diagram

4 Euler path

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GRAPH THEORY
 A path in a graph is a series of connected edges
 An Euler path (Euler trail) is a path through a graph
that contains every edge exactly once
 Not all graphs have Euler paths

 Graph has Euler path if either all vertices have even

degree or exactly two vertices have odd degree

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GENERAL FORMAT
 Get good
layout if n- and
p-diffusion are
one unbroken
line whenever
possible
 Aim for this
format:

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EXAMPLE OF NAND2

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EULER PATH  LAYOUT ???
 To lay out a gate with unbroken diffusion, find Euler
paths through the n- and p-networks in which the
edges appear in the same order
 That gives you the ordering on the inputs to the gate

 If you can’t find such an ordering, have to break up

one or both the diffusion lines
 Break the graphs into pieces, find Euler paths on the
pieces
 In some cases, may have to stack the diffusion lines
vertically
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EXAMPLE WITH ONE EULER PATH

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GATE THAT REQUIRES
MULTIPLE PATHS

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USING INPUTS MULTIPLE TIMES MAY
REQUIRE STACKED DIFFUSION

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XOR GATE -- BROKEN AND STACKED
LINES

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