-:Asynchronous Counter: -  

➢ Aim 
To design Asynchronous UP-DOWN counter(4-bit) using J-K flip-flops. 

➢ Apparatus Required 
Digital Trainer Kit(ST-2611), Bread Board, IC-74293, Connecting Wires, LED’s, Resistors(330 
ohm) 

➢ Theory 
 
Asynchronous counters are those whose output is free from the clock signal. Because 
the flip- flops in asynchronous counters are supplied with very less. So they are simple in 
design. Another name for asynchronous counters is “ripple counters”. 
 
The number of flip-flops used in a ripple counter is depends up on the number of states 
different clock signals, there may be a delay in producing output. 
 
The required number of logic gates to design asynchronous counters is of counter (ex: 
mod 4, mod 2 etc). The number of output states of counter is called “modulus” or “mod” 
of the counter. The maximum number of states that a counter can have is 2n where n 
Represents the number of flip -flops used in counter. 
 
For example, if we have 2 flip-flops, the maximum number of outputs of the counter is 4 
i.e. 22. So it is called as “mod-4 counter” or “modulus 4 counter”. 
 
 
Different types of Asynchronous Counters 
 
There are many types of Asynchronous counters available in digital electronics. They are 
● 4- bit synchronous UP counter 
● 4 bit synchronous DOWN counter 
● 4 bit synchronous UP / DOWN counter 
 
Review of Flip-Flops 
 
Flip-flops are synchronous bistable devices. The term synchronous means the output 
changes state only when the clock input is triggered. That is, changes in the output 
occur in synchronization with the clock. 

Positive edge-triggered (without bubble at Clock input): 

S-R, J-K, and D 

Negative edge-triggered (with bubble at Clock input): 

S-R, J-K, and D. 

An edge-triggered flip-flop changes states either at the positive edge (rising edge) or 
at the negative edge (falling edge) of the clock pulse on the control input. The three 
basic types are introduced here: S-R, J-K and D. 

The S-R, J-K and D inputs are called synchronous inputs because data on these inputs 
are transferred to the flip-flop's output only on the triggering edge of the clock pulse. 
On the other hand, the direct set (SET) and clear (CLR) inputs are called asynchronous 
inputs, as they are inputs that affect the state of the flip-flop independent of the clock. 
For the synchronous operations to work properly, these asynchronous inputs must 
both be kept LOW. 

 
 Edge-triggered J-K flip-flop 
The J-K flip-flop works very similar to S-R flip-flop. The only difference is that this 
flip-flop has NO invalid state. The outputs toggle (change to the opposite state) when 
both J and K inputs are HIGH. 

Asynchronous Counters 
An asynchronous counter is one in which the flip-flop within the counter do not change 
states at exactly the same time because they do not have a common clock pulse. 

● 2 Bit asynchronous binary counter 

● 3 Bit asynchronous binary counter 
● 4 Bit asynchronous binary counter 

The main characteristic of an asynchronous counter is each flip-flop derives its own 
clock from other flip-flops and is therefore independent of the input clock. 
Consequently, the output of each flip-flop may change at different time, hence the 
term asynchronous. From the asynchronous counter diagram above, we observed that 
the output of the first flip-flop becomes the clock input for the second flip-flop, and the 
output of the second flip-flop becomes the clock input for the third flip-flop etc. 

For the first flip-flop, the output changes whenever there is a negative transition in the 
clock input. This means that the output of the first flip flop produces a series of square 
waves that is half the frequency of the clock input. Since the output of the first flip-flop 
becomes the clock of the second flip-flop, the output of the second flip-flop is half the 
frequency of its clock, i.e. the output of the first flip-flop that in turn is half the 
frequency of the clock input. This behaviour, in essence is captured by the binary bit 
pattern in the counting sequence. 

4 Bit Asynchronous Binary Counter 

The following is a 4-bit asynchronous binary counter and its timing diagram for one 
cycle. It works exactly the same way as a 2-bit or 3 bit asynchronous binary counter 
mentioned above, except it has 16 states due to the fourth flip-flop. 
  

Fig: Four-bit asynchronous binary counter, timing diagram [Floyd] 

Asynchronous Up-Down Counters 

In certain applications a counter must be able to count both up and down. The 
circuit below is a 4-bit up-down counter. It counts up or down depending on the status 
 of the control signals UP and DOWN. When the UP input is at 1 and the DOWN input is 
at 0, the NAND network between FF0 and FF1 will gate the non-inverted output (Q) of 
FF0 into the clock input of FF1. Similarly, Q of FF1 will be gated through the other 
NAND network into the clock input of FF2. Thus the counter will count up. 

Fig: 4-bit up-down counter 

● When the control input UP is at 0 and DOWN is at 1, the inverted outputs of FF0 and 
FF1 are gated into the clock inputs of FF1 and FF2 respectively. If the flip-flops are 
initially reset to 0's, then the counter will go through the following sequence as input 
pulses are applied. 

● Notice that an asynchronous up-down counter is slower than an up counter or a down 

counter because of the additional propagation delay introduced by the NAND 
networks. 

 
➢ Advantages 
● Asynchronous counters can be easily designed by J-K flip-flop or D flip-flop. 
● These are also called as Ripple counters, and are used in low speed circuits. 
● They are used as Divide by- n counters, which divide the input by n, where n is an 
integer. 
● Asynchronous counters are also used as Truncated counters. These can be used to 
design any mod number counters, i.e. even Mod (ex: mod 4) or odd Mod (ex: mod3). 
 
➢ Disadvantages 
● Sometimes extra flip-flop may be required for “Resynchronization”. 
● To count the sequence of truncated counters (mod is not equal to 2n), we need 
additional feedback logic. 
● While counting large number of bits, the propagation delay of asynchronous  
counters is very large. 
● For high clock frequencies, counting errors may occur, due to propagation delay. 
 
 
➢ Applications of Asynchronous Counters 
● Asynchronous counters are used as frequency dividers, as divide by N counters. 
● These are used for low power applications and low noise emission. 
● These are used in designing asynchronous decade counter. 
● Also used in Ring counter and Johnson counter. 
● Asynchronous counters are used in Mod N ripple counters. EX: Mod 3, Mod 4,Mod  
8,Mod 14, Mod 10 etc.