Taif University

Al-Haweiyah Campus, Al-Taif

Taif University Makkah Province
College of Computers & Information Technology Kingdom of Saudi Arabia
Phone: +966 2 7272020
Computer Engineering Department Fax: +966 2 727 4299
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Digital Logic Design

503220-3
Week 5
Chapter 3
 Boolean Algebra and Logic Gates
Introduction

Gate-level minimization is the design task of finding an optimal gate-level implementation of the
Boolean functions describing a digital circuit. This task is well understood, but is difficult to
execute by manual methods when the logic has more than a few inputs. Fortunately, computer-
based logic synthesis tools can minimize a large set of Boolean equations efficiently and quickly.
Nevertheless, it is important that a designer understand the underlying mathematical description
and solution of the problem. In this chapter will introduce:

 Simplification of Expressions
 Logic Circuit Analysis
 Karnaugh maps
 Mapping a Nonstandard SOP Expression
 Group the 1s in the K maps:
 SOP Expression Minimization
 Mapping Directly from a Truth Table
 Don’t Care Cases
 Design Logic Circuits
 Logic Gates
 Exclusive OR Gate
 Exclusive NOR Gate
 NAND Gate
 Build using NAND gates
 Construction of SOP Expression
 Analysis of NAND Circuits
 NOR Gate
 Build using NOR gate
 Pulsed Waveforms
  Simplification of Expressions

Example 1:
Simplify the following:

𝐴’𝐵𝐶 + 𝐴𝐵𝐶’ + 𝐴𝐵𝐶

= 𝐴’𝐵𝐶 + 𝐴𝐵𝐶’ + 𝐴𝐵𝐶 + 𝐴𝐵𝐶 (Use A = A + A)

= 𝐵𝐶(𝐴’ + 𝐴) + 𝐴𝐵(𝐶’ + 𝐶) (Reverse distribute)

= 𝐵𝐶 + 𝐴𝐵 (Inverse A + A’ = 1)

= 𝐴𝐵 + 𝐵𝐶 (Commutate)

Example 2:
Simplify the following:

𝐴’𝐵𝐶 + 𝐴𝐵’𝐶’ + 𝐴’𝐵’𝐶’ + 𝐴𝐵’𝐶 + 𝐴𝐵𝐶

= 𝐵𝐶(𝐴’ + 𝐴) + 𝐴𝐵’(𝐶’ + 𝐶) + 𝐴’𝐵’𝐶’ (Reverse distribute)

= 𝐵𝐶 + 𝐴𝐵’ + 𝐴’𝐵’𝐶’ (Inverse A + A’ = 1)

= 𝐵𝐶 + 𝐵’(𝐴 + 𝐴’𝐶’) (Reverse distribute)

= 𝐵𝐶 + 𝐵’(𝐴 + 𝐶’) (Use A +A’B = A + B)

= 𝐵𝐶 + 𝐵’𝐴 + 𝐵’𝐶’ (Distribute)

= 𝐴𝐵’ + 𝐵’𝐶’ + 𝐵𝐶 (Commutate)

Logic Circuit Analysis

 When a logic circuit is given, we can analyze the circuit to obtain the logical expression

Example 3:
What is the Boolean expression for 𝐹 ?

𝐹 = ̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅
𝐴̅ ∙ 𝐵̅ + 𝐶 = (𝐴 ̅ ∙ 𝐵̅) ∙ 𝐶̅ = (𝐴 + 𝐵) ∙ 𝐶̅ = 𝐴𝐶̅ + 𝐵𝐶̅

 Steps of logic circuits analysis:

- Label all the outputs of the gates (modules) that are connected directly to the inputs
with (short) arbitrary names.
- Label all the outputs of the gates that are connected directly to the previous set.
- Repeat till all gates are done.
- Determine the expression for the output of each gate (module) that is connected
directly to the inputs in terms of the inputs.
- Determine the expression of the next set in terms of the expressions of the preceding
one.
- Do not simplify, unless it is clear plus, till you get to the final output(s)
 Example 4:
What is the Boolean expression for?

𝐹 = 𝑐′ + 𝑐𝑑 + 𝑎𝑐 + 𝑎𝑏𝑐

Simplify the expression of 𝐹

𝐹 = 𝑐′ + 𝑐𝑑 + 𝑎𝑐 + 𝑎𝑏𝑐

= 𝑐′ + 𝑑 + 𝑎𝑐(1 + 𝑏)

= 𝑐′ + 𝑑 + 𝑎𝑐

= 𝑐′ + 𝑎𝑐 + 𝑑

= 𝑐′ + 𝑎 + 𝑑

= 𝑎 + 𝑐′ + 𝑑
Karnaugh maps

 The Karnaugh map (K-map) is a tool for simplifying combinational logic with 3 or 4
variables.
 For 3 variables, 8 cells are required (23).
 The map shown is for three variables labeled A, B, and C although other letters could
be used.

 Each cell represents one term.

 Each cell differs from an adjacent cell by only one variable.
 For 4 variables, 16 cells are required (24).
 Each cell represent specific relation

𝐴𝐵
00 01 11 10

00
01
𝐶𝐷

11
10

 Cells are usually labeled using 0’s and 1’s to represent the variable and its complement.
 The numbers are entered in gray code, to force adjacent cells to be different by only
one variable.

 Alternatively, cells can be labeled with the variable letters. This makes it simple to
read, but it takes more time preparing the map.
 Example 5:
Read the terms for the yellow cells.

𝐶̅ 𝐶

𝐴̅ 𝐵̅

𝐴̅ 𝐵

𝐴𝐵

𝐴 𝐵̅

Solution
The cells are 𝐴̅𝐵𝐶̅ and 𝐴𝐵̅ 𝐶.

 K-maps can simplify combinational logic by grouping cells and eliminating variables
that change.

Example 6:
𝐶
Group the 1’s on the map and read the minimum logic. 0 1

Solution 00 1

01 1 1
𝐴𝐵

11
10
1. Group the 1’s into two overlapping
groups as indicated.
2. Read each group by eliminating any
variable that changes across a
boundary.
3. The vertical group is read 𝐴̅𝐶̅ .
4. The horizontal group is read 𝐴̅𝐵 .
 Example 7:
Group the 1’s on the map and read the minimum logic.

𝐶𝐷

00 01 11 10
1 1
00

𝐴𝐵
1 1
01
1 1
11
1 1
10

Solution
1. Group the 1’s into two overlapping groups as indicated.
2. Read each group by eliminating any variable that changes across a boundary.
3. The upper (yellow) group is read as 𝐴̅𝐷
̅.
4. The lower (green) group is read as 𝐴𝐷.
C changes across outer boundary

𝐶𝐷

00 01 11 10
B changes 1 1
00
𝐴𝐵

1 1
01
1 1
11
B changes 1 1
10
C changes
𝑋 = 𝐴̅𝐷
̅ + 𝐴𝐷
 Example 8:
Map the following standard SOP expression on a Karnaugh map:

𝐴′𝐵′𝐶 + 𝐴′𝐵𝐶′ + 𝐴𝐵𝐶′ + 𝐴𝐵𝐶

Solution:
For each standard product term in the expression, place a 1 on the 3-variable Karnaugh map as
shown.

𝐶
0 1

00 1 𝐴′𝐵′𝐶

01 1 𝐴′𝐵𝐶′
𝐴𝐵

1 𝐴𝐵𝐶
11 1

10 𝐴𝐵𝐶′

Example 9:
Map the following standard SOP expression on a K map:

𝐴′𝐵′𝐶𝐷 + 𝐴′𝐵𝐶′𝐷′ + 𝐴𝐵𝐶′𝐷 + 𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶′𝐷′ + 𝐴′𝐵′𝐶′𝐷 + 𝐴𝐵′𝐶𝐷′

Solution:
𝐴′𝐵′𝐶𝐷 𝐴′𝐵𝐶′𝐷′ 𝐴𝐵𝐶′𝐷 𝐴𝐵𝐶𝐷 𝐴𝐵𝐶′𝐷′ 𝐴′𝐵′𝐶′𝐷 𝐴𝐵′𝐶𝐷′
𝟎𝟎𝟏𝟏 𝟎𝟏𝟎𝟎 𝟏𝟏𝟎𝟏 𝟏𝟏𝟏𝟏 𝟏𝟏𝟎𝟎 𝟎𝟎𝟎𝟏 𝟏𝟎𝟏𝟎
𝐴′𝐵′𝐶′𝐷

𝐶𝐷

00 01 11 10 𝐴′𝐵′𝐶𝐷
′ ′ ′
𝐴 𝐵𝐶 𝐷 1 1
00
𝐴𝐵𝐶 ′ 𝐷
𝐴𝐵

1
01
𝐴𝐵𝐶′𝐷′ 𝐴𝐵𝐶𝐷
1 1 1
11
1 𝐴𝐵′𝐶𝐷′
10
Mapping a Nonstandard SOP Expression

In a 4 variable domain that depends on A, B, C, and D, if we have a product term: BC in the SOP
expression, then BC represents -BC-.

Example 10:
Express the −𝐵𝐶 −

0110 𝐴′𝐵𝐶𝐷′

0111 𝐴′𝐵𝐶𝐷

1110 𝐴𝐵𝐶𝐷′

1111 𝐴𝐵𝐶𝐷

Example 11:
Map the following SOP expression on a K map:

𝐴′ + 𝐴𝐵′ + 𝐴𝐵𝐶′

Solution:
𝐴′ is: 𝐴′ − −, such 000, 001, 010, and 011

𝐴𝐵′ is 𝐴𝐵′ −, such 100, and 101

𝐴𝐵𝐶′ is 110

Thus the map is:

𝐶
0 1

00 1 1

01 1 1
𝐴𝐵

11 1

10 1 1
 Example 12:
Map the following SOP expression on a Karnaugh map:

𝐵’𝐶’ + 𝐴𝐵’ + 𝐴𝐵𝐶’ + 𝐴𝐵’𝐶𝐷’ + 𝐴’𝐵’𝐶’𝐷 + 𝐴𝐵’𝐶𝐷

Solution:
𝐵’𝐶’ 𝐴𝐵’ 𝐴𝐵𝐶’ 𝐴𝐵’𝐶𝐷’ 𝐴’𝐵’𝐶’𝐷 𝐴𝐵’𝐶𝐷
0000 1000 1100 1010 0001 1011
0001 1001 1101
1000 1010
1001 1011

The resulting map:

𝐶𝐷

00 01 11 10
1 1
00
𝐴𝐵

01
1 1
11
1 1 1 1
10
Group the 1s in the K maps:

 Rules For Grouping

o A group must contain either 1, 2, 4, 8, or 16 cells, which are all powers of two.
 In the case of a 3-variable map, 23 = 8 cells is the maximum group.
o Each cell in a group must be adjacent to one or more cells in that group.
o Always include the largest possible number of 1s in a group.
o Each 1 on the map must be included in at least one group. The 1s already in a
group can be included in another group as long as the overlapping groups
include non-common 1s.

Examples of grouping:

𝐶 𝐶
0 1 0 1

00 1 00 1

01 1 01 1
𝐴𝐵

𝐴𝐵

11 1 1 11 1 1

10 10
(a)

𝐶 𝐶
0 1 0 1

00 1 1 00
1 1

01 1 01 1
Wrap around adjacent
𝐴𝐵

𝐴𝐵

11 1 11 1

10 1 1 10 1 1
(b)
 𝐶𝐷 𝐶𝐷

00 01 11 10 00 01 11 10
1
1 1 1
00 00
𝐴𝐵

𝐴𝐵
1 1 1 1 1 1 1 1
01 01

11 11
1 1 1 1
10 10
(c)

𝐶𝐷 𝐶𝐷

00 01 11 10 00 01 11 10
1 1
1 1
00 00
1
𝐴𝐵

𝐴𝐵
1 1 1 1 1
01 01
1 1 1 1 1 1
11 11
1 1 1 1
1 1
10 10
(d)
SOP Expression Minimization

 The simplest SOP expression is an expression that has:

o A minimum number of ‘products’
o A minimum number of literal in each ‘product’.
 This can be achieved in a K-map by:
o Grouping the largest possible number of 1s in one merger (i.e. prime implicant
(PI))
o Selecting a minimum number of PIs (mergers) that cover all the 1s.

Example 13:

Create the max mergers and determine the product terms for the Karnaugh map in the following
Figure and write the resulting minimum SOP expression.

𝐶𝐷 𝐶𝐷

00 01 11 10 00 01 11 10
1 1 1 1
00 00
1
𝐴𝐵

𝐴𝐵

1 1 1 1 1 1 1
01 01
1 1 1 1 1 1 1 1
11 11
1 1
10 10

The Corresponding PIs are: 𝐵, 𝐴′𝐶 𝑎𝑛𝑑 𝐶𝐷

The Minimum Sum of Products Expression is: 𝐵 + 𝐴′𝐶 + 𝐶𝐷

 Example 14:
Determine the product terms for the Karnaugh map in the following Figure and write the resulting
minimum SOP expression.

𝐶 𝐶
0 1 0 1

00 1 00 1

01 1 01 1
𝐴𝐵

𝐴𝐵
11 1 1 11 1 1

10 10

The PIs are: 𝐴𝐵, 𝐵𝐶 𝑎𝑛𝑑 𝐴′𝐵′𝐶′

The Minimum Sum of Products Expression is: 𝐴𝐵 + 𝐵𝐶 + 𝐴′𝐵′𝐶′

Example 15:
Determine the product terms for the Karnaugh map in the following Figure and write the resulting
minimum SOP expression.

𝐶𝐷 𝐶𝐷

00 01 11 10 00 01 11 10
1 1
1 1
00 00
1
𝐴𝐵

𝐴𝐵

1 1 1 1 1
01 01
1 1 1 1 1 1
11 11
1 1 1 1 1 1
10 10

The PIs are: 𝐷′ , 𝐵𝐶 ′ 𝑎𝑛𝑑 𝐴𝐵′𝐶

The Minimum Sum of Products Expression is: 𝐷′ + 𝐵𝐶 ′ + 𝐴𝐵′𝐶

 Example 15:
Determine the product terms for the Karnaugh map in the following Figure and write the resulting
minimum SOP expression.

𝐶𝐷 𝐶𝐷

00 01 11 10 00 01 11 10
1 1 1
1
00 00
1
𝐴𝐵

𝐴𝐵
1 1 1
01 01
1 1 1 1 1 1
11 11
1 1
10 10

The PIs are: 𝐴′𝐷′ , 𝐵𝐷, 𝐴𝐵𝐶 ′ 𝑎𝑛𝑑 𝐴𝐶′𝐷

The Minimum Sum of Products Expression is: 𝐴′𝐷′ + 𝐵𝐷 + 𝐴𝐵𝐶 ′ + 𝐴𝐶′𝐷

Example 16:
Determine the minimum SOP expression for F:

𝐹𝐴,𝐵,𝐶,𝐷 = ∑(2, 3, 4, 6, 7,11, 15)

𝐶𝐷

00 01 11 10
1 1
00
1 1
𝐴𝐵

1
01
1
11
1
10
The PIs are: 𝐴′ 𝐶, 𝐶𝐷 𝑎𝑛𝑑 𝐴𝐵𝐷′

The Minimum Sum of Products Expression is: 𝐹 = 𝐴′𝐶 + 𝐶𝐷 + 𝐴′𝐵𝐷′

Mapping Directly from a Truth Table

Example 17:
Express the truth table on the K-map

𝑖𝑛𝑝𝑢𝑡 𝑜𝑢𝑡𝑝𝑢𝑡

𝐴 𝐵 𝐶 𝐹

0 0 0 1
𝐶
0 0 1 0 0 1

0 1 0 0 00 1
01 1
0 1 1 1

𝐴𝐵
11 1 1
1 0 0 0
10
1 0 1 0

1 1 0 1

1 1 1 1
Don’t Care Cases

 Use don’t care cases to your advantage, such as:

o Set to one when it generates a better merger.

Example 18:

𝐹𝐴,𝐵,𝐶,𝐷 = ∑(2, 3, 4, 6, 7,11, 15)

and don’t care for ∑(0, 1, 5, 8,12, 14)

𝐶𝐷

00 01 11 10
d 1
d 1
00
𝐴𝐵

1 d 1 1
01
d 1 d
11
d 1
10

𝐹 = 𝐴 ′ + 𝐶𝐷
 Example 19:
Determine the minimum SOP expressions for the BCD to 7-Segment Generator from:

ABCD 7 segment
Decimal 𝐴 𝐵 𝐶 𝐷 𝑎 𝑏 𝑐 𝑑 𝑒 𝑓 𝑔
𝟎 0 0 0 0 1 1 1 0 1 1 1
𝟏 0 0 0 1 0 1 0 0 0 1 0
𝟐 0 0 1 0 1 1 0 1 1 0 1
𝟑 0 0 1 1 1 1 0 1 0 1 1
𝟒 0 1 0 0 0 1 1 1 0 1 0
𝟓 0 1 0 1 1 0 1 1 0 1 1
𝟔 0 1 1 0 1 0 1 1 1 1 1
𝟕 0 1 1 1 1 1 0 0 0 1 0
𝟖 1 0 0 0 1 1 1 1 1 1 1
𝟗 1 0 0 1 1 1 1 1 0 1 1
1 0 1 0 X X X X X X X
1 0 1 1 X X X X X X X
1 1 0 0 X X X X X X X
None

1 1 0 1 X X X X X X X
1 1 1 0 X X X X X X X
1 1 1 1 X X X X X X X
To generate the minimum SOP expressions for 𝑎:

ABCD 7
segment
Decimal 𝐴 𝐵 𝐶 𝐷 𝑎
𝟎 0 0 0 0 1
𝟏 0 0 0 1 0 𝐶𝐷
𝟐 0 0 1 0 1
𝟑 0 0 1 1 1 00 01 11 10
𝟒 0 1 0 0 0 1
1 1
𝟓 0 1 0 1 1 00
1
𝟔 0 1 1 0 0
𝐴𝐵

1
01
𝟕 0 1 1 1 1 X
𝟖 1 0 0 0 1 X X X
11
𝟗 1 0 0 1 1 X
1 1 X
1 0 1 0 X 10
1 0 1 1 X
1 1 0 0 X
None

1 1 0 1 X 𝑎 = 𝐴 + 𝐵𝐷 + 𝐶𝐷 + 𝐵′𝐷′
1 1 1 0 X
1 1 1 1 X
To generate the minimum SOP expressions for 𝑒:

ABCD 7
segment
Decimal 𝐴 𝐵 𝐶 𝐷 𝑒
𝟎 0 0 0 0 1
𝟏 0 0 0 1 0 𝐶𝐷
𝟐 0 0 1 0 1
𝟑 0 0 1 1 0 00 01 11 10
𝟒 0 1 0 0 0 1
1
𝟓 0 1 0 1 0 00
𝟔 0 1 1 0 1

𝐴𝐵
1
01
𝟕 0 1 1 1 0
𝟖 1 0 0 0 1 X X X X
11
𝟗 1 0 0 1 0 X
1 X
1 0 1 0 X 10
1 0 1 1 X
1 1 0 0 X
None

1 1 0 1 X 𝑎 = 𝐶𝐷 + 𝐵′𝐷′
1 1 1 0 X
1 1 1 1 X
Home work

Q1.Simplify the following Boolean functions, using three-variable maps:

(a) 𝐹(𝑥,𝑦,𝑧) = ∑(0, 2, 4, 5)
(b) 𝐹(𝑥,𝑦,𝑧) = ∑(0, 2, 4, 5, 6)
(c) 𝐹(𝑥,𝑦,𝑧) = ∑(0, 1, 2, 3, 5)
(d) 𝐹(𝑥,𝑦,𝑧) = ∑(1, 2, 3, 7)

Q2.Simplify the following Boolean functions, using Karnaugh maps:

(a) 𝐹 (𝑥, 𝑦, 𝑧) = ∑(2, 3, 6, 7)
(b) 𝐹 (𝐴, 𝐵, 𝐶, 𝐷) = ∑(4, 6, 7, 15)
(c) 𝐹 (𝐴, 𝐵, 𝐶, 𝐷) = ∑(3, 7, 11, 13, 14, 15)
(d) 𝐹 (𝑤, 𝑥, 𝑦, 𝑧) = ∑(2, 3, 12, 13, 14, 15)
(e) 𝐹 (𝑤, 𝑥, 𝑦, 𝑧) = ∑(11, 12, 13, 14, 15)
(f) 𝐹 (𝑤, 𝑥, 𝑦, 𝑧) = ∑(8, 10, 12, 13, 14)

Q3.Simplify the following Boolean function 𝐹 , together with the don’t-care conditions 𝑑,
and then express the simplified function in sum-of-minterms form:
(a) 𝐹(𝑥,𝑦,𝑧) = ∑(0, 1, 4, 5, 6) & 𝑑(𝑥,𝑦,𝑧) = ∑(2, 3, 7)
(b) 𝐹(A,B,C,D) = ∑(0, 6, 8, 13, 14) & 𝑑(A,B,C,D) = ∑(2, 4, 10)
(c) 𝐹(A,B,C,D) = ∑(5, 6, 7, 12, 14, 15) & 𝑑(A,B,C,D) = ∑(3, 9, 11)
(d) 𝐹(A,B,C,D) = ∑(4, 12, 7, 2, 10) & 𝑑(A,B,C,D) = ∑(0, 6, 8)
Week 6
Design Logic Circuits

 Boolean expression can be implemented using logic gates

Example 19:
Implement the functions F1 and F2 as logic gates

- 𝐹1 = 𝑥 + 𝑦′𝑧
- 𝐹2 = 𝑥𝑦′ + 𝑥′𝑦

Solution
- 𝐹1 = 𝑥 + 𝑦′𝑧

- 𝐹2 = 𝑥𝑦′ + 𝑥′𝑦

 Implement the expression as given using the available gates, otherwise:

o From the specifications of the circuit, determine the required number of inputs
and outputs and assign a symbol to each.
o Derive the truth table that defines the required relationship between inputs and
outputs.
o Obtain the simplified Boolean functions for each output as a function of the
input variables.
 o Draw the logic diagram and verify the correctness of the design (manually or
by simulation).

Example 20:
Design a code convertor to convert BCD to Excess 3

Input BCD Output Excess-3 Code

𝑨 𝐵 𝐶 𝐷 𝑊 𝑋 𝑌 𝑍
𝟎 0 0 0 0 0 1 1
𝟎 0 0 1 0 1 0 0
𝟎 0 1 0 0 1 0 1
𝟎 0 1 1 0 1 1 0
𝟎 1 0 0 0 1 1 1
𝟎 1 0 1 1 0 0 0
𝟎 1 1 0 1 0 0 1
𝟎 1 1 1 1 0 1 0
𝟏 0 0 0 1 0 1 1
𝟏 0 0 1 1 1 0 0

The remaining Input Combinations generate don’t care cases as they don’t exist!

𝐶𝐷

00 01 11 10

00 𝑊 = 𝐴 + 𝐵𝐶 + 𝐵𝐷
1 1
𝐴𝐵

1
01
d d d d
11
1 1 d d
10

𝐶𝐷

00 01 11 10
1 1 1
00 𝑋 = 𝐵′𝐷 + 𝐵′𝐶 + 𝐵𝐶′𝐷′
1
𝐴𝐵

01
d d d d
11
1 d d
10
 𝐶𝐷

00 01 11 10
1 1
00 𝑋 = 𝐶𝐷 + 𝐶′𝐷′
𝐴𝐵 01
1 1

d d d d
11
1 d d
10

𝐶𝐷

00 01 11 10
1 1
00 𝑋 = 𝐷′
𝐴𝐵

1 1
01
d d d d
11
1 d d
10
Logic Gates

 Gates AND/OR/NOT are enough to build any Boolean function

 Other gates are used because:
o Very useful (no choice),
 For example: XOR for parity bit
o Save transistors number
o Self-sufficient (can build any gate from it) NAND/NOR: save, self sufficient
Exclusive OR Gate

𝑨 𝑩 𝑭
𝟎 0 0
𝟎 1 1
𝟏 0 1
𝟏 1 0

 XOR gate is defined by the relation: 𝐹 = (𝐴 ⊕ 𝐵) and/or by the shown truth table.
 𝐹 can be rewritten as: 𝐹 = 𝐴′𝐵 + 𝐴𝐵′
 ⊕ is commutative, such as 𝑎 ⊕ 𝑏 = 𝑏 ⊕ 𝑎
 𝑎 ⊕ 0 = 𝑎, → 𝑎 ⊕ 1 = 𝑎′
 𝑎 ⊕ 𝑎 = 0, → 𝑎 ⊕ 𝑎′ = 1
 ⊕ is associative, such as 𝑎 ⊕ (𝑏 ⊕ 𝑐) = (𝑎 ⊕ 𝑏) ⊕ 𝑐 = 𝑎 ⊕ 𝑏 ⊕ 𝑐

𝐹 = (𝑎 ⊕ 𝑏)⨁𝑐

𝐺 = 𝑎⨁(𝑏⨁𝑐)

𝐹 = (𝑎 ⊕ 𝑏) ⊕ 𝑐 𝐺 = 𝑎⨁(𝑏⨁𝑐)
= (𝑎′ 𝑏 + 𝑎𝑏 ′ ) ⊕ 𝑐 = 𝑎 ⊕ (𝑏 ′ 𝑐 + 𝑏𝑐 ′ )
= (𝑎′ 𝑏 + 𝑎𝑏 ′ )′ 𝑐 + (𝑎′ 𝑏 + 𝑎𝑏 ′ )𝑐 ′ = 𝑎(𝑏 ′ 𝑐 + 𝑏𝑐 ′ )′ + 𝑎′(𝑏 ′ 𝑐 + 𝑏𝑐 ′ )
= (𝑎′ 𝑏)′ (𝑎𝑏 ′ )′ 𝑐 + (𝑎′ 𝑏 + 𝑎𝑏 ′ )𝑐 ′ = 𝑎(𝑏 ′ 𝑐)′ (𝑏𝑐 ′ )′ + 𝑎′(𝑏 ′ 𝑐 + 𝑏𝑐 ′ )
= (𝑎 + 𝑏 ′ )(𝑎′ + 𝑏)𝑐 + (𝑎′ 𝑏 + 𝑎𝑏 ′ )𝑐 ′ = 𝑎(𝑏 + 𝑐 ′ )(𝑏 ′ + 𝑐) + 𝑎′(𝑏 ′ 𝑐 + 𝑏𝑐 ′ )
= 𝑎𝑏𝑐 + 𝑎′𝑏′𝑐 + 𝑎′𝑏𝑐′ + 𝑎𝑏′𝑐′ = 𝑎𝑏𝑐 + 𝑎′𝑏′𝑐 + 𝑎′𝑏𝑐′ + 𝑎𝑏′𝑐′

Note: Odd Number of inputs are one!!!

Exclusive NOR Gate

 Inverse of Exclusive OR (Equivalence)

𝐹 = (𝑎 ⊕ 𝑏⨁𝑐)′

𝐹 = (𝑎 ⊕ 𝑏 ⊕ 𝑐)′
= (𝑎′ 𝑏 ′ 𝑐 + 𝑎′ 𝑏𝑐 ′ + 𝑎𝑏 ′ 𝑐 ′ + 𝑎𝑏𝑐)′
= (𝑎′ 𝑏 ′ 𝑐)′ (𝑎′ 𝑏𝑐 ′ )′ (𝑎𝑏 ′ 𝑐 ′ )′ (𝑎𝑏𝑐)′
= (𝑎 + 𝑏 + 𝑐 ′ )(𝑎 + 𝑏 ′ + 𝑐)(𝑎′ + 𝑏 + 𝑐)(𝑎′ + 𝑏 ′ + 𝑐 ′ )
= 𝑎𝑏𝑐′ + 𝑎𝑏′𝑐 + 𝑎′𝑏𝑐 + 𝑎′𝑏′𝑐′

Note: Even Number of inputs are one!!!

NAND Gate

a b F
0 0 1
0 1 1
1 0 1
1 1 0

 NAND gate is defined by the relation: 𝐹 = (𝐴𝐵)′ and/or by the shown truth table.
 𝐹 can be rewritten as: 𝐹 = 𝐴′ + 𝐵′ which leads to the equivalent symbol shown.

Extending from 2 to 3 inputs

 It is easy to extend the 2 input gates to 3 inputs if they are commutative and associative
 AND, OR, XOR, and XNOR are commutative and associative
 NAND is not associative!!!

𝐹 = (𝑥(𝑦𝑧)′)′ = 𝑥′ + 𝑦𝑧

𝐺 = ((𝑥𝑦)′𝑧)′ = 𝑥𝑦 + 𝑧′
 NAND gate is self-sufficient (it can build any circuit from it)
 Can be used for building AND/ OR/ NOT gates

Example 21:
Build NOT gate using NAND gate

Example 22:
Build AND gate using NAND gates:

Example 23:
Build OR gate using NAND gates:
Build using NAND gates

 It can be built Boolean circuits for any Boolean expression using NAND gates.
 Steps:
o Obtain sum-of-product Boolean expression
 For example: 𝐹 = 𝑥𝑦 + 𝑦𝑧
o Use DeMorgan theorem to get expression using two level NAND gate

Example 24:
- 𝐹 = 𝑥𝑦 + 𝑦𝑧

𝐹 = 𝑥𝑦 + 𝑦𝑧

= ̿̿̿̿̿̿̿̿̿̿
𝑥𝑦 + 𝑦𝑧

= ̅̅̅̅̅̅̅̅̅
̅̅̅ ⋅ ̅̅̅
𝑥𝑦 𝑦𝑧
Construction of SOP Expression

 Referring to previous example, any SOP can be implemented by a 2 level NAND

combinational Circuit.

Example 25:

̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅ ∙ (𝐶𝐷)
𝑋 = (𝐴𝐵) ̅̅̅̅̅̅̅

̿̿̿̿ + 𝐶𝐷
= 𝐴𝐵 ̿̿̿̿

= 𝐴𝐵 + 𝐶𝐷

 Note: The previous circuit in the example 25 is equivalent to:

And the bubbles (∘) cancel out

 Any Sum-of-product expression can be built using: Two level AND-OR gates.
 Two level NAND-NAND gates.
 Example 26:
Convert 𝐹 = 𝐴𝐵 + 𝐶𝐷 + 𝐸 from two level AND-OR gate two level NAND gate

Solution
- Replace each gate with its equivalent NAND gate(s)

- Now remove any two successive invertors.

Analysis of NAND Circuits

̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅
̅̅̅̅̅̅
𝑋 = ̅̅̅̅
𝐴𝐵 𝐶 𝐷̅̅̅̅
𝐸𝐹
̅̅̅̅̅̅̅̅
̅̅̅̅̅̅
̅̅̅̅ ̿̿̿̿
= 𝐴𝐵 𝐶 𝐷 + 𝐸𝐹
̅̅̅̅̅̅
= ̅̅̅̅
𝐴𝐵 𝐶 𝐷 + 𝐸𝐹
̿̿̿̿ + 𝐶̅ )𝐷 + 𝐸𝐹
= (𝐴𝐵

= (𝐴𝐵 + 𝐶̅ )𝐷 + 𝐸𝐹

Which can be redrawn as:

̅ )𝑫 + 𝑬𝑭
X= (𝑨𝑩 + 𝑪
 Starting from the output divide the circuit into levels, output gate(s) being at level 1.
 Gates whose outputs lead into level 𝑖 will be labelled as level 𝑖 + 1
 If a gate’s output is connected to the inputs of gates at multiple levels, duplicate it and
label each by its appropriate level.
 Replace gates at odd levels by ORs and those at even levels by ANDs
 Direct inputs to odd levels MUST be complemented.

Example 27:

𝐹 = 𝑎(𝑏′ + 𝑎𝑐) + 𝑑(𝑎′ + 𝑐′) = 𝑎𝑏′ + 𝑎𝑐 + 𝑎′𝑑 + 𝑐′𝑑

NOR Gate

 NOR gate is also self sufficient

 Can be used for building AND/OR/NOT gate

Example 28:
Build NOT gate using NOR gate

Example 29:
Build AND gate using NOR gates:

Example 30:
Build OR gate using NOR gates:
Build using NOR gate

 One can build Boolean circuits for any Boolean expression using NOR gates.
 Steps:
o Obtain product-of-sum Boolean expression
 For example: 𝐹 = (𝑥 + 𝑦). (𝑦 + 𝑧)
o Use De Morgan theorem to get expression using two level NOR gates

Example 31:
- 𝐹 = (𝑥 + 𝑦). (𝑦 + 𝑧)

𝐹 = (𝑥 + 𝑦) ∙ (𝑦 + 𝑧)

= ̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿
(𝑥 + 𝑦) ∙ (𝑦 + 𝑧)

= ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅
(𝑥 + 𝑦) + ̅̅̅̅̅̅̅̅̅̅
(𝑦 + 𝑧)
Pulsed Waveforms

Example 32:

Determine the final output waveform X for the circuit in the following Figure, with input
waveforms A, B, and C

𝑌 =𝐵+𝐶
𝑋 = ̅̅̅̅̅̅̅̅̅̅̅̅
𝐴(𝐵 + 𝐶)
= 𝐴̅ + ̅̅̅̅̅̅̅̅̅̅
(𝐵 + 𝐶)
 Example 33:
Determine the output waveform X for the logic circuit in the following Figure by first
finding the intermediate waveform at each of points Y1, Y2, Y3, and Y4. The input
waveforms are shown.

𝑌1 = 𝐴′ + 𝐵′
𝑌2 = 𝐶 ′
𝑌3 = ̅̅̅̅̅
𝐶𝑌1
𝑌4 = ̅̅̅̅̅
𝐷𝑌2
𝑋 = 𝑌3 + 𝑌̅4
̅
 Continue Example 33:
Determine the output waveform X for the circuit directly from the output expression.

𝑋 = 𝐶(𝐴′ + 𝐵′) + 𝐶′𝐷 = 𝐴′𝐶 + 𝐵′𝐶 + 𝐶′𝐷

Home work

Q1.Simplify the following functions, and implement them with two-level NAND gate
circuits:
(a) 𝐹(A,B,C,D) = 𝐴𝐶′𝐷′ + 𝐴′𝐶 + 𝐴𝐵𝐶 + 𝐴𝐵′𝐶 + 𝐴′𝐶′𝐷′
(b) 𝐹(A,B,C,D) = 𝐴′𝐵′𝐶′𝐷 + 𝐶𝐷 + 𝐴𝐶′𝐷
(c) 𝐹(A,B,C,D) = (𝐴′ + 𝐶′ + 𝐷′)(𝐴′ + 𝐶′)(𝐶′ + 𝐷′)
(d) 𝐹(A,B,C,D) = 𝐴′ + 𝐵 + 𝐷′ + 𝐵′𝐶

Q2.Simplify the following functions, and implement them with two-level NOR gate
circuits:
(a) 𝐹 = 𝑤𝑥 ′ + 𝑦 ′ 𝑧 ′ + 𝑤 ′ 𝑦𝑧 ′
(b) ) 𝐹(w,𝑥,𝑦,𝑧) = ∑(0, 3, 12, 15)
(c) 𝐹(𝑥,𝑦,𝑧) = [(x + y)(x + z)]′

Q3.Convert the logic diagram of the circuit shown in the Figure into a multiple-level
NAND circuit.

Q4.Implement the following Boolean function 𝐹, together with the don’t-care conditions
𝑑, using no more than two NOR gates:
𝐹(𝐴,𝐵,𝐶,𝐷) = ∑(2, 4, 10, 12, 14) & 𝑑(𝐴,𝐵,𝐶,𝐷) = ∑(0, 1, 5, 8)
Assume that both the normal and complement inputs are available.