PIC16F877 Memory Organisation and

Programming
Data RAM Organisation
The data RAM address space is partitioned into 4 banks of 128 bytes (known as file registers) each:
 Addresses 00 to 7F form bank 0
 Addresses 80 to FF form bank 1
 Addresses 100 to 17F form bank 2
 Addresses 180 to 1FF form bank 3

Figure 2.1 shows the organisation of data RAM in the PIC16F877.

File register addresses are 9 bits wide. Each file register can be accessed using direct or indirect addressing:
 In direct addressing, the instruction supplies a 7-bit address that corresponds to the 7 lowest address
bits. These 7 bits specify the address of the file register within a bank. The two MSBs are supplied by
separate bank selector bits, i.e., the bank selector bits select the bank in which the register is located.
 In indirect addressing, the memory pointer supplies an 8-bit address corresponding to the 8 lowest
address bits. The MSB is supplied by a separate bank selector bit. The bank selector bit and the MSB
of the memory pointer select the bank in which the register is located.

Special Function Registers (SFRs)

• The 32 lowest registers in banks 0 and 1 and the 16 lowest registers in banks 2 and 3 are SFRs. Address
ranges for SFRs are 00h – 1Fh, 80h – 9Fh, 100h – 10F and 180h – 18Fh.
• Some frequently used SFRs are mirrored in more than one bank. Some addresses in the SFR range are
reserved and should not be used by the programmer.
• SFRs are divided into core SFRs and peripheral SFRs. Core SFRs are SFRs that are associated with the
core function of the PIC. These are INDF, OPTION_REG, PCL, STATUS, FSR, PCLATH, INTCON, PIR1, PIE1,
PIR2 and PIE2.
• Peripheral SFRs are SFRs that are associated with particular peripherals. They will be named and
discussed under the coverage of the peripherals.

General Purpose Registers (GPRs)

 The higher addresses above SFRs in each bank are GPRs. Address ranges are 20h – 7Fh, A0H – FFh,
120h – 17Fh and 1A0h – 1FFh.
 The last 16 addresses in each bank (addresses 70h – 7Fh, F0h – FFh, 170H – 17Fh and 1F0h – 1FFh)
access the same memory block. This allows 16 file registers to be used as working space that is
accessible from any bank.

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Figure 2.1 RAM banks in the PIC16F877

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Core SFR Descriptions

STATUS register – addresses 03h, 83h, 103h, 183h

It contains the arithmetic status flags, the reset status bits and the bank select bits for data RAM.

IRP: Register Bank Select bit for indirect addressing

1 – selects banks 2 and 3 (100h-1FFh)
0 – selects banks 0 and 1 (00h-FFh)
RP1:RP0: Register Bank Select bits for direct addressing
11 – selects bank 3 (180h-1FFh)
10 – selects bank 2 (100h-17Fh)
01 – selects bank 1 (80h-FFh)
00 – selects bank 0 (00h-7Fh)
TO: Time-out bit
1 – indicates a power-up, a clear watchdog (CLRWDT) instruction or a SLEEP instruction occurred
0 – indicates a watchdog time-out occurred
PD: Power-down bit
1 – indicates a power-up or CLRWDT instruction occurred
0 – indicates a SLEEP instruction was executed
Z: Zero bit
1 – indicates the result of an arithmetic or logic operation is zero
0 – indicates the result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit – stores the carry or borrow out from lower nibble to higher nibble in arithmetic
operations. For borrow, the polarity is reversed.
C: Carry/borrow bit – stores the carry or borrow out (from the MSB of the byte) in arithmetic operations. For
borrow, the polarity is reversed. In rotate instructions, C is loaded with either the MSB or LSB of the
register that has been rotated.

The OPTION_REG register – addresses 81h and 181h

The OPTION_REG register contains bits for configuration of port B pull up resistances, configuration of
interrupts, configuration of Timer 0 operation, selection of assignment of the prescaler and selection of the
prescaler ratio.

RBPU: PORTB Pull-up Enable bit

1 – enables PORTB pull-up resistances
0 – disables PORTB pull-ups resistances
INTEDG: Interrupt Edge Select bit
1 – selects interrupt on rising edge of RB0/INT pin
0 – selects interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1 – selects counter source as transition on RA4/T0CKI pin
0 – selects counter source as internal instruction cycle clock (CLKO)

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T0SE: TMR0 Source Edge Select bit
1 – select timer register to increment on high-to-low transition on RA4/T0CKI pin
0 – selects timer register to increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1 – assigns prescaler to the watchdog timer (WDT)
0 – assigns prescaler to the Timer0 module
PS2:PS0: Prescaler Rate Select bits as shown in table

Prescale bits Timer 0 rate WDT rate

000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128

INTCON register (addresses 0Ah, 8Ah, 10Ah, 18Ah)

The INTCON register contains interrupt enable and flag bits for TMR0 register overflow, Port B port change
and external RB0/INT pin interrupts.

GIE: Global Interrupt Enable bit

1 – Enables all unmasked interrupts
0 – Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1 – Enables all unmasked peripheral interrupts
0 – Disables all peripheral interrupts
TMR0IE: Timer 0 Overflow Interrupt Enable bit
1 – Enables the Timer 0 interrupt
0 – Disables the Timer 0 interrupt
INTE: External interrupt (RB0/INT) Enable bit
1 – Enables the external interrupt
0 – Disables the external interrupt
RBIE: Port B Change Interrupt Enable bit
1 – Enables the Port B port change interrupt
0 – Disables the Port B port change interrupt
TMR0IF: Timer Overflow Interrupt Flag bit
1 – indicates Timer 0 register has overflowed
0 – indicates Timer MR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1 – indicates RB0/INT external interrupt occurred
0 – indicates RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1 – indicates at least one of the pins RB7:RB4 changed state. Reading PORTB ends the mismatch
condition
0 – indicates none of the pins RB7:RB4 pins have changed state

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The PIE1 Register (address 8Ch)
It contains the individual interrupt enable bits for the various peripheral interrupts. An interrupt enable bit is
set to enable the interrupt and cleared to disable the interrupt.

PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit

ADIE: A/D Converter Interrupt Enable bit
RCIE: USART Receive Interrupt Enable bit
TXIE: USART Transmit Interrupt Enable bit
SSPIE: Synchronous Serial Port Interrupt Enable bit
CCP1IE: CCP1 Interrupt Enable bit
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
TMR1IE: TMR1 Overflow Interrupt Enable bit

The PIR1 register (address 0Ch)

It contains the individual interrupt flag bits for the various peripheral interrupts. An interrupt flag is set when
the condition causing the interrupt is present and is cleared when it is not absent.

PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit (flags that a write or read has occurred)
ADIF: A/D Converter Interrupt Flag bit (flags A/D conversion has been completed)
RCIF: USART Receive Interrupt Flag bit (flags that the USART buffer is full)
TXIF: USART Transmit Interrupt Flag bit (flags the USART buffer is empty)
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit (flags transmission/reception has occurred)
CCP1IF: CCP1 Interrupt Flag bit (flags a capture or a compare match has occurred)
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit (flags a match has occurred)
TMR1IF: TMR1 Overflow Interrupt Flag bit (flags an overflow occurred)

The PIE2 register (address 8Dh)

It contains the individual interrupt enable bits for the EEPROM and more peripheral interrupts. An interrupt
enable bit is set to enable the interrupt and cleared to disable the interrupt.

Bits 7, 5, 2 and 1 are unimplemented: Read as ‘0’

CMIE: Comparator Interrupt Enable bit
EEIE: EEPROM Write Operation Interrupt Enable bit
BCLIE: Bus Collision Interrupt Enable bit
CCP2IE: CCP2 Interrupt Enable bit

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The PIR2 (address 0Dh)
It contains the individual interrupt flag bits for the peripheral interrupts. An interrupt flag is set when the
condition causing the interrupt is present and is cleared when it is not absent.

Bits 7, 5, 2 and 1 are unimplemented: Read as ‘0’

CMIF: Comparator Interrupt Flag bit (flags comparator input has changed)
EEIF: EEPROM Write Operation Interrupt Flag bit (flags the write operation completed)
BCLIF: Bus Collision Interrupt Flag bit (flags a bus collision has occurred in the SSP when configured for I2C
Master mode)
CCP2IF: CCP2 Interrupt Flag bit (flags register capture or a TMR1 register compare match occurred)

The PCON register (address 8Eh)

The Power Control (PCON) register contains flag bits to allow differentiation between a Power-on Reset (POR),
a Brown-out Reset (BOR), a Watchdog Reset (WDT) and an external MCLR Reset. A flag is set if the
corresponding reset occurred.

Bits 7 – 2 are unimplemented: Read as ‘0’

POR: indicates power-on reset occurred
BOR: indicates brown-out reset occurred

Indirect addressing registers

Two registers are used for indirect addressing: the INDF (addresses 00h, 80h, 100h and 180h) and file select
register, FSR (addresses 04h, 84h, 104h and 184h).
 FSR is used to hold the lowest 8 bits of the RAM address to be accessed indirectly. The 9th bit is
provided by the IRP bit in the STATUS register.
 The INDF register is not a physical register. When it is accessed, it results in the file register whose
address is formed by concatenating the IRP and the value in the FSR (i.e. IRP:FSR) being accessed.
Indirect addressing is used only in data transfer operations.

The Program Counter

 The Program Counter (PC) is 13 bits wide.
 It is built from two SFRs which are PCL and PCLATH.
 PCL supplies the lower byte whilst PCLATH supplies the upper 5 bits.
 PCL is at addresses 02h, 82h, 108h and 182h in the data RAM memory space
 PCLATH is at addresses 0Ah, 8Ah, 10Ah and 18Ah in the data RAM memory space

Program Memory
 The program memory is divided into four pages of 2k words each.
 By design, branch instructions (CALL and GOTO) supply an 11-bit branch offset. This is the offset of the
instruction to an instruction to be branched to from the start of the page. The offset, thus, allows
branching only within a page.

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  The offset becomes the lower 11 bits of the PC. The upper two bits are provided by PCLATH bits 4 and
3. The full address to be branched to is thus, formed from concatenating the 11-bit offset provided by
the instruction with PCLATH bits 4 and 3.
 When branching across a 2k boundary, the programmer must select the page by writing to bits 3 and
4 of the PCLATH before the call instruction is executed.
 For return instructions, PCLATH and PCL are loaded with whole 13-bit address from stack, hence it is
not necessary to select the page to return to.

PIC16F877 Instructions
The PIC16F877 instructions can perform the following operations: data transfer; arithmetic (add, subtract,
increment, decrement); logic (AND, OR, XOR, NOT); rotates; bit operations (set, clear, test and skip is set, test
and skip if set); program flow (unconditional branch, conditional branch, call, return).

The PIC16F877 has 35 instructions that are all 14-bits wide. The bits are distributed into opcode and operand
bits. The instruction structures are grouped into byte-oriented, bit-oriented, literal and control instructions.
The respective instruction encodings for the instruction groups are shown in figure 2.3.

Figure 2.3 Instruction formats in different categories

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Byte-oriented file Operations
 They perform various operations on values in file registers – data transfer, arithmetic, logic and
rotates. In two-operand instructions, one of the operands is always held in the working register. The
destination of the operation is either the working register or a file register.
 The file register to be operated on is specified using a direct address (lowest 7 bits). The destination
of the result is specified using a destination specifier bit.

Bit-oriented file Operations

 They perform various operations on particular bits in file registers – set bit, clear bit and bit test.
 The bit to be operated on is specified using a bit number (0 to 7) specifying the bit position). The file
register containing the bit is specified using a direct address (lowest 7 bits).

Literal and Control Operations

 They can be put into two subgroups.
 The first subgroup performs various operations on immediate values – data transfer, arithmetic, logic
and return with literal. The working register is always involved and stores results of the operation. The
instruction specifies the 8-bit immediate value to be operated on.
 The second subgroup is the call and goto instructions. These cause branching to a specified address.
The instruction specifies the address to be branched to (11 lower bits of the address).

Control Operations
 They perform control operations on the PIC. They do not need any operand to be specified and all bits
represent the opcode. The opcode implicitly imply a particular register, bit or operation.

Microchip Assembly Language

 Microchip assembly language is used to write the instructions.
 Figure 2.4 shows the instruction set for the PIC16F877.

Format of Assembly Instructions

 The opcode is separated from the operands using at least one space. The operands are separated
using a comma.
 f represents the file direct register address. It is a number in the range 0 to 127. For SFRs, the file
register name can be used. A user defined name may also be used. The address is the offset within a
bank. Hence, the bank must be selected using bank select bits before the instruction is executed.
 d represents the destination specifier (0 or 1). When it is 0, the destination is the working register.
When it is 1, the destination is the file register specified by the direct address.
 b represents the bit specifier (values 0 to 7). It specifies the position of the bit to be operated on: 7
represents the MSB and 0 represents the LSB.
 k represents an immediate data (8 bits) value or an address value (11 bits).
 Numbers are represented as follows:
o Hexadecimal – the prefix 0x is used, e.g., 0x56, 0xC8.
o Binary – the prefix 0b is used, e.g., 0b10110011.
o Decimal – the number is used with no prefix, e.g. 43, 125.

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 Figure 2.4 Instruction set Summary

Instruction Examples
 ADDWF 27,1 ; add contents of file register at 27 (decimal) to accumulator, store in file register.
 DECF 0x63,0 ; decrement contents of file register at 27 (hex), store result in file register.
 MOVWF 0x7E ; move contents of working register into a file register at 7E (hex).
 INFSZ 78,0 ; increment contents of file register at 78 (decimal), store result in file register,
; skip next instruction if result is zero.

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  BSF 0x77,5 ; set bit 5 in file register 77 (hex)
 BTFSC STATUS,C ; test the carry flag, skip next instruction if carry flag is set.
 XORLW 0x5A ; exclusive OR the number 5A (hex) with contents of working register.
 CALL 0x2C5 ; call subroutine at address 2C5 (hex).
 RETLW 0xC5 ; return with the literal C5 (hex) in the working register.

Working with Banks

For instructions that specify the address of a file register, it is important to ensure the correct bank has been
selected before executing the instruction. Once selected, a bank will only change when the values in the RP0
and RP1 bits have been changed. As an example, suppose the current bank is bank 2 and there is need to
enable interrupts and then select bank 0. The following sequence of instructions may be used:
BSF STATUS,RP1 ;
BCF STATUS,RP0 ; select bank 1 (the two instructions select the page)
MOVLW 0x01000111
MOVWF PIE1 ; enable and disable different interrupts
BSF PIE2,EEIE ; enable interrupts
BCF STATUS,RP0 ; select bank zero

Some Useful Microchip Program Snippets

Conditional Branches
It is effected using a combination of conditional skip and a goto instructions. For example, when branching is
required when a zero is produced:
loop: INCFZ 51,1
GOTO loop

If file register 51 does not contain a zero, the GOTO is executed causing branching. If it contains a zero, the
GOTO is skipped and execution continues at the instruction following the GOTO hence no branching done.

Delay Program
In software, a delay can be achieved by decrementing a register in a loop until it gets to zero or incrementing
a register in a loop until it gets to some maximum value. Between the point of entry and the point of leaving
the loop, a delay lapses. The duration of the delay is determined by the initial value loaded into the register to
be decremented or incremented. Longer delays may be generated by nesting one-register delay routines.

The program for a delay using two nested dummy decrement loops is:
delay: MOVLW 0xff ; number of times to decrement outer register
MOWVF fr1 ; load into file register
d1: MOVLW 0xff ; number of times to decrement inner register
MOVWF fr2 ; load into file register
d2: DECFSZ fr2,1 ; decrement inner register until zero
GOTO d2
DECFSZ fr1,d1 ; decrement outer register until zero

The program for a delay using increment loops will be seen in a later chapter.

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Indirect Addressing Program
A program to fill a block of file registers from addresses 0x21 to 0x91 with the value 0x3E will be used to
illustrate indirect addressing. The program that may be used is:
MOVLW 0x21 ; starting address of memory block
MOVWF fsr ; store in file select register
MOVLW 0xaa ; number of locations to be filled with values
MOVWF 0x70 ; store in file register designated as counter
MOVLW 0x3e ; the number to be stored in memory block
loop: MOVWF indf ; effect indirect move
DECFSZ 0x70 ; repeat till all locations filled up
GOTO loop

Decoding Using the RETLW

The RETLW instruction can be used to decode values into a different format. This uses a combination of
addition of a value to the value in PCL and a return with literal instruction. For example, to decode BCD codes
into seven segment codes, the following piece of code may be used:
decode: MOVWF 0x5 ; initialise W with BCD code to be decoded
ADDWF PCL,1 ; add value to PC
RETLW ‘0’ ; return with code for ‘0’ in W
RETLW ‘1’ ; return with code for ‘1’ in W
RETLW ‘2’ ; return with code for ‘2’ in W
RETLW ‘3’ ; return with code for ‘3’ in W
RETLW ‘4’ ; return with code for ‘4’ in W
RETLW ‘5’ ; return with code for ‘5’ in W
RETLW ‘6’ ; return with code for ‘6’ in W
RETLW ‘7’ ; return with code for ‘7’ in W
RETLW ‘8’ ; return with code for ‘8’ in W
RETLW ‘9’ ; return with code for ‘9’ in W

The approach can be adapted to decode any other values that may have a sequential behaviour like BCD
codes.

Handling Interrupts
There are 15 sources of interrupts and all interrupts cause branching to address 04h.

Sequence of Events under Interrupt Conditions

The sequence of events when an interrupt occurs is:
 GIE is cleared to disable responses to further interrupts.
 The PC is pushed to the stack to preserve the return address.
 The PC is loaded with 04h so that program execution branches to address 04h where the handler is
located.
 The PIC executes instructions until it reaches a return from interrupt instruction (RETFIE). Since all
interrupts cause branching to address 04h, it is necessary to check interrupt flags so as to determine
the interrupt that has occurred.
 Execution of the RETFIE causes the return address to be popped from the stack into the PC and the
GIE to be set.

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Figure 2.5 summarises the various interrupt sources and also indicates how they may be managed.

Figure 2.5

Sample Program to handle interrupts

A sample Microchip program that can be used to handle interrupts is shown next:
org 00h
goto main

org 04h
btfsc INTCON,INTF
goto extern ; external interrupt
btfsc INTCON,TMR0IF
goto tim_1 ; timer interrupt
btfsc PIR1.ADIF
goto adconv ; ADC interrupt
btfsc PIR2,EEIF
goto eprom ; EPROM interrupt
bcf INTCON,RBIF ; clear flags for undesired interrupts
clrf PIR1 ; clear flags for
clrf PIR2 ; undesired interrupts
retfie ; return from interrupt code for
; checking interrupts

main: . ; main code of program

.

extern: . ; code for external handler

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 .

adconv: . ; code of ADC interrupt

.
. ; and rest of handlers

The reset vector is at 00h. There are only four locations before running into the interrupt vector. Hence, a
jump is located at 00h so that the main program is located at a place where there is enough space.

Conditional jumps are used within the ISR to branch to a program section that handles the particular interrupt
condition.

Context Saving During Interrupts

Only the PC is saved on the stack when an interrupt occurs. Any other file register that needs to be saved is
saved onto a user-defined stack in the RAM area using ordinary data transfer instructions. Typically, registers
W, STATUS, PCLATH and FSR may require saving when an interrupt occurs. The following code snippet shows
how context switching may be achieved.

MOVWF W_TEMP ; Save W in W_TEMP register

SWAPF STATUS,0 ; Swap status into W
CLRF STATUS ; Clear IRP, RP1, RP0 and hence go to bank 0
MOVWF STATUS_TEMP ; Save STATUS in STATUS_TEMP register
MOVF PCLATH,0 ; Copy PCLATH into W
MOVWF PCLATH_TEMP ; Save PCLATH in PCLATH_TEMP
CLRF PCLATH ; Go to page zero of program memory.

: ; User code for ISR

MOVF PCLATH_TEMP,0 ; Move PCLATH_TEMP into W

MOVWF PCLATH ; Restore PCLATH
SWAPF STATUS_TEMP,0 ; Move STATUS_TEMP register into
MOVWF STATUS ; Restore STATUS
SWAPF W_TEMP,F ; Swap W_TEMP into W
SWAPF W_TEMP,W ; Restore W
RETFIE

Chapter 2 Tutorial Questions

1. Write Microchip instructions to
a) Store the number 3Eh in file registers at addresses 39H, 15Bh and 1FEh.
b) Enable response to all interrupts
c) Enable timer 0 interrupt
d) Enable response to all peripheral interrupts
e) Enable EEPROM write complete interrupt
f) Assign the prescaler to the watchdog timer

2. The following program segment is running in a microcontroller

BCF OPTION_REG,RP0
BCF OPTION_REG,RP1
MOVLW 0x33
MOVF 0x70,1

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 MOVLW 0x9D
MOVF 0x71,1
MOVLW 0x35
MOVF FSR,1
MOVLW 0x23
SUBWF 0x70,1
RRF 0x71,0
XORW 0x55
MOVF INDF,1
BSF OPTION_REG,RP0
BCF 0x71,2
MOVLW 0x71,0
MOVF 0x35,1

Draw a table showing the contents of the file registers W, 35h, 70h, 71h, 115h and FSR after execution
of each instruction in the program. Also indicate contents of the carry flag as well as the current page
for each instruction.

3. The following program is running in a PIC:

TEMP0 equ 2DH
TEMP1 equ 2EH

MOVF PORTD,0
MOVF TEMP0,1
MOVLW 0x33
MOVF TEMP1,1
BSF TEMP1,0
BCF TEMP1,7
MOVF TEMP1,0
SUBLW 0XCF
BTFSS OPTION_REG,C
GOTO NEXT
MOVF TEMP1,0
MOVF PORTC,1
NEXT: CLRF TEMP0

Port D pins have the following voltages from the MS pin to LS pin: 0V, 5V, 0V, 0V, 0V, 0V, 5V, 5V.

Draw a table indicating which instructions will be executed and also showing the contents of the
working register W, file registers 2DH and 2Eh, and port C after execution of each instruction in the
program.

4. Write Microchip programs to do the following

a) Convert an 8-bit value into three BCD codes for units tens and hundreds (find number of hundreds,
tens and units in the value).
b) Convert a BCD code into seven segment code for a common cathode seven segment display using
the RETLW instruction.
c) Convert a BCD code into an ASCII code.

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d) Store the number 3Dh in file registers 21h – 40h
e) Provide a delay of 1 microsecond for a clock frequency of 10Mhz.
f) Provide a delay of 1 millisecond for a clock frequency of 10Mhz.
g) Provide a delay of 1 second for a clock frequency of 10Mhz.
h) Add 16 bit numbers.
i) Subtract 16 bit numbers.
j) Multiply two 8 bit numbers.
k) Divide a 16-bit number by an 8-bit number (give result as a quotient and a remainder).

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