MOSFET amplifiers

Unit II
Lecture I
 MOSFET amplifiers- Syllabus

▪ Single ended amplifiers:

• CS amplifier
▪ Current mirrors
• With resistive load
• Basic current mirror
• Diode connected load
• Cascode current mirror
• Current source load
• Triode load
• Source degeneration
• CG and CD amplifiers
▪ Cascode amplifier
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• Current sources have many important applications in analog design

• For example, some digital-to-analog converters employ an array

of current sources to produce an analog output proportional to the
digital input

• Current sources in conjunction with "current mirrors," can perform

useful functions on analog signals

 Current mirrors

• Definition:

1. Circuit designed to copy a current through one active device

2. By controlling the current in another active device of a circuit

3. Keeping the output current constant regardless of loading

• Application:

• The current mirror is often used to provide bias currents and active loads in
amplifier stages

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 Fig. 2.1.1 Two application scenarios of current sources

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 Current mirror - design issues

MOS devices operating in saturation can act as a current source

• Output resistance and capacitance and the voltage headroom of a current source
trade with the magnitude of the output current

• Supply, process, and temperature dependence

• Output noise current

• Matching with other current sources

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 Need for stable current source

• Consider the simple resistive biasing

Fig. 2.1.2 Definition of current by resistive divider

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 Need for stable current source
• Assuming M1 is in saturation,

• n -Mobility of electrons in the channel

• Cox - Gate-oxide capacitance per unit area

• W - Transistor width

• L - Effective channel length

• VTH or Vt - Threshold voltage

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 Need for stable current source

• The eqn. (1) reveals various PVT dependencies of Iout

• Overdrive voltage is a function of VDD and Vt

• Threshold voltage may vary by 50 to 100 mV from wafer to wafer

• Both μn and Vt exhibit temperature dependence

• Thus, Iout is poorly defined

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 Need for stable current source

• The issue becomes more severe as the device is biased with a smaller overdrive
voltage

• e.g., to consume less headroom and support greater voltage swings at the drain

• With a nominal overdrive of, say, 200 mV, a 50-mV error in VTH results in a
44% error in the output current

• Process and temperature dependencies exist even if the gate voltage is not a
function of the supply voltage

• For this reason, we must seek other methods of biasing MOS current sources

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 Copying currents from reference

• Design of current sources in analog circuits is based on “copying” currents from

a reference,

• With the assumption that one precisely-defined current source is already

available

Fig. 2.1.3 Use of a reference to generate various currents

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 Copying currents from reference

• A relatively complex circuit, sometimes

requiring external adjustments is used to
generate a stable reference current
IREF

• IREF is then cloned to create many

current sources in the system

Fig. 2.1.4 Conceptual means of copying currents

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 Guarantee for Iout = IREF

• For a MOSFET, if ID = f (VGS), where f (·) denotes the dependence of ID upon

VGS, then VGS = f −1 (ID)

• If a transistor is biased at IREF, then it produces VGS = f −1(IREF)

• Thus, if this voltage is applied to the gate and source terminals of a second
MOSFET, the resulting current is

Iout = f [ f −1 (IREF) ] = IREF

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 Diode connected MOSFET
• When the MOSFET has the gate connected to the drain, it acts like a diode with
characteristics similar to a pn-junction diode.
• when the gate is connected to the drain of an enhancement MOSFET, the MOSFET is
always in the saturation region

• Since VT is always greater than zero for an enhancement device, then vDG = 0 satisfies the
conditions for saturation
• This configuration exhibits small-signal behavior similar to that of two-terminal resistor
• Since saturation VGS=VDS
• MOSFET is configured as a
diode while carrying a
current of IREF
VGS must be generated from IREF
VGS = f −1(IREF)
 Basic current mirror
• The structure consisting of M1 and M2 in Fig. (b) is the current mirror

(a) (b)
Fig. 2.1.5 (a) Diode-connected device providing inverse function
(b) Basic current mirror 15
 Basic current mirror
• The transistors need not be identical

• Neglecting channel-length modulation,

obtaining
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 Basic current mirror

• Key property of this topology

• It allows precise copying of the current with no dependence on process and

temperature

• The translation from IREF to Iout merely involves the ratio of device dimensions

• Device dimensions - Quantity that can be controlled with reasonable accuracy

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 Cause and Effect relationships

1. VGS = f −1(IREF)

• VGS must be generated from IREF; i.e., IREF is the cause and VGS is the effect

• A MOSFET can perform this function only if it is configured as a diode

while carrying a current of IREF [M1 in current mirror circuit]

2. f [ f −1(IREF)] = IREF

• The transistor must sense f −1(IREF) (= VGS) and generate f [f −1(IREF)] i.e., the
cause is VGS and the effect is the output current, f [f −1(IREF)]

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 Long current mirror chains

• If all of the transistors are in saturation

• Also and
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 Long current mirror chains
• Thus,

• where and

• Proper choice of α and β can establish large or small ratios between ID4 and IREF

• Example

• α =  = 5 yields a magnification factor of 25

• α =  = 0.2 can be utilized to generate a small, well-defined current

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 Long current mirror chains

• However, copy of a copy may not be as clear as the original

• Owing to random mismatches between M1 and M2 , ID2 slightly deviates from

its nominal value

• Similarly, as ID2 is copied onto ID4, additional errors accumulate

• Therefore long current mirror chains must be avoided

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 Fig. 2.1.6 Structure of a MOS device

Leff : Effective length of gate Ldrawn : Total Length of gate

LD : Amount of side diffusion W : Width of gate
Tox : Oxide thickness

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 Sizing Issues

• Current mirrors usually employ the same length for all of the transistors so as to
minimize errors due to the side-diffusion of the source and drain areas (LD)

• If Ldrawn is doubled, then Leff = Ldrawn − 2LD is not exactly doubled

• Threshold voltage of short-channel devices exhibits some dependence on the channel

length

• Thus, current ratioing is achieved by scaling only the width of the transistors

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 Sizing Issues- generation of 2IREF
• To copy a reference current, IREF, and generate 2IREF

• Choose 2WREF for the current source

(a) (b)
Fig. 2.1.7 (a) Current mirror multiplying IREF by 2 (b) Effect of gate corner on
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current accuracy
 Sizing Issues- generation of 2IREF

• Unfortunately, direct scaling of the width also faces difficulties

• Since the corners of the gate are poorly defined, if the drawn W is
doubled, the actual width does not exactly double

• We thus prefer to employ a unit transistor and create copies by repeating

such a device

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 Sizing Issues- generation of 2IREF

Fig. 2.1.8 More accurate current multiplication

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 Sizing Issues- generation of IREF/2

• To generate a current equal to IREF/2 from IREF

• The diode-connected device itself must consist of two units, each carrying
IREF/2

• Fig. 2.1.9 depicts an example for the generation of both 2IREF and IREF/2

• Each unit has a width of W0 and the same length

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 Sizing Issues- generation of IREF/2

Fig. 2.1.9 Current mirrors providing 2IREF, IREF/2 from IREF

by half-width device

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 Sizing Issues- generation of IREF/2

• This approach requires a large number of unit transistors if many different

currents must be generated

• It is possible to reduce the complexity by scaling the lengths, but not directly

• In order to avoid the errors due to LD, we can double the equivalent length by
placing two unit transistors in series

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 Sizing Issues- generation of IREF/2

• This approach preserves an effective length of Ldrawn− 2LD for each unit,
yielding an equivalent length of 2(Ldrawn − 2LD) for the composite device and
hence halving the current

Fig. 2.1.10 Current mirrors providing 2IREF, IREF/2 from IREF by series transistors
 Active current mirror - Introduction

• Current mirrors can process signals as well - operate as “active” elements

• If IREF increases by I, then Iout increases by I(W/L)2/(W/L)1

• Thus, the circuit amplifies the small-signal current if (W/L)2/(W/L)1 > 1

• At the cost of proportional multiplication of the bias current

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 Cascode Current Mirrors

• Basic current mirror - Neglects the channel-length modulation

• In practice, channel-length modulation produces significant error in copying

currents

• Especially if minimum-length transistors are used so as to minimize the

width and hence the output capacitance of the current source

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 Cascode Current Mirrors

Fig. 2.1.11 Basic current mirror

• For this simple mirror,

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 Cascode Current Mirrors

• Thus,

where  is channel length modulation coefficient

• While VDS1 = VGS1 = VGS2, VDS2 may not equal VGS2 because of the circuitry

fed by M2

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 Cascode Current Mirrors

• In order to suppress the effect of channel-length modulation in basic current

mirror, we can

(1) Force VDS2 to be equal to VDS1 - First Approach (or)

(2) Force VDS1 to be equal to VDS2 - Second Approach

• These two principles lead to two different topologies

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 Cascode Current Mirrors
• First Approach

• Cascode current mirror topology

• Based on the value of Vb

• Less accuracy topology

• Higher accuracy topology

• Second Approach

• Cascode current mirror topology using IR drop

• Two Vb generation methods

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 First Approach
• Ensure that VDS2 in current mirror is both constant and equal to VDS1

• A cascode device can shield a current source, thereby reducing the voltage
variations across it

Fig. 2.1.12 Cascode current source

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 First Approach

• Even though the analog circuit may allow VP to vary substantially, VY remains
relatively constant

• To ensure that VDS2 = VDS1

• We must generate Vb such that

Vb − VGS3 = VDS1 (= VGS1), i.e., Vb = VGS3 + VGS1

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 First Approach

• Vb can be established by two diode-connected devices in series provided that

VGS0 + VGS1 = VGS3 + VGS1

• Hence VGS0 = VGS3

Fig. 2.1.13 Modification of mirror circuit to generate the

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cascode bias voltage
 First Approach
• Now attach the Vb generator to the cascode current source

Fig. 2.1.14 Cascode current mirror

• The result allows accurate copying of the current even in the presence of body
effect
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 Sizing of the transistors
• To obtain the desired multiple of IREF, select L2 = L1 and scale W2 (in integer
units) with respect to W1

• Similarly, for VGS3 to be equal to VGS0, we choose L3 = L0 and scale W3 with

respect to W0 by the same factor

i.e., W3/ W0 = W2/ W1

• In practice, L3 and L0 are equal to the minimum allowable value so as to minimize

their width, while L1 and L2 may be longer in some cases

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 First Approach
• While operating as a current source with a high output impedance and accurate value,
the topology nonetheless consumes substantial voltage headroom

• For simplicity, let us neglect the body effect and assume that all of the transistors
are identical

• Then, the minimum allowable voltage at node P is equal to

• i.e., two overdrive voltages plus one threshold voltage

• Thus, Cascode mirror of Fig. 2.1.14 “wastes” one threshold voltage in the headroom
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 First Approach

• First topology based on Vb value (Summary)

• Vb is chosen to allow the lowest possible value of VP

• But the output current does not accurately track IREF because M1 and M2
sustain unequal drain-source voltages

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 First Approach

Fig. 2.1.15 Cascode current source with minimum headroom

voltage

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 First Approach
• Second topology based on Vb value (Summary)

• A higher accuracy is achieved, but the minimum level at P is higher by one

threshold voltage

2/27/2021 Fig. 2.1.16 Headroom consumed by a cascode mirror 45

 Second Approach

• In order to avoid the Vt penalty in the voltage headroom of the above cascode
current source,

• VDS1 is forced to be equal to VDS2 instead

• Vt headroom consumption is eliminated

• only if Vb = VGS3 + (VGS2 − Vt2)

• i.e., only if VDS2 is around one overdrive voltage

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 Second Approach

• To ensure that VDS1 = VDS2 (= VGS2 − Vt2)

• Since M1 is a diode-connected device, it appears impossible to expect a VDS1

less than one threshold

• But, a deliberate voltage difference can be created between the gate and
drain of M1 by a means of a resistor

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 Second Approach

• The idea is to choose

R1 IREF ≈ Vt1 and Vb = VGS3 + (VGS1 − Vt1) (10)

• Now, VDS1 = VGS1 − R1 IREF ≈ VGS1 − VTH1, which is equal to Vb − VGS3 and hence
to VDS2

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 Second Approach

Fig. 2.1.17 Use of IR drop to improve accuracy of current mirror

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 Second Approach

• Issues:

1. In the presence of PVT variations, it may be difficult to guarantee that R1IREF ≈

Vt1 as R1 and Vt may vary differently

2. The generation of Vb = VGS3 + (VGS1 − Vt1) is not straightforward

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 Second Approach

• Vb generation

• That adds one gate-source voltage to an

overdrive, surmising that we must begin with
a diode-connected device

Fig. 2.1. 18 Generation of Vb

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 Second Approach

Vb = VGS5+ R6 I6 (11)

• We can readily choose I6 and the dimensions of M5 to ensure that VGS5 = VGS3

• However, the condition

R6 I6 = VGS1 − VTH1 = VGS1 − R1IREF (12)

translates to

R6 I6 + R1 IREF = VGS1, which is difficult to meet because the IR products do not

“track” the MOS gate-source voltage

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 Second Approach

• Alternative generation of Vb

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 Second Approach

• M5 establishes the VGS, and M6 and R6 the overdrive

• Select I6 and the device parameters such that

VGS5 = VGS3 (13)

VGS6 − R6 I6 = VGS1 − Vt1 = VGS1 − R1 IREF (14)

• It is now possible to ensure that VGS6 and VGS1 track each other, and so do
R1IREF and R6 I6

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