Published by : International Journal of Engineering Research & Technology (IJERT)

http://www.ijert.org ISSN: 2278-0181

Vol. 9 Issue 02, February-2020

Design of Low Power Multiplier Unit

using Wallace Tree Algorithm
R.Krishnaveni B.Sivaranjani P.Sakthy Priya
Electronics and Communication Electronics and Communication Electronics and Communication
Engineering Engineering Engineering
National Engineering College National Engineering College National Engineering College
Kovilpatti, Tamil Nadu Kovilpatti, Tamil Nadu Kovilpatti, Tamil Nadu

M.Sathishkumar I.Vivek Anand

Electronics and Communication Engineering Electronics and Communication Engineering
National Engineering College National Engineering College
Kovilpatti, Tamil Nadu Kovilpatti, Tamil Nadu

Abstract—A multiplier is one of the most important building for carrying out large arithmetical operations easily. To
block that is widely used in processor, embedded systems, evaluate the performance of the new multiplier, the multiplier
application specific integrated circuits and most of the DSP is compared with the already existing digital multipliers on
applications. Low power is an emerging trend which intern can various parameters as power consumption and speed of
maximize the lifespan of battery operating time. In this project,
it is proposed to balance and optimize the performance of
operation. In a typical processor, central processing unit
Wallace multiplier which consumes less power. The two main involves considerable amount of processing time in
sources of power consumption are static power dissipation and performing arithmetic operations, particularly multiplication
dynamic power dissipation. The multiplier has been designed operations. Multiplication is one of the basic arithmetic
and simulated using cadence tool. The three main thrust operations. It requires more hardware resources and
parameters of any VLSI design lies in speed, area and power. processing time when compare to addition and subtraction.
Low power is an emerging trend which intern can maximize the MULTIPLIERS can be designed by using any of the
lifespan of battery operating time. The main objective of the following methods. Here the main objective is to design low
project is to design and implement a low power multiplier used power consumption, consuming less area and a high-speed
for various VLSI applications. The work includes designing of
basic gates, half adder and full adder with operating voltage.
multiplier.
The multiplier block is implemented using Microwind tool. The
logic styles used in our proposed design of the multiplier are II. LOW POWER MULTIPLIER UNIT
CMOS. The power analysis has been carried out and measured A. Low Power Multiplier Unit
on CMOS logic. In any signal processing system, Multiplier plays an
important role and also perform as a basic building block
Keywords— Multiplier algorithm, Wallace multiplier, CMOS element. The performance of these types of processing
logic, Half adder, Full adder. systems depends on the performance of the inbuilt multiplier.
So it is acts as a challenging task for any designer to design a
I. INTRODUCTION high performance multiplier. There are different factors that
Now a days, Multiplier is one of the most important drive high performance electronic system for to design in
blocks in any processor. A binary multiplier is an electronic terms of low power dissipation and high speed. The basic
circuit used in digital electronics, to multiply two binary block diagram of a multiplier is shown in Fig 1.
numbers. A variety of computer arithmetic techniques can be A basic multiplier consists of three stages:
used to realize a digital multiplier. Most techniques involve 1. Generation of partial product
computing a set of fractional products, and then summing the 2. Addition of partial product
fractional products together. This process conducting the long 3. Final addition
multiplication on base-10 integers, but have been modified as
a number of base two systems. In more transistors, per chip Partial Addition of Final
became available due to larger-scale integration. It became to Product Partial Addition
put enough adders on a single Chip to sum all the fractional Generation Product
products at once than use again a single adder to handle each
partial product one at a time. In digital signal processing,
algorithm spends more time to multiply the processors. It Fig-1: Block diagram of multiplier unit
spends a lot of chip area in order to make the multiplication
as fast as possible. Hence a non conventional however very
efficient Vedic mathematics is used for making a high B. Multiplier Algorithm
performance multiplier. Vedic algorithms deals mainly with Array Multiplier
various Vedic mathematical formulae and their applications

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Array multiplier is a traditional method for multiplication. that a logarithmic depth reduction tree-based CSA’s has an
Array multiplier is popular due to its structure. It is based on irregular structure, therefore its design and layout is difficult.
add and shift algorithm. In parallel multiplication, the number
of partial products to be added is the main parameter that Booth Algorithm
determines the performance of the multiplier. With one Booth algorithm is the multiplication algorithm. It
multiplier bit each partial product is generated by the multiplies two binary numbers in two's complement notation
multiplication of the multiplicand. The partial products are of signed binary numbers. The algorithm was invented by
shifted according to their bit order and then it gets added with Andrew Donald Booth in 1950 while doing research on
normal carry propagate adder. Crystallographyat Birkbeck College in Bloomsbury, London.
For n x n array multiplier, number of adders and gates Booth's algorithm is the interest of studying computer
required are: architecture. Booth multiplier is best for signed numbers.
1. n(n-2) full adders Booth used desk calculators that were faster at shifting than
2. n half adders adding & created the algorithm to increase their speed. Hence
3. AND gates to reduce the iterations Booth’s Algorithm is developed for
The advantage of array multiplier is that it has minimum multiplying signed as well as unsigned numbers. It initiates
complexity and regular structure. Disadvantages are large with the ability to both add and subtract, there are multiple
number of logic gates, so more chip area and it has high ways to calculate a product. This multiplier can scan the three
power consumption and it is limited to 16-bits. bits at a time hence the delay decreases. But the power
consumption of this multiplier is more hence the efficiency of
the system reduces.
Wallace-Tree Multiplier Example: 3 x (-4).
Wallace tree is an efficient hardware implementation of m = 3 = 0011, r = (-4) = 1100.
a digital circuit that multiplies two integers, devised by
Multiplication can be implemented by repeatedly adding
Australian Computer Scientist Chris Wallace in 1964.
one of two predetermined values A and S to a product P, then
The Wallace tree has three steps:
rightward arithmetic shift on P.
• In one of the arguments each bit is multiplied by
each bit of the other, yielding results. The Karatsuba Algorithm
wires carry different weights depending on The Karatsuba algorithm is a fast multiplication
position of the multiplied bits, algorithm. It was discovered by Anatoly Karatsuba in 1960,
• The number of partial products reduced to two published in 1962. Karatsuba algorithm uses a divide and
by layers of full and half adders. conquers approach. Where it breaks down the inputs into
• The wires in two numbers gets grouped, and Most Significant half and Least Significant half.
added with a conventional adder.
Recursive application of Karatsuba Algorithm
If n are four or more, the three multiplications in
Karatsuba's basic step involve operands with fewer than n
digits. Therefore, products can be computed by recursive
calls of the Karatsuba algorithm. The recursion can be
applied until the numbers are small that they can be computed
directly.
In a computer with a full 32-bit by 32-bit multiplier, for
example, one could choose B = 231 = 2,147,483,648, and
store each digit as a separate 32-bit binary word. Then the
sums x1+ x0 and y1 + y0 will not need an extra binary word
for storing the carry-over digit, and the Karatsuba recursion
can be applied until the numbers to multiply only one digit
long.
Karatsuba algorithm uses divide and conquer approach
where it break down the inputs into Most significant half and
Least significant half. Karatsuba algorithm is suited for
operands of higher bit length. For multiplication, break down
the input into two such as XH and XL.

Vedic Multiplier
Vedic Mathematics is a book written by the Indian monk
Swami Bharati Krishna Tirtha, published in 1965. It contains
Fig-2: Example of Wallace Tree Multiplier
a list of mental calculation techniques claimed to be based on
the Vedas. The calculation system mentioned in the book is
The advantage of Wallace-tree multiplier is that it becomes also known by the same name or as "Vedic Maths". It is
more pronounced for more than 16-bits. And Disadvantage is characterised as "Vedic" mathematics and has been criticized

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by academics, who have also opposed its inclusion in the Function and Algorithm of Modules
Indian school curriculum. Ancient mathematics has 16 2’S Complement Generator
different sutras, which are taken from Atharva Ved. For Function: The 2’s complement generator takes the
multiplication, there are two sutras. Urdhva-Tiryagbhyam is multiplicand MD and MR as its input and produces MD and
one of the sutra from 16-Vedic sutras which performs the – MR as its output in case of negative numbers.
product of two decimal numbers. Urdhva-Tiryagbhyam is the Algorithm: 2’s complement is generated by inverting all
general formula applicable to all cases of multiplication of a bits of the multiplicand and then adding 1 using a ripple carry
large number by another large number. “Urdhva” means adder.
vertical and “Tiryagbhyam” means crosswise therefore it is
also called as vertical and Crosswise Algorithm. Partial Product Generator
Function: The partial product generator generates the
partial products to be added with a Wallace tree.
Algorithm: The partial product generator uses the table
for each multiplier bit. Depending on the value of MD or –
MD and MR or- MR, it is assigned to partial product. 4 bit is
then extended to 7th bit for appropriate sign extension.

Carry Look-Ahead Adder

Function: Carry Look-Ahead adder (CLA) add two
numbers with very lower latency.
Algorithm: By extending c with the corresponding
Fig-3: Example for Vedic Multiplier
inputs, the carry and sum are independent of the previous
bits.
Its advantage is that it has Minimum Delay. As number of
Wallace Multiplication
bits increases, multiplication process becomes tedious which
Function: The Wallace tree module adds with the 4
is a major disadvantage in Vedic multiplier.
partial products and generates two intermediate operands for
By comparing the all algorithms. We prefer Wallace tree
final addition.
multiplier because it provides the only efficient multiplier
which has substantial hardware savings, higher speeds, less
propagation delay, has reduced schematic layout and
occupies less area. Hence Wallace is very often preferable for
multipliers.

III. PROPOSED WALLACE TREE MULTIPLIER

A. Wallace Tree Multiplier
A Multiplier which is based on Wallace-tree structure is
called Wallace multiplier. It is more faster than other
multiplier architecture. Wallace multiplier operation is
carried out in three different steps. In this architecture, after
generating the partial product, accumulation of partial
product and final addition are done in different stages. When
the final stage contains only two rows, then final addition is Fig-4: Wallace Tree Multiplier
done. The number of rows of partial product in a particular
stage can be expressed as,
Ri+1 = 2(Ri /3) + Ri mod 3 IV. SOFTWARE USED
where, Ri gives the groups or stages. N= number of MICROWIND is truly integrated EDA software of IC
bits. Let us consider an example that N bits multiplication, designs from a concept to complete by enabling chip
N2 AND gates are required to generate the partial product designers to design beyond their imagination. It integrates
terms and the number of reduction stages is given by traditionally separated front-end and back-end chip design
S = log 2 N into one flow, accelerating design cycle and reduces design
complexities. It tightly integrates mixed-signal
Basic Building Blocks of Multiplier implementation with digital implementation, circuit
• Formation of partial product using AND gate logic. simulation, transistor-level extraction and verification to
• Reducing the ‘n’ number of partial products to a provide an innovative education and initiative to help
two-row partial products by compressing the individuals, to develop the skills needed for design positions
column’s with [3,2] & [2,2] adders. in every domain of IC industry.
• Merging two-rowed partial products with carry MICROWIND supports entire front-end to back-end
propagation Adders. design flow. We have DSCH (digital schematic editor) which
• 2bit result. posses in-built pattern based simulator for front-end

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Published by : International Journal of Engineering Research & Technology (IJERT)
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Vol. 9 Issue 02, February-2020

designing. User can also build analog circuits and convert

them into SPICE files and use third party simulators like
WinSpice or pSPICE.
DSCH can convert digital circuits into Verilog file
which can be further synthesized for FPGA/CPLD devices of
any vendor. In MICROWIND, the same Verilog file can be
compiled for layout conversion.
MICROWIND supports the back-end design of circuits.
User can design digital circuits and compile using Verilog
file. MICROWIND automatically generates an error free
CMOS layout. Although this place-route is not optimized
enough as we do not indulge in complex place & route
algorithms.
User can also create CMOS layout of their own use,
compiling one line Verilog syntax or custom build the layouts
by manual drawing.This layouts can be verified using inbuilt
mix-signal simulator and analyzed for DRC, crosstalks,
delays, 2D cross section, 3D view, etc.

Fig-6: Schematic diagram of OR gate

V. RESULTS

Fig-7: Symbol of Full adder

Fig-5: Schematic diagram of AND gate

Fig-8: Schematic diagram of EXOR gate

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VI. CONCLUSION
Thus schematic is designed for four bit multiplier for
which we provide two four bit data input lines and obtain the
product of 8bit.The designed multiplier is tested for various
data and functionally verified. The multiplier is implemented
using CMOS logic style. The Wallace tree multiplier is
designed and implemented using Microwind tool. The
schematic is designed using DSCH. Microwind tool is used
for the implementation of the multiplier design. The
schematic is designed for 4-bit multiplier. The complete
schematic of 4-bit multiplier is functionally verified and
implemented using Microwind tool. The synthesis result
confirms that the proposed Wallace tree multiplier is suitable
for low power and small area applications. A low power
and efficient multiplier is designed and implemented for
various VLSI applications.
Fig-9: Schematic diagram of Half adder

REFERENCES
[1] K. Gopi Krishna, B. Santhosh, V. Sridhar (2013) “Design of
Wallace Tree Multiplier using Compressors”, International
Journal of Engineering Sciences and Research Technology, Vol.
2, No. 9, pp. 2249-2254.
[2] Kokila Bharti Jaiswal, Nithish Kumar V, Pavithra Seshadri and
Lakshminarayanan G (2015) “Low Power Wallace Tree
Multiplier Using Modified Full Adder” 3rd International
Conference on Signal Processing, Communication and
Networking (ICSCN).
[3] M. Naresh, B. Suneetha (2017) “Design of Low Power Full
Adder Based Wallace Tree Multiplier Using Cadence 180nm
Technology” International Journal of Innovative Research in
Science, Engineering and Technology Vol. 6, Issue 5.
[4] S Venkateswara Reddy (2013) “Design and Implementation of 32
Bit multiplier using Vedic mathematics” International journal of
advanced research in electrical electronics and Instrumentation
engineering Volume 2 , Issue 8 .
[5] Swathi A.C, Yuvraj T, Praveen J, Raghavendra Rao A (2016) “A
Proposed Wallace Tree Multiplier Using Full Adder and Half
Adder” INTERNATIONAL Journal of Innovative Research In
Electrical, Electronics, Instrumentation And Control Engineering
Vol. 4, issue 5.
[6] C. S. Wallace (1964) “A suggestion for a fast multiplier,” IEEE
Transactions on Electronic Computers, vol. EC-13, pp. 14-17.

Fig- 10: Output of Multiplier unit

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