ISD4003 SERIES

SINGLE-CHIP, MULTIPLE-MESSAGES

VOICE RECORD/PLAYBACK DEVICES

4-, 5-, 6-, AND 8-MINUTE DURATION

Publication Release Date: January 2004

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1. GENERAL DESCRIPTION
The ISD4003 ChipCorder® series provides high-quality, 3-volt, single-chip record/playback solutions
for 4- to 8-minute messaging applications ideally for cellular phones and other portable products. The
CMOS-based devices include an on-chip oscillator, anti-aliasing filter, smoothing filter, AutoMute®
feature, audio amplifier, and high density multilevel Flash memory array. The ISD4003 series is
designed to be used in a microprocessor- or microcontroller-based system. Address and control are
accomplished through a Serial Peripheral Interface (SPI) or Microwire Serial Interface to minimize pin
count.

Recordings are stored into the on-chip Flash memory cells, providing zero-power message storage.
This unique single-chip solution utilizes Winbond’s patented multilevel storage technology. Voice and
audio signals are directly stored onto memory array in their natural form, providing high-quality voice
reproduction.

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2. FEATURES
• Single-chip voice record/playback solution
• Single 3 volt supply
• Low-power consumption
Operating current:
- ICC_Play = 15 mA (typical)
- ICC_Rec = 25 mA (typical)
Standby current:
- ICC_Standby = 1 µA (typical)
• Duration: 4, 5, 6, and 8 minutes
• High-quality, natural voice/audio reproduction
• AutoMute feature provides background noise attenuation
• No algorithm development required
• Microcontroller SPI or Microwire™ Serial Interface
• Fully addressable to handle multiple messages
• Non-volatile message storage
• 100K record cycles (typical)
• 100-year message retention (typical)
• On-chip oscillator
• Power-down feature to reduce power consumption
• Available in die form, PDIP, SOIC, and TSOP
• Temperature:
- Commercial (die): 0°C to +50°C
- Commercial (packaged units): 0°C to +70°C
- Extended: -20°C to +70°C
- Industrial: -40°C to +85°C

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3. BLOCK DIAGRAM

Internal Clock Timing

XCLK
Sampling Clock

ANA IN- 5-Pole Active

Amp Analog Transceivers
Antialiasing Filter
ANA IN+
1920K Cell

Decoders
Nonvolatile 5-Pole Active
Multilevel Storage Smoothing Filter
Array
AutoMuteTM
Feature

Amp AUDOUT

Power Conditioning Device Control

VCCA VSSA VSSA VSSA VSSD VCCD SCLK SS MOSI MISO INT RAC AM CAP

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4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION.................................................................................................................. 2
2. FEATURES ......................................................................................................................................... 3
3. BLOCK DIAGRAM .............................................................................................................................. 4
4. TABLE OF CONTENTS ...................................................................................................................... 5
5. PIN CONFIGURATION ....................................................................................................................... 6
6. PIN DESCRIPTION ............................................................................................................................. 7
7. FUNCTIONAL DESCRIPTION.......................................................................................................... 12
7.1. Detailed Description.................................................................................................................... 12
7.2. Serial Peripheral Interface (SPI) Description.............................................................................. 13
7.2.1. OPCODES ........................................................................................................................... 14
7.2.2. SPI Diagrams ....................................................................................................................... 15
7.2.3. SPI Control and Output Registers........................................................................................ 16
8. TIMING DIAGRAMS.......................................................................................................................... 18
9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 20
9.1. Operating Conditions .................................................................................................................. 21
10. ELECTRICAL CHARACTERISTICS ............................................................................................... 22
10.1. Parameters For Packaged Parts ........................................................................................ 22
10.2. Parameters For Die .............................................................................................................. 25
10.3. SPI AC Parameters .............................................................................................................. 26
11. TYPICAL APPLICATION CIRCUIT ................................................................................................. 27
12. PACKAGING AND DIE INFORMATION ......................................................................................... 30
12.1. 28-Lead 300-Mil Plastic Small Outline IC (SOIC)..................................................................... 30
12.2. 28-Lead 600-Mil Plastic Dual Inline Package (PDIP) ............................................................... 31
12.3. 28-Lead 8x13.4mm Plastic Thin Small Outline Package (TSOP) Type 1 ................................ 32
12.4. Die Information ......................................................................................................................... 33
13. ORDERING INFORMATION........................................................................................................... 35
14. VERSION HISTORY ....................................................................................................................... 36

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5. PIN CONFIGURATION

SS 1 28 SCLK
MOSI 2 27 VCCD
MISO 3 26 XCLK
VSSD 4 25 INT
NC 5 24 RAC
NC 6 23 VSSA
NC 7 22 NC
NC 8
ISD4003 21 NC
NC 9 20 NC
NC 10 19 NC
VSSA 11 18 VCCA
VSSA 12 17 ANA IN+
AUD OUT 13 16 ANA IN-
AM CAP 14 15 NC

SOIC / PDIP

VSSA 1 28 NC
RAC 2 27 NC
NC 3 26 VCCA
NC 4 25 ANA IN+
INT 5 24 ANA IN-
XCLK 6 23 NC
VCCD 7 22 AM CAP
SCLK 8
ISD4003 21 NC
SS 9 20 AUD OUT
MOSI 10 19 NC
MISO 11 18 VSSA
VSSD 12 17 VSSA
NC 13 16 NC
NC 14 15 NC

TSOP

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6. PIN DESCRIPTION
PIN NAME PIN NO. FUNCTION
SOIC / TSOP
PDIP

SS 1 9 Slave Select: This input, when LOW, will select the

ISD4003 device.
MOSI 2 10 Master Out Slave IN: This is the serial input to the
ISD4003 device when it is configured as slave. The master
microcontroller places data on the MOSI line one half-cycle
before the rising edge of SCLK for clocking into the device.
MISO 3 11 Master In Slave Out: This is the serial output (open drain)
of the ISD4003 device. This output goes into a high-
impedance state if the device is not selected.
VSSA / VSSD 11, 12, 1, 17, 18 / Ground: The ISD4003 series utilizes separate analog and
23 / 4 12 digital ground busses. The analog ground (VSSA) pins
should be tied together as close as possible and connected
through a low-impedance path to power supply ground.
The digital ground (VSSD) pin should be connected through
a separate low-impedance path to power supply ground.
These ground paths should be large enough to ensure that
the impedance between the VSSA pins and the VSSD pin is
less than 3 Ω. The backside of the die is connected to VSS
through the substrate. For chip-on-board design, the die
attach area must be connected to VSS or left floating.
NC 5-10, 15, 3, 4, 13- Not connected
19-22 16, 19, 21,
23, 27, 28
AUD OUT [1] 13 20 Audio Output: This pin provides an audio output of the
stored data and is recommended be AC coupled. It is
capable of driving a 5 KΩ impedance REXT.

[1]
The AUD OUT pin is always at 1.2 volts when the device is powered up. When in playback, the output buffer
connected to this pin can drive a load as small as 5 KΩ. When in record, a built-in resistor connects AUD OUT to
the internal 1.2-volt analog ground supply. This resistor is approximately 850 KΩ, but will vary somewhat
according to the sample rate of the device. This relatively high impedance allows this pin to be connected to an
audio bus without loading it down.

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PIN NAME PIN NO. FUNCTION

SOIC / TSOP
PDIP
AM CAP 14 22 AutoMute™ Feature: The AutoMute feature only applies
for playback operation and helps to minimize noise (with 6
dB of attenuation) when there is no signal (i.e. during
periods of silence). A 1 µF capacitor to ground is
recommended to connect to the AM CAP pin.
This capacitor becomes a part of an internal peak detector
which senses the signal amplitude. This peak level is
compared to an internally set threshold to determine the
AutoMute trip point. For large signals, the AutoMute
attenuation is set to 0 dB automatically but 6 dB of
attenuation occurs for silence. The 1 µF capacitor also
affects the rate at which the AutoMute feature changes with
the signal amplitude (or the attack time).
The AutoMute feature can be disabled by connecting the
AM CAP pin directly to VCCA..
ANA IN- 16 24 Inverting Analog Input: This pin transfers the signal into
the device during recording via differential-input mode.
In this differential-input mode, a 16 mVp-p maximum input
signal should be capacitively coupled to ANA IN- for
optimal signal quality, as shown in Figure 1: ANA IN
Modes. This capacitor value should be equal to that used
on ANA IN+ pin. The input impedance at ANA IN- is
normally 56 KΩ.
In the single-ended mode, ANA IN- should be capacitively
coupled to VSSA through a capacitor equal to that used on
the ANA IN+ pin.
ANA IN+ 17 25 Non-Inverting Analog Input: This pin is the non-inverting
analog input that transfers the signal to the device for
recording. The analog input amplifier can be driven single
ended or differentially.
In the single-ended input mode, a 32 mVp-p (peak-to-peak)
maximum signal should be capacitively connected to this
pin for optimal signal quality. The external capacitor
associated with ANA IN+ together with the 3 KΩ input
impedance are selected to give cutoff at the low frequency
end of the voice passband.
In the differential-input mode, the maximum input signal at
ANA IN+ should be 16 mVp-p capacitively coupled for
optimal signal quality. The circuit connections for the two
modes are shown in Figure 1.

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PIN NAME PIN NO. FUNCTION

SOIC / TSOP
PDIP
VCCA / VCCD 18 / 27 26 / 7 Supply Voltage: To minimize noises, the analog and digital
circuits in the ISD4003 devices use separate power
busses. These +3V busses are brought out to separate
pins and should be tied together as close to the supply as
possible. In addition, these supplies should be decoupled
as close to the package as possible.
RAC 24 2 Row Address Clock: This is an open drain output that
provides the signal of a ROW with a 200 ms period for 8
KHz sampling frequency. (This represents a single row of
memory.) This signal stays HIGH for 175 ms and stays
LOW for 25 ms when it reaches the end of a row.
The RAC pin stays HIGH for 109.37 µsec and stays LOW
for 15.63 µsec in Message Cueing mode (see Message
Cueing section for detailed description). Refer to the AC
Parameters table for RAC timing information at other
sample rates.
When a record command is first initiated, the RAC pin
remains HIGH for an extra TRACL period. This is due to the
need of loading the internal sample and hold circuits in the
device. This pin can be used for message management
techniques.
A pull-up resistor is required to connect this pin to other
device.

INT 25 5 Interrupt: This is an open drain output pin. This pin goes
LOW and stays LOW when an Overflow (OVF) or End of
Message (EOM) marker is detected. Each operation that
ends with an EOM or OVF will generate an interrupt. The
interrupt will be cleared the next time an SPI cycle is
initiated. The interrupt status can also be read by an RINT
instruction.
A pull-up resistor is required to connect this pin to other
device.
Overflow Flag (OVF) – The Overflow flag indicates that the
end of memory has been reached during a record or
playback operation.
End of Message (EOM) – The End of Message flag is set
only during playback operation when an EOM is found.
There are eight EOM flag position options per row.

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PIN NAME PIN NO. FUNCTION

SOIC / TSOP
PDIP
XCLK 26 6 External Clock Input: The pin has an internal pull-down
device. The ISD4003 series is configured at the factory with
an internal sampling clock frequency centered to ±1
percent of specification. The frequency is then maintained
to a variation of ±2.25 percent over the entire commercial
temperature and operating voltage ranges. The internal
clock has a –6/+4 percent tolerance over the extended
temperature, industrial temperature and voltage ranges. A
regulated power supply is recommended for industrial
temperature range parts. If greater precision is required,
the device can be clocked through the XCLK pin as follows:
Part Number Sample Rate Required Clock
ISD4003-04M 8.0 kHz 1024 kHz
ISD4003-05M 6.4 kHz 819.2 kHz
ISD4003-06M 5.3 kHz 682.7 kHz
ISD4003-08M 4.0 kHz 512 kHz

These recommended clock rates should not be varied

because the anti-aliasing and smoothing filters are fixed.
Otherwise, aliasing problems can occur if the sample rate
differs from the one recommended. The duty cycle on the
input clock is not critical, as the clock is immediately
divided by two. If the XCLK is not used, this input must
be connected to ground.
SCLK 28 8 Serial Clock: This is the input clock to the ISD4003 device.
It is generated by the master device (typically
microcontoller) and is used to synchronize the data transfer
in and out of the device through the MOSI and MISO lines,
respectively. Data is latched into the ISD4003 on the rising
edge of SCLK and shifted out of the device on the falling
edge of SCLK.

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Internal to the device

53KΩ

0.1 µ F ANA IN+ 3KΩ

Signal 32m Vp-p -
To Filter
+

0.1 µ F ANA IN- 3KΩ

53KΩ

Single-Ended Input Mode 1.2V

Internal to the device

53KΩ

0.1 µ F ANA IN+ 3KΩ

Input Signal 16m Vp-p -
To Filter
Input Signal 16m Vp-p +
180°
0.1 µ F ANA IN- 3KΩ
53KΩ

Differential Input Mode 1.2V

FIGURE 1: ISD4003 SERIES ANA IN MODES

TRAC
(200 ms)

RAC

25 ms
TRACL

FIGURE 2: RAC TIMING WAVEFORM DURING NORMAL OPERATION

(example of 8KHz sampling rate)

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7. FUNCTIONAL DESCRIPTION
7.1. DETAILED DESCRIPTION

Audio Quality
The Winbond’s ISD4003 ChipCorder® series is offered at 8.0, 6.4, 5.3 and 4.0 kHz sampling
frequencies, allowing the user a choice of speech quality options. Increasing the sampling frequency
will produce better sound quality, but affects duration. Please refer to Table 1: Product Summary for
details.
Analog speech samples are stored directly into on-chip non-volatile memory without the digitization
and compression associated with other solutions. Direct analog storage provides higher quality
reproduction of voice, music, tones, and sound effects than other solid-state solutions.

Duration
The ISD4003 Series is a single-chip solution with 4-, 5-, 6-, and 8-minute duration.

TABLE 1: PRODUCT SUMMARY OF ISD4003 SERIES

Part Number Duration Sample Rate Typical Filter Pass
(Minutes) (kHz) Band (kHz) *
ISD4003-04M 4 8.0 3.4
ISD4003-05M 5 6.4 2.7
ISD4003-06M 6 5.3 2.3
ISD4003-08M 8 4.0 1.7

* This is the –3dB point. This parameter is not checked during production testing and may vary due to process
variations and other factors. Therefore, the customer should not rely upon this value for testing purposes.

Flash Storage
The ISD4003 series utilizes on-chip Flash memory, providing zero-power message storage. The
message is retained for up to 100 years typically without power. In addition, the device can be re-
recorded typically over 100,000 times.

Memory Architecture
The ISD4003 series contains a total of 1,920K Flash memory cells, which is organized as 1,200 rows
of 1,600 cells each.

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Microcontroller Interface

A four-wire (SCLK, MOSI, MISO & SS ) SPI interface is provided for controlling and addressing
functions. The ISD4003 is configured to operate as a peripheral slave device, with a microcontroller-
based SPI bus interface. Read and write operations are controlled through this SPI interface. An
interrupt signal ( INT ) and internal read only Status Register are provided for handshake purposes.

Programming
The ISD4003 series is also ideal for playback-only applications, where single- or multiple-messages
playback is controlled through the SPI port. Once the desired message configuration is created,
duplicates can easily be generated via a programmer.

7.2. SERIAL PERIPHERAL INTERFACE (SPI) DESCRIPTION

The ISD4003 series operates via SPI serial interface with the following protocol.
First, the data transfer protocol assumes that the microcontroller’s SPI shift registers are clocked on
the falling edge of the SCLK. However, for the ISD4003, the protocols are as follows:

1. All serial data transfers begin with the falling edge of SS pin.

2. SS is held LOW during all serial communications and held HIGH between instructions.
3. Data is clocked in on the rising edge of the SCLK signal and clocked out on the falling edge of
the SCLK signal, with LSB first.

4. Playback and record operations are initiated when the device is enabled by asserting the SS
pin LOW, shifting in an opcode and an address data to the ISD4003 device (refer to the
Opcode Summary in the following page).
5. The opcodes contain <11 address bits> and <5 control bits>.
6. Each operation that ends with an EOM or Overflow will generate an interrupt. The Interrupt
will be cleared the next time a SPI cycle is initiated.
7. As Interrupt data is shifted out of the MISO pin, control and address data are simultaneously
shifted into the MOSI pin. Care should be taken such that the data shifted in is compatible
with current system operation. Because it is possible to read an interrupt data and start a new
operation within the same SPI cycle.
8. An operation begins with the RUN bit set and ends with the RUN bit reset.

9. All operations begin after the rising edge of SS .

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7.2.1. OPCODES
The available Opcodes are summarized as follows:
TABLE 2: OPCODE SUMMARY

Instructions OpCodes Descriptions

Address (11 bits) Control bits (5 bits)
<A0 – A10> C0 C1 C2 C3 C4
POWERUP <XXXXXXXXXXX> 0 0 1 0 0 Power-Up: Device will be ready for an operation after
TPUD.
SETPLAY <A0 – A10> 0 0 1 1 1 Initiates playback from address <A0-A10>.
PLAY <XXXXXXXXXXX> 0 1 1 1 1 Playback from the current address (until EOM or OVF).
SETREC <A0 – A10> 0 0 1 0 1 Initiates a record operation from address <A0-A10>.
REC <XXXXXXXXXXX> 0 1 1 0 1 Records from current address until OVF is reached or
Stop command is sent.
SETMC <A0 – A10> 1 0 1 1 1 Initiates Message Cueing (MC) from address <A0-
A10>.
MC [1] <XXXXXXXXXXX> 1 1 1 1 1 Performs a Message Cueing from current location.
Proceeds to the end of message (EOM) or enters OVF
condition if no more messages are present.
STOP <XXXXXXXXXXX> 0 1 1 X 0 Stops the current operation.
STOPPWRDN <XXXXXXXXXXX> X 1 0 X 0 Stops the current operation and enters into standby
(power-down) mode.
RINT [2] <XXXXXXXXXXX> 0 1 1 X 0 Read Interrupt status bits: Overflow and EOM.

Notes:
C0 = Message cueing
C1 = Ignore address bit
C2 = Master power control
C3 = Record or playback operation
C4 = Enable or disable an operation

[1]
Message Cueing can be selected only at the beginning of a playback operation.
[2]
As the Interrupt data is shifted out of the ISD4003, control and address data are being shifted in. Care should
be taken such that the data shifted in is compatible with current system operation. It is possible to read interrupt
data and start a new operation at the same time. See Figures 5 - 8 for references.

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7.2.2. SPI Diagrams

MOSI Input Shift Register

(Loaded to Row Counter

A0-A10
only if IAB = 0)

Row Counter Select Logic

P0-P10
OVF EOM

MISO Output Shift Register

FIGURE 3: SPI INTERFACE SIMPLIFIED BLOCK DIAGRAM

The following diagram describes the SPI port and the control bits associated with it.

MISO OVF EOM P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 0 0 0

LSB MSB

MOSI A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 C0 C1 C2 C3 C4

Message Cueing (MC)

Ignore Address Bit (IAB)

Power Up (PU)

Play/Record (P/R)

RUN

FIGURE 4: SPI PORT

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7.2.3. SPI Control and Output Registers

The SPI control register provides control of individual function such as play, record, message cueing,
power-up, power-down, start, stop and ignore address pointer operations.

TABLE 3: SPI CONTROL REGISTERS

Control Bit Control Register Bit Device Function
C0 MC Message Cueing function
= 1 Enable Message Cueing
= 0 Disable Message Cueing
[1]
C1 IAB Ignore Address bit
= 1 Ignore input address register (A0-A10)
= 0 Use the input address register (A0-A10)
C2 PU Power Up
= 1 Power-Up
= 0 Power-Down

C3 P/ R Playback or Record
= 1 Play
= 0 Record
C4 RUN Enable or Disable an operation
= 1 Start
= 0 Stop
Address Bits A0-A10 Input address register

TABLE 4: SPI OUTPUT REGISTERS

Output Bits Description
OVF Overflow
EOM End-of-Message
P0-P10 Output of the row pointer register

[1]
When IAB (Ignore Address Bit) is set to 0, a playback or record operation starts from address (A0-A10). For
consecutive playback or record, IAB should be changed to a 1 before the end of that row (see RAC timing).
Otherwise the ISD4003 will repeat the operation from the same row address. For memory management, the Row
Address Clock (RAC) signal and IAB can be used to move around the memory segments.

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Message Cueing
Message cueing (MC) allows the user to skip through messages, without knowing the actual physical
location of the messages. It will stop when an EOM marker is reached. Then, the internal address
counter will point to the next message. Also, it will enter into OVF condition when it reaches the end of
memory. In this mode, the messages are skipped 1,600 times faster than the normal playback
mode.

Power-Up Sequence
The ISD4003 will be ready for an operation after power-up command is sent and followed by the TPUD
timing (25 ms for 8 KHz sampling rate). Refer to the AC timing table for other TPUD values with respect
to different sampling rates.

The following sequences are recommended for optimized Record and Playback operations.

Record Mode
1. Send POWERUP command.
2. Wait TPUD (power-up delay).
3. Send POWERUP command.
4. Wait 2 x TPUD (power-up delay).
5. a). Send SETREC command with address xx, or
b). Send REC command (recording from current location).
6. Send STOP command to stop recording.
7. Wait TSTOP/PAUSE.
For 3 & 4), please refer to Apps Brief 39A: recorded pop elimination in the ISD4000 series.
For 5.a), the device will start recording at address xx and will generate an interrupt when an overflow
(end of memory array) is reached, if no STOP command is sent before that. Then, it will automatic
stop recording operation.

Playback Mode
1. Send POWERUP command
2. Wait TPUD (power-up delay)
3. a). Send SETPLAY command with address xx, or
b). Send PLAY command (playback from current location).
4. a). Send STOP command to halt the playback operation, or
b). Wait for playback operation to stop automatically, when an EOM or OVF is reached.
5. Wait TSTOP/PAUSE.
For 3.a), the device will start playback at address xx and it will generate an interrupt when an EOM or
OVF is reached. It will then stop playback operation.

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8. TIMING DIAGRAMS

T SSH

SS
T SSm in
T SSS T SCKhi

SCLK
T DIH T SCKlow
T DIS

M OSI

T PD T PD T DF
(TRISTATE)
M ISO LSB

FIGURE 5: TIMING DIAGRAM

SS

SCLK

LSB

MOSI A8 A9 A10 C0 C1 C2 C3 C4

LSB
MISO OVF EOM P0 P1 P2 P3 P4 P5

FIGURE 6: 8-BIT COMMAND FORMAT

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SS

SCLK

LSB
MOSI A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 C0 C1 C2 C3 C4

LSB
MISO OVF EOM P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 X X X

FIGURE 7: 16-BIT COMMAND FORMAT

≈

SS
≈

SCLK
≈

≈
≈ ≈

≈ ≈

≈ ≈

MOSI Play/Record Stop

≈ ≈
≈ ≈

MISO Data Data

≈

TSTOP/PAUSE

(Rec)

ANA IN
≈

TSTOP/PAUSE

(Play)

ANA OUT
≈

FIGURE 8: PLAYBACK/RECORD AND STOP CYCLE

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9. ABSOLUTE MAXIMUM RATINGS

TABLE 5: ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS)

CONDITIONS VALUES
Junction temperature 150°C
Storage temperature range -65°C to +150°C
Voltage applied to any pin (VSS –0.3V) to (VCC +0.3V)
Voltage applied to any pin (Input current limited to ±20mA) (VSS –1.0V) to (VCC +1.0V)

Voltage applied to MOSI, SCLK, and SS pins (VSS –1.0V) to 5.5V

(Input current limited to ±20mA)

Lead temperature (soldering – 10 seconds) 300°C
VCC – VSS -0.3V to +7.0V

TABLE 6: ABSOLUTE MAXIMUM RATINGS (DIE)

CONDITIONS VALUES
Junction temperature 150°C
Storage temperature range -65°C to +150°C
Voltage applied to any pad (VSS –0.3V) to (VCC +0.3V)
Voltage applied to any pad (Input current limited to ±20 mA) (VSS –1.0V) to (VCC +1.0V)

Voltage applied to MOSI, SCLK, and SS pins (VSS –1.0V) to 5.5V

(Input current limited to ±20mA)

VCC – VSS -0.3V to +7.0V

Note: Stresses above those listed may cause permanent damage to the device. Exposure to the absolute
maximum ratings may affect device reliability and performance. Functional operation is not implied at these
conditions.

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9.1. OPERATING CONDITIONS

TABLE 7: OPERATING CONDITIONS (PACKAGED PARTS)

CONDITIONS VALUES
Commercial operating temperature range (Case temperature) 0°C to +70°C
Extended operating temperature (Case temperature) -20°C to +70°C
Industrial operating temperature (Case temperature) -40°C to +85°C
[1]
Supply voltage (VCC) +2.7V to +3.3V
[2]
Ground voltage (VSS) 0V

TABLE 8: OPERATING CONDITIONS (DIE)

CONDITIONS VALUES
Commercial operating temperature range 0°C to +50°C
[1]
Supply voltage (VCC) +2.7V to +3.3V
[2]
Ground voltage (VSS) 0V

[1]
VCC = VCCA = VCCD
[2]
VSS = VSSA = VSSD

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10. ELECTRICAL CHARACTERISTICS

10.1. PARAMETERS FOR PACKAGED PARTS

TABLE 9: DC PARAMETERS
PARAMETERS SYMBOLS MIN[2] TYP[1] MAX[2] UNITS CONDITIONS
Input Low Voltage VIL VCC x 0.2 V
Input High Voltage VIH VCC x 0.8 V
Output Low Voltage VOL 0.4 V IOL = 10 µA

RAC, INT Output Low VOL1 0.4 V IOL = 1 mA

Voltage
Output High Voltage VOH VCC - 0.4 V IOH = -10 µA
VCC Current (Operating) ICC
- Playback 15 30 mA REXT = ∞ [3]
- Record 25 40 mA REXT = ∞ [3]
[3] [4]
VCC Current (Standby) ISB 1 10 µA
Input Leakage Current IIL ±1 µA
MISO Tristate Current IHZ 1 10 µA
Output Load Impedance REXT 5 KΩ
ANA IN+ Input Resistance RANA IN+ 2.2 3.0 3.8 KΩ
ANA IN- Input Resistance RANA IN- 40 56 71 KΩ
ANA IN+ or ANA IN- to AUD AARP 23 dB 32 mVpp 1 KHz
OUT Gain sinewave input [5]

Notes:
[1]
Typical values @ TA = 25°C and VCC = 3.0V.
[2]
All Min/Max limits are guaranteed by Winbond via electronical testing or characterization. Not all
specifications are 100 percent tested.
[3]
VCCA and VCCD connected together.
[4]
SS = VCCA = VCCD, XCLK = MOSI = VSSA = VSSA and all other pins floating.
[5]
Measured with AutoMute feature disabled.

- 22 -
 ISD4003 SERIES

TABLE 10: AC PARAMETERS (Packaged Parts)

[2] [1] [2]
CHARACTERISTIC SYMBOLS MIN TYP MAX UNITS CONDITIONS
Sampling Frequency FS
[5]
ISD4003-04M 8.0 KHz
[5]
ISD4003-05M 6.4 KHz
[5]
ISD4003-06M 5.3 KHz
[5]
ISD4003-08M 4.0 KHz
Filter Pass Band FCF
[3][7]
ISD4003-04M 3.4 KHz 3 dB Roll-Off Point
[3][7]
ISD4003-05M 2.7 KHz 3 dB Roll-Off Point
[3][7]
ISD4003-06M 2.3 KHz 3 dB Roll-Off Point
[3][7]
ISD4003-08M 1.7 KHz 3 dB Roll-Off Point
Record Duration TREC
[6]
ISD4003-04M 4 min
[6]
ISD4003-05M 5 min
[6]
ISD4003-06M 6 min
[6]
ISD4003-08M 8 min
Playback Duration TPLAY
[6]
ISD4003-04M 4 min
[6]
ISD4003-05M 5 min
[6]
ISD4003-06M 6 min
[6]
ISD4003-08M 8 min
Power-Up Delay TPUD
ISD4003-04M 25 msec
ISD4003-05M 31.25 msec
ISD4003-06M 37.5 msec
ISD4003-08M 50 msec
Stop or Pause in Record or Play TSTOP or TPAUSE
ISD4003-04M 50 msec
ISD4003-05M 62.5 msec
ISD4003-06M 75 msec
ISD4003-08M 100 msec
RAC Clock Period TRAC
[10]
ISD4003-04M 200 msec
[10]
ISD4003-05M 250 msec
[10]
ISD4003-06M 300 msec
[10]
ISD4003-08M 400 msec
RAC Clock Low Time TRACL
ISD4003-04M 25 msec
ISD4003-05M 31.25 msec
ISD4003-06M 37.5 msec
ISD4003-08M 50 msec
RAC Clock Period in Message TRACM
Cueing Mode
ISD4003-04M 125 µsec
ISD4003-05M 156.3 µsec
ISD4003-06M 187.5 µsec
ISD4003-08M 250 µsec
RAC Clock Low Time in TRACML
Message Cueing Mode
ISD4003-04M 15.63 µsec
ISD4003-05M 19.53 µsec
ISD4003-06M 23.44 µsec
ISD4003-08M 31.25 µsec
Total Harmonic Distortion THD 1 2 % 32 mVpp 1 KHz
[11]
sinewave input
[4] [8] [9]
ANA IN Input Voltage VIN 32 mV Peak-to-Peak

Publication Release Date: January 2004

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 ISD4003 SERIES

Notes:
[1]
Typical values @ TA = 25°C, VCC = 3.0V and timing measurement at 50%.
[2]
All Min/Max limits are guaranteed by Winbond via electrical testing or characterization. Not all
specifications are 100 percent tested.
[3]
Low-frequency cutoff depends upon the value of external capacitors (see Pin Descriptions)
[4]
Single-ended input mode. In the differential input mode, VIN maximum for ANA IN+ and ANA IN- is 16
mVp-p.
[5]
Sampling Frequency can vary as much as ±2.25 percent over the commercial temperature and voltage
ranges, and –6/+4 percent over the extended temperature, industrial temperature and voltage ranges.
For greater stability, an external clock can be utilized (see Pin Descriptions)
[6]
Playback and Record Duration can vary as much as ±2.25 percent over the commercial temperature and
voltage ranges, and –6/+4 percent over the extended temperature, industrial temperature and voltage
ranges. For greater stability, an external clock can be utilized (see Pin Descriptions)
[7]
Filter specification applies to the antialiasing filter and the smoothing filter. Therefore, from input to
output, expect a 6 dB drop by nature of passing through both filters.
[8]
The typical output voltage will be approximately 450 mVp-p with VIN at 32 mVp-p.
[9]
For optimal signal quality, this maximum limit is recommended.
[10]
When a record command is sent, TRAC = TRAC + TRACL on the first row address.
[11]
Measured with AutoMute feature disabled.

- 24 -
 ISD4003 SERIES

10.2. PARAMETERS FOR DIE

TABLE 11: DC PARAMETERS
[6]
PARAMETERS SYMBOLS MIN[2] TYP[1] MAX[2] UNITS CONDITIONS
Input Low Voltage VIL VCC x 0.2 V
Input High Voltage VIH VCC x 0.8 V
Output Low Voltage VOL 0.4 V IOL = 10 µA

RAC, INT Output Low VOL1 0.4 V IOL = 1 mA

Voltage
Output High Voltage VOH VCC - 0.4 V IOH = -10 µA
Operating Current ICC
-Playback 15 30 mA REXT = ∞ [3]
-Record 25 40 mA REXT = ∞ [3]
[3] [4]
Standby Current ISB 1 10 µA
Total Harmonic Distortion THD 1 2 % 32 mVpp 1 KHz
sinewave input [5]
ANA IN+ or ANA IN- to AUD AARP 23 dB 32 mVpp 1 KHz
OUT Gain sinewave input [5]

Notes:
[1]
Typical values @ TA = 25°C and VCC = 3.0V. Sampling Frequency can vary as much as ±2.25 percent
over the commercial temperature and voltage ranges
[2]
All Min/Max limits are guaranteed by Winbond via electrical testing or characterization. Not all
specifications are 100 percent tested.
[3]
VCCA and VCCD connected together.
[4]
SS = VCCA = VCCD, XCLK = MOSI = VSSA = VSSA and all other pins floating.
[5]
Measured with AutoMute feature disabled.
[6]
The test coverage for die is limited to room temperature testing. The test conditions may differ from that
of packaged parts.

Publication Release Date: January 2004

- 25 - Revision 1.0
 ISD4003 SERIES

10.3. SPI AC PARAMETERS

TABLE 12: AC PARAMETERS[1]
PARAMETER SYMBOL MIN TYP MAX UNITS CONDITIONS

SS Setup Time TSSS 500 nsec

SS Hold Time TSSH 500 nsec

Data in Setup Time TDIS 200 nsec

Data in Hold Time TDIH 200 nsec
Output Delay TPD 500 nsec
[2]
Output Delay to HighZ TDF 500 nsec

SS HIGH TSSmin 1 µsec

SCLK High Time TSCKhi 400 nsec

SCLK Low Time TSCKlow 400 nsec
CLK Frequency F0 1,000 KHz

Notes:
[1]
Typical values @ TA = 25°C, VCC = 3.0V and timing measurement at 50%.
[2]
Tri-state test condition.

VCC

6.32KΩ
MISO

10.91KΩ
50pF (Includes scope and fixture capacitance)

- 26 -
 ISD4003 SERIES

11. TYPICAL APPLICATION CIRCUIT

These application examples are for illustration purposes only. Winbond makes no representation or
warranty that such application will be suitable for production.
Make sure all bypass capacitors are as close as possible to the package.

C9 C8
15-30 pF 15-25 pF

VCC
U2 U1
39 OCS1 PD0/RDI 29 3 MISO VCCD 27
R7
C2 0.22µ F
10 KΩ 38 OCS2 PD1/TD0 30 2 MOSI VSSD 4
PD2/MISO 31 28 SCLK
C1
1 RESET PD3/MOSI 32 1 SS 47 µ F
2 IRQ PD4/SCK 33

PD5/SS 34 VCCA 18
C3 0.22µ F
VSSA 23
37 TCAP PC0 28 VSSA 12
PC1 27 C11 VSSA 11 C4
0.1 µ F 1 µF J1
PC2 26 16 ANA IN- AUD OUT 13 3

PC3 25 ISD4003 2
4
LINE OUT
35 TCMP PC4 24 C10 5
0.1 µ F R2 1
PC5 23 17 ANA IN+ 1M
VCC 22 R1
68HC705C8PPC6 10K
PC7 21 24 RAC
AM CAP 14
R4

R6 PB0 12 25 INT R3 100

1
100K POT
C5 3
47 KΩ PB1 13 1µF
11 PA0 PB2 14 26 XCLK U3 2

13 -IN GAIN-OUT 11
10 PA1 PB3 15 J4
3
V01 10
9 PA2 PB4 16 14 +IN 2
EXT
4
8 PA3 PB5 17 SPEAKER
VCC PDIP / SOIC 5 BYPASS
V02 15 5
7 PA4 PB6 18 1

6 C6 6 HP-IN1 VDD 12
PA5 PB7 19 C7
1µ F 7 HP-IN2
GND 1 .1µ F
5 PA6
3 HPSENSE GND 4
R5
4 PA7 GND 8
47 KΩ 2 SHUTDOWN
GND 9
PD7
GND 16

LM4860M

FIGURE 9: APPLICATION EXAMPLE USING SPI

Publication Release Date: January 2004

- 27 - Revision 1.0
 ISD4003 SERIES

VCC
U2 U1

D3 22 3 MISO VCCD 27
23 GND C2 0.22µ F
D2 21 2 MOSI VSSD 4
D1 20 28 SCLK C1
47 µ F
D0 19 1 SS

G3 28

27 VCCA 18
24 RESET G2
C3 0.22µ F
26 VSSA 23
G1

INT 25 VSSA 12

SI 3 VSSA 11 C4
C9
0.1 µ F 1 µF
VCC SK 2 16 ANA IN- AUD OUT 13 3 J1
2
4
COP 820C G7
ISD4003 4
LINE OUT
5
6 VCC SO 1 1
C8 R2
0.1 µ F 1M
L7 18 17 ANA IN+ R1
17 10K
L6
R7 R4
3.3 K Ω L5 16 24 RAC R3 100
AM CAP 14 100K POT
1
5 CLI L4 15 3

7 10 14 C5 U3 2
L3 25 INT 1µF
13 -IN GAIN-OUT 11
8 11 L2 13 3 J4
V01 10
C10 14 +IN 2
9 12 L1 12 EXT
82 pF VCC 4
VCC 26 XCLK 15
SPEAKER
V02 5
10 13 L0 11 5 BYPASS
1

R6 C6 6 HP-IN1 VDD 12
1µF 7 HP-IN2 C7
4.7 KΩ R5 1
GND .1µ F
4.7 KΩ 3 4
HPSENSE GND
PDIP / SOIC 8
GND
2 SHUTDOWN
GND 9
GND 16

LM4860M

FIGURE 10: APPLICATION EXAMPLE USING MICROWIRE

- 28 -
 ISD4003 SERIES

VCC
U2 U1

D3 22 3 MISO VCCD 27
23 GND C2 0.22µ F
D2 21 2 MOSI VSSD 4
D1 20 28 SCLK C1
47 µ F
D0 19 1 SS

G3 28

27 VCCA 18
24 RESET G2
C3 0.22µ F
26 VSSA 23
G1

INT 25 VSSA 12

SI 3 VSSA 11 C4
C9
0.1 µ F 1 µF
VCC SK 2 16 ANA IN- AUD OUT 13 3 J1
2
4
COP 820C G7
ISD4003 4
LINE OUT
5
6 VCC SO 1 1
C8 R2
0.1 µ F 1M
L7 18 17 ANA IN+ R1
17 10K
L6
R7 R4
3.3 K Ω L5 16 24 RAC R3 100
AM CAP 14 100K POT
1
5 CLI L4 15 3

7 10 14 C5 U3 2
L3 25 INT 1µF
13 -IN GAIN-OUT 11
8 11 L2 13 3 J4
V01 10
C10 14 +IN 2
9 12 L1 12 EXT
82 pF VCC 4
VCC 26 XCLK 15
SPEAKER
V02 5
10 13 L0 11 5 BYPASS
1

R6 C6 6 HP-IN1 VDD 12
1µF 7 HP-IN2 C7
4.7 KΩ R5 1
GND .1µ F
4.7 KΩ 3 4
HPSENSE GND
PDIP / SOIC 8
GND
2 SHUTDOWN
GND 9
GND 16

LM4860M

FIGURE 11: APPLICATION EXAMPLE USING SPI PORT ON MICROCONTROLLER

Publication Release Date: January 2004

- 29 - Revision 1.0
 ISD4003 SERIES

12. PACKAGING AND DIE INFORMATION

12.1. 28-LEAD 300-MIL PLASTIC SMALL OUTLINE IC (SOIC)

28 27 26 25 24 23 22 21 20 19 18 17 16 15

1 2 3 4 5 6 7 8 9 10 11 12 13 14

A
G
C

B
D

E F H

INCHES MILLIMETERS
Min Nom Max Min Nom Max
A 0.701 0.706 0.711 17.81 17.93 18.06
B 0.097 0.101 0.104 2.46 2.56 2.64
C 0.292 0.296 0.299 7.42 7.52 7.59
D 0.005 0.009 0.0115 0.127 0.22 0.29
E 0.014 0.016 0.019 0.35 0.41 0.48
F 0.050 1.27
G 0.400 0.406 0.410 10.16 10.31 10.41
H 0.024 0.032 0.040 0.61 0.81 1.02

Note: Lead coplanarity to be within 0.004 inches.

- 30 -
 ISD4003 SERIES

12.2. 28-LEAD 600-MIL PLASTIC DUAL INLINE PACKAGE (PDIP)

INCHES MILLIMETERS
Min Nom Max Min Nom Max
A 1.445 1.450 1.455 36.70 36.83 36.96
B1 0.150 3.81
B2 0.065 0.070 0.075 1.65 1.78 1.91
C1 0.600 0.625 15.24 15.88
C2 0.530 0.540 0.550 13.46 13.72 13.97
D 0.19 4.83
D1 0.015 0.38
E 0.125 0.135 3.18 3.43
F 0.015 0.018 0.022 0.38 0.46 0.56
G 0.055 0.060 0.065 1.40 1.52 1.62
H 0.100 2.54
J 0.008 0.010 0.012 0.20 0.25 0.30
S 0.070 0.075 0.080 1.78 1.91 2.03
q 0° 15° 0° 15°

Publication Release Date: January 2004

- 31 - Revision 1.0
 ISD4003 SERIES

12.3. 28-LEAD 8X13.4MM PLASTIC THIN SMALL OUTLINE PACKAGE (TSOP) TYPE 1

A
A
B
B G
G
1 28
28
22 27
27
33 26
26
44 25
25
55 24
24 F
66 23
23
77 22
22
88 21
21 C
99 20
20
10
10 19
19
11
11 18
18
12
12 17
17
13
13 16
16
14
14 15
15 E
E

H
H JJ
I

INCHES MILLIMETERS
Min Nom Max Min Nom Max
A 0.520 0.528 0.535 13.20 13.40 13.60
B 0.461 0.465 0.469 11.70 11.80 11.90
C 0.311 0.315 0.319 7.90 8.00 8.10
D 0.002 0.006 0.05 0.15
E 0.007 0.009 0.011 0.17 0.22 0.27
F 0.0217 0.55
G 0.037 0.039 0.041 0.95 1.00 1.05
H 0° 3° 6° 0° 3° 6°
I 0.020 0.022 0.028 0.50 0.55 0.70
J 0.004 0.008 0.10 0.21

Note: Lead coplanarity to be within 0.004 inches.

- 32 -
 ISD4003 SERIES

12.4. DIE INFORMATION

ISD4003 Series
o Die Dimensions (with scribe line) [1]
X: 166.6 ± 1 mils VSSD
MOSI SCLK VCCD
INT RAC
MISO SS VCCD XCLK
Y: 274.9 ± 1 mils
VSSD VSSA

o Die Thickness [2]

11.5 ± 0.5 mils

o Pad Opening
Single pad: 90 x 90 microns
Double pad: 180 x 90 microns ≈ ISD4003
≈

VSSA[3] [3]
VSSA
AUD OUT ANA IN- VCCA [3]
VSSA[3] AM CAP ANA IN+ VCCA

Notes:
[1]
The backside of die is internally connected to VSS. It MUST NOT be connected to any other potential or
damage may occur.
[2]
Die thickness is subject to change, please contact Winbond as this thickness may change in the future.
[3]
Double bond is recommended if treated as one pad.

Publication Release Date: January 2004

- 33 - Revision 1.0
 ISD4003 SERIES

ISD4003 SERIES PAD COORDINATIONS

(with respect to die center)

Pad Pad Description X Axis (µm) Y Axis (µm)

VSSA Analog Ground 1885.2 3273.7
RAC Row Address Clock 1483.8 3273.7

INT Interrupt 794.8 3273.7

XCLK External Clock Input 564.8 3273.7

VCCD Digital Power Supply 384.9 3273.7
VCCD Digital Power Supply 169.5 3273.7
SCLK Slave Clock -14.7 3273.7

SS Slave Select -198.1 3273.7

MOSI Master Out Slave In -1063.7 3273.7

MISO Master In Slave Out -1325.6 3273.7
VSSD Digital Ground -1665.3 3273.7
VSSD Digital Ground -1836.9 3273.7
[1]
VSSA Analog Ground -1943.1 -3272.4
[1]
VSSA Analog Ground -1853.1 -3272.4
VSSA Analog Ground -1599.9 -3272.4
AUD OUT Audio Output 281.9 -3272.4
AM CAP AutoMute 577.3 -3272.4
ANA IN- Inverting Analog Input 1449.3 -3272.4
ANA IN+ Noninverting Analog Input 1603.5 -3272.4
[1]
VCCA Analog Power Supply 1853.7 -3272.4
[1]
VCCA Analog Power Supply 1943.7 -3272.4

Note:
[1]
Double bond recommended if treated as one pad.

- 34 -
 ISD4003 SERIES

13. ORDERING INFORMATION

ISD4003-

Product Family : Special Temperature Field :

ISD4000 Family Blank = Commercial Package (0°C to + 70°C)
or Commercial Die (0°C to + 50°C)
Product Series : D = Extended (-20°C to + 70°C)
03 = Third Series (4-8 min) I = Industrial (-40°C to + 85°C)

Duration : Packaged Units / Die :

04M = 4 minutes X = Die
05M = 5 minutes P = 28-Lead 600-mil Plastic Dual Inline
Package (PDIP)
06M = 6 minutes
S = 28-Lead 300-mil Plastic Small Outline
08M = 8 minutes
Package (SOIC)
E = 28-Lead 8x13.4mm Plastic Thin Small
Outline Package (TSOP) Type 1

When ordering ISD4003 Series devices, please refer to the following valid part numbers.

Die / Package Part Number

Die ISD4003-04MX ISD4003-05MX ISD4003-06MX ISD4003-08MX
PDIP ISD4003-04MP ISD4003-05MP ISD4003-06MP ISD4003-08MP
SOIC ISD4003-04MS ISD4003-05MS ISD4003-06MS ISD4003-08MS
ISD4003-04MSI ISD4003-05MSI ISD4003-06MSI ISD4003-08MSI
TSOP ISD4003-04ME ISD4003-05ME ISD4003-06ME ISD4003-08ME
ISD4003-04MED ISD4003-05MED ISD4003-06MED ISD4003-08MED
ISD4003-04MEI ISD4003-05MEI ISD4003-06MEI ISD4003-08MEI

For the latest product information, access Winbond worldwide website at http://www.winbond-usa.com

Publication Release Date: January 2004

- 35 - Revision 1.0
 ISD4003 SERIES

14. VERSION HISTORY

VERSION DATE DESCRIPTION
0 June 2000 Initial version
1.0 Jan. 2004 Reformat the document.
Add note for typical filter pass band.
Add memory architecture description.
Remove all CSP info.
Revise RAC timing parameter for MC.
Revise AutoMute: playback only.
Revise SPI, opcodes sections, record & playback steps.
Rename TRACLO to TRACL.
Revise AARP parameter.
Revise DC & AC parameters tables for die.
Revise die: (x,y) coordinates.
Figures 9-11: revise VCCA and VCCD pin #.
Revise Ordering Information.

- 36 -
 ISD4003 SERIES

The contents of this document are provided only as a guide for the applications of Winbond products. Winbond
makes no representation or warranties with respect to the accuracy or completeness of the contents of this
publication and reserves the right to discontinue or make changes to specifications and product descriptions at
any time without notice. No license, whether express or implied, to any intellectual property or other right of
Winbond or others is granted by this publication. Except as set forth in Winbond's Standard Terms and
Conditions of Sale, Winbond assumes no liability whatsoever and disclaims any express or implied warranty of
merchantability, fitness for a particular purpose or infringement of any Intellectual property.

Winbond products are not designed, intended, authorized or warranted for use as components in systems or
equipments intended for surgical implantation, atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other
applications intended to support or sustain life. Furthermore, Winbond products are not intended for applications
wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe
property or environmental injury could occur.
Application examples and alternative uses of any integrated circuit contained in this publication are for illustration
only and Winbond makes no representation or warranty that such applications shall be suitable for the use
specified.
ISD® and ChipCorder® are trademarks of Winbond Electronics Corporation.
The 100-year retention and 10K record cycle projections are based upon accelerated reliability tests, as published
in the Winbond Reliability Report, and are neither warranted nor guaranteed by Winbond. This product
incorporates SuperFlash® technology licensed from SST.
® ®
Information contained in this ISD ChipCorder data sheet supersedes all data for the ISD ChipCorder products
®
published by ISD prior to August, 1998.
® ®
This data sheet and any future addendum to this data sheet is(are) the complete and controlling ISD ChipCorder
product specifications. In the event any inconsistencies exist between the information in this and other product
documentation, or in the event that other product documentation contains information in addition to the information
in this, the information contained herein supersedes and governs such other information in its entirety.
Copyright© 2003, Winbond Electronics Corporation. All rights reserved. ChipCorder® ISD® are registered
trademark of Winbond. All other trademarks are properties of their respective owners.

Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.

No. 4, Creation Rd. III 2727 North First Street, San Jose, 27F, 299 Yan An W. Rd. Shanghai,
Science-Based Industrial Park, CA 95134, U.S.A. 200336 China
Hsinchu, Taiwan TEL: 1-408-9436666 TEL: 86-21-62365999
TEL: 886-3-5770066 FAX: 1-408-5441797 FAX: 86-21-62356998
FAX: 886-3-5665577 http://www.winbond-usa.com/
http://www.winbond.com.tw/

Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd.
9F, No. 480, Pueiguang Rd. 7F Daini-ueno BLDG. 3-7-18 Unit 9-15, 22F, Millennium City,
Neihu District Shinyokohama Kohokuku, No. 378 Kwun Tong Rd.,
Taipei, 114 Taiwan Yokohama, 222-0033 Kowloon, Hong Kong
TEL: 886-2-81777168 TEL: 81-45-4781881 TEL: 852-27513100
FAX: 886-2-87153579 FAX: 81-45-4781800 FAX: 852-27552064

Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.

Publication Release Date: January 2004

- 37 - Revision 1.0