Introduction Microprocessor Architecture Data Path and Address Map NVIC and Bus System Memory and Peripherals

Microprocessor Systems

Cortex-M Architecture

University of Engineering and Technology Lahore

Introduction Microprocessor Architecture Data Path and Address Map NVIC and Bus System Memory and Peripherals

Contents
1 Introduction

2 Microprocessor Architecture

ARM ISA and Register Set

Processor Operating Modes

3 Data Path and Address Map

4 NVIC and Bus System

5 Memory and Peripherals

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Introduction Microprocessor Architecture Data Path and Address Map NVIC and Bus System Memory and Peripherals

Families of ARM Architectures

Processor
Family ARM7TDMI ARM9E ARM11, Cortex-M0, Cortex-M1 Cortex-M, Cortex-R, Cortex-A

Cortex-M3/M4,
ARM1136, Cortex-R4, Cortex-
1176, A8
1156T2
Processor
Cores
ARM926, 946, Cortex-M0,
966, Cortex-M1
ARM7TDMI, Intel XScale (FPGA)
920T,
Intel StrongARM

Architecture
ARMv4/v4T ARMv5/v5E ARMv6 ARMv7
Version

Figure: Different versions of ARM processor architecture and their

evolution.

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ARM Processor Profiles

• Cortex-M profile: Processors in this profile are designed for

microcontroller-based embedded systems.
• Cortex-A profile: This profile is aimed for addressing the high
performance applications mainly covering the cellular market.
• Cortex-R profile: Addressing the demands of real-time
applications is the main motive of this profile.

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Microcontroller Architecture

The ARM Cortex-M based microcontroller architecture usually

integrates the following key building blocks:
1. Microprocessor core
2. Nested vectored interrupt controller
3. Bus system and bus matrix
4. Memory and peripherals
5. Debug system

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Microcontroller Architecture
Microprocessor Core
(Cortex-M4/M3) Debug
NVIC
Interface
Instruction Data
SysTick

Bus Matrix

Developed by ARM

Peripherals
Memory

I/Os

Developed by ARM
or Chip Manufacturers

Figure: Block diagram of ARM Cortex-M based microcontroller

architecture.

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ARM Cortex-M

Cortex-M3
Cortex-M4

DSP Instructions Cortex-M4F

Floating Point Unit

(FPU)

Figure: Architectural differences between Cortex-M3 and Cortex-M4

microprocessor cores.

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Key Components of Processor Core

The Cortex-M3 based microprocessor core includes the following

key components and the associated features.
• Instruction Set Architecture (ISA)
• Register Set
• Processor Operating Modes
• Interrupts and Processor Reset Sequence
• Pipelined Architecture and Data Path
• Memory Address Map

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ARM ISA

Thumb2 Instruction Set

(16-bit and 32-bit)

Cortex-M3
(ARMv7-M) Thumb Instructions
(16-bit)

Figure: The relationship between ARMv7-M Instruction Set Architecture

(ISA) with Thumb2 and the traditional Thumb.

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ARM ISA Cont’d

• ARM processors have supported two different instruction sets:
the ARM instructions that are 32 bits and Thumb instructions
that are 16 bits.
• ARM ISA has, in general, better execution performance, while
Thumb ISA has higher code density.
• Thumb2 is a superset of the Thumb instruction set. Thumb2
introduces 32-bit instructions that are intermixed with the
16-bit instructions.
• Thumb2 instruction set gives approximately 26% improvement
in code density compared to ARM and approximately 25%
performance gain over the conventional 16-bit only Thumb
architecture.

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ARM ISA Cont’d

100 100

80 80
Processing Speed

Memory Usage
60 60

40 40

20 20

0 0
ARM Thumb-2 Thumb ARM Thumb-2 Thumb

Figure: Performance comparison of Thumb2 instruction set with the

conventional Thumb and ARM architectures.

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Register Set
• General-purpose registers, R0-R12
1. Registers R0-R7 are called low registers.
2. Registers R8-R12 are called high registers (not accesible by any
THUMB instruction).
• Stack Pointer (SP): Register R13 is used as the Stack Pointer
(SP). It is a banked register with two copies, namely Main
Stack Pointer (MSP) and Process Stack Pointer (PSP).
• Link Register (LR): Register R14 is the subroutine Link
Register (LR).
• Program Counter (PC): Register R15 is called the program
counter register. PC contains the current program or
instruction address that is to be executed.

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Register Set Cont’d

R0 R8

R1 R9

R2 R10 General-purpose High registers

R3 R11
General-purpose
Low registers
R4 R12

R13(MSP) R13(PSP) Main stack pointer (MSP),

R5
Process stack pointer (PSP)
R6 R14 Link register (LR)

R7 R15 Program counter (PC)

Figure: General purpose along with some special purpose registers. All of
the registers are 32-bit.

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Register Set Cont’d

• Program Status Registers (PSRs): This set of registers

consists of the following three status registers:
1. Application Program Status Register (APSR)
2. Interrupt Program Status Register (IPSR)
3. Execution Program Status Register (EPSR)
• Control register (CONTROL): The control register is used to
configure the privilege level as well as to perform the selection
of stack pointer register.

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Register Set Cont’d

31 30 29 28 27 26:25 24 23:20 19:16 15:10 9 8 7 6 5 4:0

APSR N Z C V Q

IPSR Exception number

EPSR ICI/IT T ICI/IT

Figure: Program status registers and their bit field allocations.

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Register Set Cont’d

Table: Bit field definitions for different program status registers.

Bit field Description

N Negative flag.
Z Zero flag.
C Carry flag.
V Overflow flag.
Q Saturation flag.
ICI/IT Interrupt continuable instruction (ICI) bits. IF-THEN instruc-
tion block status bit.
T Thumb state (always 1 in case of Cortex-M processor using
Thumb2 ISA).
Exception Shows which exception number is being handled by the pro-
number cessor.

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Register Set Cont’d

Table: Control register bit field definitions.

Bit field Description

CONTROL-Bit1 When this bit is set to 0, main stack is used (through main
stack pointer (MSP) register) and is the default setting.
Setting this bit to 1 results in the use of process stack
(through process stack pointer (PSP) register).
CONTROL-Bit0 When this bit is 0 thread mode is privileged and setting
it to 1 makes thread mode switch to unprivileged (user)
level.

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RISC-V Register Set

• 32 registers, 32 bit each. Can be referred as x0, x1, x2, ... ,

x31.
• x0 is hard wired to zero
• x1 holds the return address (link register)
• RISC V architecture has a large collection of control and
status registers (CSRs)
• The register file (implementing the register set) usually has
dual read port and single write port

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RISC-V Register Set Cont’d

Figure: Write port indexed via RW on falling edge when WE=1. Read
ports indexed via RA, RB

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Processor Operating Modes

The processor supports two modes of operation, Thread mode and

Handler mode. These modes of operation have an associated pair
of access levels namely Privileged and Unprivileged (user) access
levels.
• Thread Mode: The processor enters Thread mode on reset or
as a result of an exception return. Code execution in thread
mode can have either privileged or unprivileged (user) access
levels.
• Handler Mode: The processor enters Handler mode as a result
of an exception. All code is privileged in handler mode.

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Processor Operating Modes

Exception exit &

CONTROL-Bit0 = 0
Handler Mode
(Privileged always)
Exception
Reset
Thread Mode
(Privileged) Exception exit &
Exception
CONTROL-Bit0 = 1

Thread Mode
CONTROL-Bit0 (Unprivileged or User)
0→1

Figure: Possible transitions for operating modes and privilege levels.

Operating System
(Privileged & Main Stack)
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Thread
CONTROL-Bit0 (Unprivilege
0→1

Processor Operating Modes

Operating System
(Privileged & Main Stack)

System Calls Application Program

Interface (API)

User Application
(Unprivileged & Process
Stack)

Figure: Selection of privilege level and stack between operating system

and user application program.

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Processor Operating Modes

Table: Control register bit combinations and their possible usage.

CONTROL- CONTROL- Description

Bit0 Bit1
0 0 For simple applications, where the en-
tire program runs at privileged level
and only the Main Stack Pointer
(MSP) is used.
0 1 When the user application program
runs, in privileged thread mode, on
top of an embedded operating system.
The user application uses PSP, while
the MSP is used by the operating sys-
tem kernel and exception or interrupt
handlers.

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Processor Operating Modes

Table: Control register bit combinations and their possible usage.

CONTROL- CONTROL- Description

Bit0 Bit1
1 0 The user application is running with
unprivileged access level and still uses
MSP. It is highly unlikely scenario.
1 1 In this case the user application pro-
gram runs, in unprivileged thread
mode, on top of an embedded operat-
ing system. The user application uses
PSP, while the MSP is used by the op-
erating system kernel and exception or
interrupt handlers.

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Processor Interrupt Response Sequence

The processor response involves the following sequence of

operations in case of an interrupt or exception:
• When an event occurs, an interrupt request is generated to
the processor.
• The processor suspends current task execution in response to
the interrupt and starts executing an interrupt service routine
to generate the response to the event.
• Once the response to the event is completed, the processor
resumes execution of the suspended task.

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Processor Reset Sequence

The Cortex-M processor response involves the following sequence

of operations on reset:
• Address 0x00000000: This address in the code memory
contains the starting value that is loaded to the main stack
pointer, MSP (R13).
• Address 0x00000004: Reset vector is contained at this address
and the program counter is loaded with this value to jump to
the reset interrupt service routine.

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Data Path

The Cortex-M3 processor has a three-stage pipeline. The pipeline

stages are
1. Instruction Fetch.
2. Instruction Decode.
3. Instruction Execute.

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Data Path Cont’d

Sequence
Execution Fetch Decode Execute Instruction 1
Sequence
Execution
Fetch Decode Execute Instruction 1
Fetch Decode Execute Instruction 2
Fetch Decode Execute Instruction 2

(a)
Fetch Decode Execute Instruction 1
Execution Sequence

Fetch Decode Execute Instruction 1

Execution Sequence

Fetch Decode Execute Instruction 2

Fetch Decode Execute Instruction 2
Fetch Decode Execute Instruction 3
Fetch Decode Execute Instruction 3
Fetch Decode Execute Instruction 4
Fetch Decode Execute Instruction 4

Processor clock cycles

Processor clock cycles
(b)
Figure: Comparison between non-pipelined and pipelined architectures.
(a) Non-pipelined architecture and (b) three stage pipelined architecture.

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Data Path Cont’d

Write Data
Register DBus-Data
IBUS-Data
Bidirectional
Instruction
Mux
Decode Read data
register

Register
Bank Barrel
Mul/Div
Shifter

ALU
Address
incrementer A

Address
Register
Write Back
IBUS-Address
Address
Incrementer
INT-Address

Address
Register
DBus-Address

Figure: Processor data path.

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Example RISC-V Data Path

An example five stage pipelined datapath for RISC-V Processor has

the following stages:
1. Instruction Fetch
2. Decode
3. Execute
4. Memory Access
5. Register Writeback

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Example RISC-V Data Path Cont’d

The figure is taken from [Patterson and Hennessy, 2016].

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Memory Address Map

Vendor Specific
0xE0100000
External Private Peripheral Bus (EPPB)
0xE0040000
Internal Private Peripheral Bus (IPPB)
0xE0000000

External Peripherals

0xA0000000

External Memory (RAM)

0x60000000

Peripherals
0x40000000

SRAM
0x20000000

Code Memory (Flash/EEPROM)

0x00000000

Figure: Predefined memory map model for Cortex-M3.

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Memory Address Map Cont’d

• Code region for storing program or code.
• Data region for application data.
• Peripheral region hosts different input and output peripherals.
• External memory and peripheral region, through a bus
interface, can have access to external memory or peripherals.
• Private Peripheral Bus (PPB) region is meant for debug
interfaces. This address space also hosts the registers for the
NVIC, processor’s configuration registers, and registers for
debug components.
• Vendor specific region contains information about device ID,
versions, release, etc.

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Nested Interrupt Vector Controller

The Nested Vectored Interrupt Controller (NVIC) is closely coupled

to the processor core and provides a number of features as listed
below:
• Nested interrupt support
• Vectored interrupt support
• Dynamic priority change support
• Reduction of interrupt latency
• Interrupt masking

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Bus System and Bus Matrix

Cortex-M3
Nested Interrupt
Vector Controller
Processor Core

External PPB
Bus Matrix (APB) debug
interface
AHB-AP Bus
(DAP)
ICode Bus Dcode Bus System
(AHB) (AHB) Bus (AHB)
System Bus (AHB)
Bus
Multiplexer

On Chip Memory Controller External

SRAM for Offchip SRAM Device AHB
Flash Static RAM Connection to
Memory (Optional) APB
Bridge

Advanced Peripheral Bus (APB)

UART

Timer

Keypad

Digital/
Analog I/O

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Memory and Peripherals

0xFFFFFFFF
System

0xE0100000

External PPB (APB) Debug Components

0xE0040000

INTERNAL PPB SCS + NVIC

0xE0000000

External Peripheral

Instruction
Bus

External RAM
Cortex-M3
Bus Matrix With
Bit-Bander SYSTEM AHB
Aligner Peripherals
Data Bus
Peripheral
RAM
0x20000000
ICODE AHB
Code Space
DCODE AHB
Debug Access 0x00000000
Port (DAP)

ICode & DCode buses addressable space

System bus addressable space

PPB bus addressable space

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Memory Endianness Cont’d

Memory

Address Data

A0 D0 LS Byte

A1 D1

A2 D2

A3 D3 MS Byte

Register

Little Endian Big Endian

(Byte Invariant)
31 16 15 0 31 16 15 0

D3 D2 D1 D0 Word Transfer D0 D1 D2 D3

31 16 15 0 31 16 15 0

D1 D0 Half-Word Transfer D0 D1

31 16 15 0 31 16 15 0

D0 Byte Transfer D0

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Bit Banding
• Each bit in the bit-band region is accessed separately in the
LSB of 32-bit contents at word-aligned bit-band alias address

Bit-band Alias
Bit-band Region Region

x 1 0x23FFFF84
0x200FFFFC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
x 1 0x23FFFF80

...
...

x 0 0x22000090

x 1 0x2200008C

...
0x20000004 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
x 1 0x22000004

0x20000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 x 0 0x22000000

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Stack Implementation in Cortex-M3

• The stack memory is accessed using stack pointers (MSP or

PSP).
• Stack memory can be used to pass parameter or argument
values when a function or subroutine is called.
• Stack is also utilized for declaring any local variables used by a
software function or subroutine.

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Stack Implementation

• The Cortex-M processor uses a full-descending stack operation

model, where the SP points to the largest address when stack
memory is empty.
• Each PUSH/POP operation transfers 4 bytes of data, the SP
decrements/increments by 4 at a time.
• The Cortex-M processor has two SPs: the MSPS and the
PSP. Which of the two stack pointers should be used is
controlled by the control register bit 1 (CONTROL-Bit1).

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Stack Implementation Cont’d

Exception service Ex
Exception service Exception Exception service
Exception routine exit
routine (Handler mode) occurs routine (Handler mode)
occurs

Main Program Main Program Main Program Main

(Thread mode) (Thread mode) (Thread mode) (Thre
Use MSP Use MSP
Use MSP Use MSP Use PSP Use

time time
(a) (a)

...
...
Peripherals Peripherals

0x40000000

SRAM
SRAM
PSP
Process stack region (accessed by PSP)

MSP
Main stack region (Accessed using MSP)
When stack is Main stack region (accessed using MSP)
empty MSP

0x20000000

Code Memory (Flash/EEPROM) Code Memory (Flash/EEPROM)

0x00000000

(b) (b)

Figure: When CONTROL-Bit1 is 0 both thread and handler modes use

main stack.

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Stack Implementation Cont’d

Exception service Exception service
Exception service Exception Exception service
on routine exit routine exit
routine (Handler mode) occurs routine (Handler mode)

ram Main Program Main Program Main Program

ode) (Thread mode) (Thread mode) (Thread mode)
Use MSP Use MSP
SP Use MSP Use PSP Use PSP

time time
(a) (a)

...
...

Peripherals Peripherals

0x40000000 0x40000000

SRAM
SRAM
PSP
Process stack region (accessed by PSP)

Main stack region (Accessed using MSP)

Main stack region (accessed using MSP)
MSP

0x20000000 0x20000000

Code Memory (Flash/EEPROM) Code Memory (Flash/EEPROM)

0x00000000 0x00000000

(b) (b)

Figure: When CONTROL-Bit1=1, thread mode uses process stack and

handler mode uses main stack.

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References

Patterson, D. A. and Hennessy, J. L. (2016).

Computer Organization and Design ARM Edition: The Hardware Software
Interface.
Morgan kaufmann.

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