INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:

• The IC04 LOCMOS HE4000B Logic

Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC

HEF4027B
flip-flops
Dual JK flip-flop
Product specification January 1995
File under Integrated Circuits, IC04
Philips Semiconductors Product specification

HEF4027B
Dual JK flip-flop
flip-flops

DESCRIPTION FUNCTION TABLES

The HEF4027B is a dual JK flip-flop which is INPUTS OUTPUTS
edge-triggered and features independent set direct
(SD), clear direct (CD), clock (CP) inputs and outputs SD CD CP J K O O
(O,O). Data is accepted when CP is LOW, and transferred H L X X X H L
to the output on the positive-going edge of the clock. The L H X X X L H
active HIGH asynchronous clear-direct (CD) and set-direct
H H X X X H H
(SD) are independent and override the J, K, and CP inputs.
The outputs are buffered for best system performance.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times. INPUTS OUTPUTS
SD CD CP J K On + 1 On + 1
L L L L no change
L L H L H L
L L L H L H
L L H H On On

Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
On + 1 = state after clock positive transition

PINNING
J,K synchronous inputs
CP clock input (L to H edge-triggered)
SD asynchronous set-direct input (active HIGH)
CD asynchronous clear-direct input (active HIGH)
O true output
O complement output

Fig.1 Functional diagram. HEF4027BP(N): 16-lead DIL; plastic (SOT38-1)

HEF4027BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF4027BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America

FAMILY DATA, IDD LIMITS category FLIP-FLOPS

See Family Specifications

Fig.2 Pinning diagram.

January 1995 2
Philips Semiconductors Product specification

HEF4027B
Dual JK flip-flop
flip-flops

Fig.3 Logic diagram (one flip-flop).

AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns

VDD TYPICAL EXTRAPOLATION

SYMBOL MIN. TYP. MAX.
V FORMULA
Propagation delays
CP → O, O 5 105 210 ns 78 ns + (0,55 ns/pF) CL
HIGH to LOW 10 tPHL 40 80 ns 29 ns + (0,23 ns/pF) CL
15 30 60 ns 22 ns + (0,16 ns/pF) CL
5 85 170 ns 58 ns + (0,55 ns/pF) CL
LOW to HIGH 10 tPLH 35 70 ns 27 ns + (0,23 ns/pF) CL
15 30 60 ns 22 ns + (0,16 ns/pF) CL
SD → O 5 70 140 ns 43 ns + (0,55 ns/pF) CL
LOW to HIGH 10 tPLH 30 60 ns 19 ns + (0,23 ns/pF) CL
15 25 50 ns 17 ns + (0,16 ns/pF) CL
CD → O 5 120 240 ns 93 ns + (0,55 ns/pF) CL
HIGH to LOW 10 tPHL 45 90 ns 33 ns + (0,23 ns/pF) CL
15 35 70 ns 27 ns + (0,16 ns/pF) CL
SD → O 5 140 280 ns 113 ns + (0,55 ns/pF) CL
HIGH to LOW 10 tPHL 55 110 ns 44 ns + (0,23 ns/pF) CL
15 40 80 ns 32 ns + (0,16 ns/pF) CL

January 1995 3
Philips Semiconductors Product specification

HEF4027B
Dual JK flip-flop
flip-flops

VDD TYPICAL EXTRAPOLATION

SYMBOL MIN. TYP. MAX.
V FORMULA
CD → O 5 75 150 ns 48 ns + (0,55 ns/pF) CL
LOW to HIGH 10 tPLH 35 70 ns 24 ns + (0,23 ns/pF) CL
15 25 50 ns 17 ns + (0,16 ns/pF) CL
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) CL
HIGH to LOW 10 tTHL 30 60 ns 9 ns + (0,42 ns/pF) CL
15 20 40 ns 6 ns + (0,28 ns/pF) CL
5 60 120 ns 10 ns + (1,0 ns/pF) CL
LOW to HIGH 10 tTLH 30 60 ns 9 ns + (0,42 ns/pF) CL
15 20 40 ns 6 ns + (0,28 ns/pF) CL
Set-up time 5 50 25 ns
J,K → CP 10 tsu 30 10 ns
15 20 5 ns
Hold time 5 25 0 ns
J,K → CP 10 thold 20 0 ns
15 15 5 ns
Minimum clock 5 80 40 ns
see also waveforms
pulse width; LOW 10 tWCPL 30 15 ns
Figs 4 and 5
15 24 12 ns
Minimum SD, CD 5 90 45 ns
tWSDH,
pulse width; HIGH 10 40 20 ns
tWCDH
15 30 15 ns
Recovery time 5 20 −15 ns
tRSD,
for SD, CD 10 15 −10 ns
tRCD
15 10 −5 ns
Maximum clock 5 4 8 MHz
see also waveforms
pulse frequency 10 fmax 12 25 MHz
Fig.4
J = K = HIGH 15 15 30 MHz

VDD
TYPICAL FORMULA FOR P (µW)
V
Dynamic power 5 900 fi + ∑ (foCL) × VDD2 where
dissipation per 10 4 500 fi + ∑ (foCL) × VDD2 fi = input freq. (MHz)
package (P) 15 13 200 fi + ∑ (foCL) × VDD2 fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)

January 1995 4
Philips Semiconductors Product specification

HEF4027B
Dual JK flip-flop
flip-flops

Fig.4 Waveforms showing set-up times, hold times and minimum clock pulse width. Set-up and hold times are
shown as positive values but may be specified as negative values.

Fig.5 Waveforms showing recovery times for SD and CD; minimum SD and CD pulse widths.

APPLICATION INFORMATION
Some examples of applications for the HEF4027B are:
• Registers
• Counters
• Control circuits

January 1995 5