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Lab Manual For Half Adder

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Yash Kharote
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133 views

Lab Manual For Half Adder

Uploaded by

Yash Kharote
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EXPERIMENT NO: 10 AIM: TO DESIGN & VERIFY OPERATION OF HALF ADDER &FULL ADDER. APPARATUS REQUIRED: Power supply, IC’s , Digital Trainer, Connecting leads BRIEF THEORY: We are familiar with ALU, which performs all arithmetic and logic operation but ALU doesn’t perforny process decimal no’s. They process binary no’s. Half Adder: It is a logic circuit that adds two bits. It produces the O/P, sum & carry.The Boolean equation for sum & carry are SUM=A+B CARRY = A.B Therefore, sum produces 1 when A&B are different and carry is when A&B are 1. Application of Half adder is limited. Full Adder; It is a logic circuit that can add three bits. It produces two O/P sum & carry. The Boolean Equation for sum & carry are SUM=A+B+C CARRY = AB + (A+B) C ‘Therefore, sum produces one when I/P is containing odd no’s of one & carry is one when there are two or more one in I/P. CIRCUIT DAIGRAM ——- =o | HALF ADDER FULL ADDER PROCEDURE: (a) Comnect the ekt. as shown in fig. For half adder (b) Apply diff. Combination of inputs to the I/P terminal (c) Note O/P for Half adder (@) Repeat procedure for Full wave (2) The result should be in accordance with truth table OBSERVATION TABLE: HALF ADDER: INPUTS OUTPUT A B Ss c 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 i FULL ADDER: INPUTS OUTPUTS A B c s CARRY 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 a RESULT: The Half Adder & Full Adder ckts. are verified. PRECAUTIONS: 1) Make the connections according to the IC pin diagram, 2) The comections should be tight

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