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ES 4 VHDL Reference Sheet: Instantiate A Submodule

This document provides a summary of key concepts in VHDL, including comments, libraries, entity/architecture structure, component instantiation, types, literals, type conversion, processes, sequential logic, conditional statements, case statements, loops, reporting, and file handling. It defines common keywords, syntax, and constructs in VHDL with examples. Concepts covered include ports, signals, generics, port maps, continuous assignments, sensitivity lists, clocks, and testbenches.

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Lap Ngo Doan
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83 views

ES 4 VHDL Reference Sheet: Instantiate A Submodule

This document provides a summary of key concepts in VHDL, including comments, libraries, entity/architecture structure, component instantiation, types, literals, type conversion, processes, sequential logic, conditional statements, case statements, loops, reporting, and file handling. It defines common keywords, syntax, and constructs in VHDL with examples. Concepts covered include ports, signals, generics, port maps, continuous assignments, sensitivity lists, clocks, and testbenches.

Uploaded by

Lap Ngo Doan
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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ES 4 VHDL reference sheet r.2020.04.

03
GRAY_ITALICS represent user-defined names or operations keywords www.ece.tufts.edu/es/4
Purple constructs are only available in VHDL 2008. literals (constants)
-- This is a comment
/* Multi-line comment
(VHDL 2008 only) */
library IEEE;
use IEEE.std_logic_1164.all;
You almost always need these libraries;
use IEEE.numeric_std.all; just put this at the top of every file.

entity ENTITY_NAME is
port(
PORT_NAME : in std_logic; -- Single bit input
ANOTHER : out std_logic_vector(3 downto 0) -- 4-bit output
);
end;
No semicolon on the last one!
Don't forget these semicolons!

architecture ARCH_NAME of ENTITY_NAME is


-- Component declarations, if using submodules
component SUB_ENTITY is Just replace `entity` with `component`
port( and put `end component` at the end.
-- Port list for the entity you're including

Instantiate a submodule
);
end component;
INSTANCE_NAME : MODULE_NAME
-- Signal declarations, if using intermediate signals generic map (
signal NAME : TYPE; GENERIC => CONSTANT,
begin )
-- Architecture definition goes here port map(
end; PORT => VALUE,
ANOTHER => LOCAL_SIGNAL
);
Continuous assignments
RESULT_SIGNAL <= SIGNAL1 and SIGNAL2; Also works for or, not, nand, nor, xor
RESULT_SIGNAL <= '1' when (SIGNAL1 = x"5") else '0'; Note '=' for comparison (not '==')
HIGHEST_BIT <= EIGHT_BIT_VEC(7); Extract a single bit (7 is MSB, 0 is LSB)
TWO_BIT_VEC <= EIGHT_BIT_VEC(3 downto 2); Extract multiple bits
SIX_BIT_VEC <= "000" & EIGHT_BIT_VEC(3 downto 2) & SINGLE_BYTE; Concatenate

Types Literals
std_logic Basic logic type, can take values 0, 1, X, Z (and others) '0', '1', 'X', 'Z'
std_logic_vector (n downto m) Ordered group of std_logic "00001010", x"0c" 8-bit binary, hex
unsigned (n downto m) Like std_logic_vector, but preferred 9x"101" 3b"101" 7d"101"
for numerically meaningful signals 9-bit hex 3-bit binary 7-bit decimal
signed (n downto m)
integer Poor for synthesis, but constants are integers by default 5, 38, 10000000

Type conversion
to_unsigned(INTEGER, WIDTH) Use to_unsigned for unsigned constants before VHDL 2008.
unsigned(LOGIC_VECTOR) (Same things for signed)
std_logic_vector(UNSIGNED)
Process blocks If sensitivity includes:
process (SENSITIVITY) is all↕ Combinational logic Specify all signals by name prior to
begin VHDL 2008
clk↑ Flip-flop / register
-- if/case/print go here
end process; clk↑ + data↕ Latch
Nothing Testbench (repeated evaluation)
Something else Bad things you probably didn't want

Reporting stuff
assert CONDITION report "MESSAGE" severity error; Print message if condition is false
report "MESSAGE" severity error; Severity can be NOTE, WARNING, ERROR, FATAL
"FATAL" ends the simulation

report "A is " & to_string(a); Use image function prior to VHDL 2008
report "A in hex is " & to_hstring(a);
concatenation conversion to string

Writing to files (or stdout)


variable BUF : line; Declare buffer in process block
write(BUF, string'("MESSAGE")); Append message to buffer
writeline(output, BUF); Write buffer to stdout (like report, but just the text)

file RESULTS : text; Declare file handle in process block


file_open(RESULTS, "FILENAME", WRITE_MODE);
writeline(RESULTS, BUF);

If/else Case
if CONDITION then case INPUT_SIGNAL is
SIGNAL <= VALUE1; when VALUE1 => OPERATION1;
elsif OTHER_CONDITION then when VALUE2 => OPERATION2;
SIGNAL <= VALUE2; Note spelling when others => DEFAULT;
else of "elsif"! end case;
SIGNAL <= VALUE3;
end if;
For loop
Sequential logic for INDEXVAR in MIN to MAX loop
-- loop body here
process (CLOCK) is
end loop;
begin
if rising_edge(CLOCK) then
-- Clocked assignments go here To count down:
end if; for INDEXVAR in MAX downto MIN loop
end process;

Enumerated types
type TYPENAME is (VAL1, VAL2, VAL3);
signal NAME : TYPENAME; Just like any other type

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