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TB Fifo

The document describes a testbench module for a FIFO module. It defines the inputs and outputs of the FIFO, generates a clock, and implements tasks to write and read from the FIFO in different patterns to test its functionality. These include single, back-to-back, and burst writes and reads of the FIFO to verify correct operation.

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jallaravi
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21 views

TB Fifo

The document describes a testbench module for a FIFO module. It defines the inputs and outputs of the FIFO, generates a clock, and implements tasks to write and read from the FIFO in different patterns to test its functionality. These include single, back-to-back, and burst writes and reads of the FIFO to verify correct operation.

Uploaded by

jallaravi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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`timescale 1 ns/ 1 ps

//----------------------------------------------------------------
// WR TX
//
// +-------+ +--------+
//__________| |______| |______ clk_i
//
// +--------------+
//__________| |______________ wr_fifo
//
//
// +------------------------------
//_________|data xxxxxxxxxxxxxx wr_fifo_data
// +------------------------------
//
// RD TX
// +-------+ +--------+ +--------+
//__________| |______| |______| |_________ clk_i
//
// +--------------+
//__________| |__________________________________ rd_fifo
//
// +---------------+-------------------
//_________________________|wait 1clk | rd_data xxxxx rd_fifo_data
// +---------------+-------------------
//
//------------------------------------------------------------------

module tb_fifo;
localparam WIDTH=8, DEPTH=16;

reg clk_i=0 ;
reg rst_n=0 ;
// wr port
reg wr_fifo =1'b0 ;
reg [WIDTH-1:0] wr_fifo_data = 'd0 ;
// rd port
reg rd_fifo = 1'b0 ;
wire [WIDTH-1:0]rd_fifo_data ;
// flags
wire empty ;
wire full ;

localparam T=10;

// fifo inst
fifo FIFO_INST (
.clk_i (clk_i ),
.rst_n (rst_n ),
.wr_fifo (wr_fifo),
.wr_fifo_data (wr_fifo_data),
.rd_fifo (rd_fifo),
.rd_fifo_data (rd_fifo_data),
.empty (empty),
.full (full)
);
reg [WIDTH-1:0] sample_read_data;

integer i=0;

//clock gen
always #(T/2) clk_i = ~ clk_i;

// reset gen
initial begin
@(negedge clk_i);
rst_n = 1'b1;
end

task fifo_write(
input [WIDTH-1:0] wr_data
);
begin
@(negedge clk_i);
wr_fifo = 1'b1;
wr_fifo_data = wr_data;

@(negedge clk_i);
wr_fifo = 1'b0;

$display ("Fifo write: Data: %h was written",wr_data);


end

endtask

task fifo_read(
output [WIDTH-1:0] rd_data
);
begin
@(negedge clk_i);
rd_fifo = 1'b1;

@(negedge clk_i); // wait for 1 clock cycle


rd_data = rd_fifo_data;
rd_fifo = 1'b0;

$display ("Fifo read: Data: %h was read",rd_data);


end
endtask

task back_to_back_write ();


begin
for (i=0;i<16;i=i+1) begin
@(negedge clk_i);
wr_fifo = 1'b1;
wr_fifo_data = (i%255)+1;
$display ("Fifo write: Data: %h was written",wr_fifo_data);
end
wr_fifo = 1'b0;
end
endtask
//task back_to_back_read ():
// begin
//
//
// end
//endtask

task wr_blast;
begin
for (i=0;i<16;i=i+1) begin
fifo_write ((i%255)+1);
end
end
endtask

task rd_balst;
begin
for (i=0;i<16;i=i+1) begin
fifo_read (sample_read_data);
end
end
endtask

task single_write_read;
begin
fifo_write (8'h01);
fifo_read (sample_read_data);
end
endtask

initial begin
$dumpfile ("tb_fifo.vcd");
$dumpvars (0, tb_fifo);

// test case 1 ::: fifo write


//single_write_read;
//wr_blast();
back_to_back_write ();
rd_balst();
#1000;
$finish;

end
endmodule

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