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Plate 4 - Design of Memory Cell Array in Logical Organization of Computer - Morales, Kristelle Janine V

This document describes a 4x3 memory cell design layout. It contains 12 memory cells arranged in a 4 row by 3 column array. Each memory cell consists of 4 transistors - 2 access transistors and 2 cross-coupled inverters to store the bit. The cells are arranged to allow independent read/write access to each cell location.

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Chelsiemea Vargas
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187 views

Plate 4 - Design of Memory Cell Array in Logical Organization of Computer - Morales, Kristelle Janine V

This document describes a 4x3 memory cell design layout. It contains 12 memory cells arranged in a 4 row by 3 column array. Each memory cell consists of 4 transistors - 2 access transistors and 2 cross-coupled inverters to store the bit. The cells are arranged to allow independent read/write access to each cell location.

Uploaded by

Chelsiemea Vargas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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4X3 MEMORY CELL DESIGN

CMPE 30141 COMPUTER ENGINEERING DRAFTING AND DESIGN


MORALES, KRISTELLE JANINE V. DATE: DECEMBER 02, 2021
BSCpE 3-6 TIME STARTED: 9:00 PM
PLATE #4: DESIGN OF MEMORY CELL ARRAY IN LOGICAL TIME FINISHED: 11:00 PM
ORGANIZATION OF COMPUTER
4X3 IC MEMORY LAYOUT DESIGN

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