UNIT – 5

Increasing the memory size

 It is not necessary to make very large memory chips and there is 2 simple
techniques that allow you to build larger memories using a number of smaller
memory chips.

The techniques are best illustrated with some examples.

 The first technique to combine many memory chips to make a larger memory is
used in the manufacturing of SIMM and DIMM memories. The memory
manufacturers would make memory chips that has a large number of cells
(addresses) but only 1 bit per cell:

The chip has

o N address lines (and thus have 2N addresses)

o 1 data line (and thus 1 bit per address)
o A number of control lines (signals). Among these are:
 Enable: this signal is used to activate the memory chip
 R/W: this signal is used to choose an operation
Presently, the most economical chips made is the 64M x 1 or the 128M x 1
chips.

Although each memory chip only has 1 bit per address, we can easily build 8
bit memory per address using these memory chips.

The following is a connection scheme that connects 8 "n x 1" memory chips
into a "n x 8" memory:

Notice that:

o The MEM signal of the system bus is used to activate the memory
chips (MEM = 1 if the CPU wants to access the memory !)
o The R/W signal of the system bus is used to choose the operation on
the memory chip.
o Each memory chip is used to read and write a separate bit of the
databus. (the data bit of different memory chips are connected to
a different wire of the data bus)
 This technique is used to build SIMM and DIMM memories that is currently
used in Pentium class machines.

These machines now have 32 or 64 bit databus and in one single read
operation, the CPU can read or write 32 or 64 bits at a time. (You may wonder
how such machine will read a byte... the CPU will read 32 or 64 bits from
memory that contains the byte it wants and "extract" the byte...)

 SIMM and DIMM:

SIMM (symmetric in-line memory module) memory modules look like this:

And they are placed in a "SIMM socket" on the motherboard of the computer.
The following picture shows a SIMM slot:
 The following picture shows a mother board:

The SIMM socket is at the top...

SIMM's, come in 30 and 72 pin sizes the latter now becoming the standard.
Older boards used by Intel 386, and some 486 machines have 30 pin sockets.
The 30 pin SIMM module was designed for 8-bit data flow, and are generally
placed in groups of four to give a 32-bit data path. (4x8 = 32).

The 72 pin SIMM was designed for 32-pin operation, and it is 50% longer in
physical length. As the databus width grew and 64 bit buses became prevalent,
the 72 pin SIMM would can be 'pair-up' to provide 64 bit data at once. But that
caused a space problem on the motherboard and The answer was the DIMM
(dual in-line memory module).

DIMMs have 168 pins and was designed to support 64-bit read/write
operations. DIMMs look similar to the older SIMM but differ in a key area.
The DIMM is highly economized on space used for pins. The DIMM module
uses both sides of the board, having 84 pins on each side (2 x 84 = 168 pins).
Each pin is completely independent of the others, and makes a separate
electrical contact. The density of the DIMM memory module is increased with
only the slightest increase in the module's physical size.

 The second technique to increase memory size was used way back in 1980's
when the most popular memory chips manufactured was the "n x 8" memory
chip.
The chip has

o N address pins or lines (and thus have 2N addresses)

o 8 data pins or lines (and thus 8 bits per address)

Granted, in those days, the "n" in "n x 8" is much less... like "1K x 8" to about
"16K x 8"... and you pay a lot more money to buy them :-(

The following figure shows how we can use 4 "1K x 8" to construct a "4K x 8"
memory:
 Notice that:

o Each memory chip has 10 address pins

o The address bus has 12 address pins
o The most significant 2 address bits selects exactly one of the memory
chips to become active for reading/writing while all other memory chips
are not active (with tri-state-buffers off !) because:
 The Decoder will send out exactly one 1, and the other 3 outputs
are 0

Associative Memory
An associative memory can be considered as a memory unit whose stored data can be
identified for access by the content of the data itself rather than by an address or memory
location.

Associative memory is often referred to as Content Addressable Memory (CAM).

When a write operation is performed on associative memory, no address or memory
location is given to the word. The memory itself is capable of finding an empty unused
location to store the word.

On the other hand, when the word is to be read from an associative memory, the content of
the word, or part of the word, is specified. The words which match the specified content are
located by the memory and are marked for reading.

The following diagram shows the block representation of an Associative memory.

From the block diagram, we can say that an associative memory consists of a memory array
and logic for 'm' words with 'n' bits per word.

The functional registers like the argument register A and key register K each have n bits,
one for each bit of a word. The match register M consists of m bits, one for each memory
word.

The words which are kept in the memory are compared in parallel with the content of the
argument register.
The key register (K) provides a mask for choosing a particular field or key in the argument
word. If the key register contains a binary value of all 1's, then the entire argument is
compared with each memory word. Otherwise, only those bits in the argument that have 1's
in their corresponding position of the key register are compared. Thus, the key provides a
mask for identifying a piece of information which specifies how the reference to memory is
made.

The following diagram can represent the relation between the memory array and the
external registers in an associative memory.

The cells present inside the memory array are marked by the letter C with two subscripts.
The first subscript gives the word number and the second specifies the bit position in the
word. For instance, the cell Cij is the cell for bit j in word i.

A bit Aj in the argument register is compared with all the bits in column j of the array
provided that Kj = 1. This process is done for all columns j = 1, 2, 3......, n.
If a match occurs between all the unmasked bits of the argument and the bits in word i, the
corresponding bit Mi in the match register is set to 1. If one or more unmasked bits of the
argument and the word do not match, Mi is cleared to 0

Cache Memory
The data or contents of the main memory that are used frequently by CPU are stored in the
cache memory so that the processor can easily access that data in a shorter time.
Whenever the CPU needs to access memory, it first checks the cache memory. If the data is
not found in cache memory, then the CPU moves into the main memory.

Cache memory is placed between the CPU and the main memory. The block diagram for a
cache memory can be represented as:

The cache is the fastest component in the memory hierarchy and approaches the speed of
CPU components.

The basic operation of a cache memory is as follows:

o When the CPU needs to access memory, the cache is examined. If the word is found
in the cache, it is read from the fast memory.
o If the word addressed by the CPU is not found in the cache, the main memory is
accessed to read the word.
o A block of words one just accessed is then transferred from main memory to cache
memory. The block size may vary from one word (the one just accessed) to about 16
words adjacent to the one just accessed.
o The performance of the cache memory is frequently measured in terms of a quantity
called hit ratio.
o When the CPU refers to memory and finds the word in cache, it is said to produce
a hit.
o If the word is not found in the cache, it is in main memory and it counts as a miss.
 o The ratio of the number of hits divided by the total CPU references to memory (hits
plus misses) is the hit ratio.

Virtual Memory in Operating System

Virtual Memory is a storage allocation scheme in which secondary memory can be
addressed as though it were part of main memory. The addresses a program may use
to reference memory are distinguished from the addresses the memory system uses to
identify physical storage sites, and program generated addresses are translated
automatically to the corresponding machine addresses.
The size of virtual storage is limited by the addressing scheme of the computer system
and amount of secondary memory is available not by the actual number of the main
storage locations.
It is a technique that is implemented using both hardware and software. It maps
memory addresses used by a program, called virtual addresses, into physical
addresses in computer memory.
1. All memory references within a process are logical addresses that are dynamically
translated into physical addresses at run time. This means that a process can be
swapped in and out of main memory such that it occupies different places in main
memory at different times during the course of execution.
2. A process may be broken into number of pieces and these pieces need not be
continuously located in the main memory during execution. The combination of
dynamic run-time address translation and use of page or segment table permits
this.
If these characteristics are present then, it is not necessary that all the pages or
segments are present in the main memory during execution. This means that the
required pages need to be loaded into memory whenever required. Virtual memory is
implemented using Demand Paging or Demand Segmentation.
Demand Paging :
The process of loading the page into memory on demand (whenever page fault occurs) is
known as demand paging.
The process includes the following steps :

1. If CPU try to refer a page that is currently not available in the main memory, it
generates an interrupt indicating memory access fault.
2. The OS puts the interrupted process in a blocking state. For the execution to
proceed the OS must bring the required page into the memory.
3. The OS will search for the required page in the logical address space.
4. The required page will be brought from logical address space to physical address
space. The page replacement algorithms are used for the decision making of
replacing the page in physical address space.
5. The page table will updated accordingly.
6. The signal will be sent to the CPU to continue the program execution and it will
place the process back into ready state.
Hence whenever a page fault occurs these steps are followed by the operating system
and the required page is brought into memory.
Advantages :
 More processes may be maintained in the main memory: Because we are going to
load only some of the pages of any particular process, there is room for more
processes. This leads to more efficient utilization of the processor because it is
more likely that at least one of the more numerous processes will be in the ready
state at any particular time.
 A process may be larger than all of main memory: One of the most fundamental
restrictions in programming is lifted. A process larger than the main memory can
 be executed because of demand paging. The OS itself loads pages of a process in
main memory as required.
 It allows greater multiprogramming levels by using less of the available (primary)
memory for each process.
Page Fault Service Time :
The time taken to service the page fault is called as page fault service time. The page
fault service time includes the time taken to perform all the above six steps.
Let Main memory access time is: m
Page fault service time is: s
Page fault rate is : p
Then, Effective memory access time = (p*s) + (1-p)*m
Swapping:
Swapping a process out means removing all of its pages from memory, or marking them
so that they will be removed by the normal page replacement process. Suspending a
process ensures that it is not runnable while it is swapped out. At some later time, the
system swaps back the process from the secondary storage to main memory. When a
process is busy swapping pages in and out then this situation is called thrashing.
Thrashing :

At any given time, only few pages of any process are in main memory and therefore
more processes can be maintained in memory. Furthermore time is saved because
unused pages are not swapped in and out of memory. However, the OS must be clever
about how it manages this scheme. In the steady state practically, all of main memory
will be occupied with process’s pages, so that the processor and OS has direct access
to as many processes as possible. Thus when the OS brings one page in, it must throw
another out. If it throws out a page just before it is used, then it will just have to get that
page again almost immediately. Too much of this leads to a condition called Thrashing.
The system spends most of its time swapping pages rather than executing instructions.
So a good page replacement algorithm is required.

In the given diagram, initial degree of multi programming upto some extent of
point(lamda), the CPU utilization is very high and the system resources are utilized
100%. But if we further increase the degree of multi programming the CPU utilization
will drastically fall down and the system will spent more time only in the page
replacement and the time taken to complete the execution of the process will increase.
This situation in the system is called as thrashing.

Causes of Thrashing :
1. High degree of multiprogramming : If the number of processes keeps on
increasing in the memory than number of frames allocated to each process will be
decreased. So, less number of frames will be available to each process. Due to
this, page fault will occur more frequently and more CPU time will be wasted in just
swapping in and out of pages and the utilization will keep on decreasing.
 For example:
Let free frames = 400
Case 1: Number of process = 100
Then, each process will get 4 frames.
Case 2: Number of process = 400
Each process will get 1 frame.
Case 2 is a condition of thrashing, as the number of processes are
increased,frames per process are decreased. Hence CPU time will be consumed
in just swapping pages.
2. Lacks of Frames:If a process has less number of frames then less pages of that
process will be able to reside in memory and hence more frequent swapping in and
out will be required. This may lead to thrashing. Hence sufficient amount of frames
must be allocated to each process in order to prevent thrashing.
Recovery of Thrashing :
 Do not allow the system to go into thrashing by instructing the long term scheduler
not to bring the processes into memory after the threshold.
 If the system is already in thrashing then instruct the mid term schedular to
suspend some of the processes so that we can recover the system from thrashing.