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Flip Flops and Counters: Digital Logic Design Laboratory

This document describes a digital logic design laboratory experiment involving flip flops and counters. The objectives are to understand flip flop operation, design circuits using flip flops to implement functions, and design counters using flip flops. The procedure involves investigating JK, D, and converting JK to D flip flops. It also includes designing asynchronous up/down and synchronous counters using flip flops and implementing the designs in a simulation tool.

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Trương Quang Tường
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729 views

Flip Flops and Counters: Digital Logic Design Laboratory

This document describes a digital logic design laboratory experiment involving flip flops and counters. The objectives are to understand flip flop operation, design circuits using flip flops to implement functions, and design counters using flip flops. The procedure involves investigating JK, D, and converting JK to D flip flops. It also includes designing asynchronous up/down and synchronous counters using flip flops and implementing the designs in a simulation tool.

Uploaded by

Trương Quang Tường
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Digital Logic Design Laboratory

Lab 6

Flip Flops and Counters

Full name:
…………BestGa………………………………….
Student number: ………………………………….
Class:
……………………………………………….......
Date:
…………………………………………………....

Digital Logic Design Laboratory 1-16


Digital Logic Design Laboratory 2-16
I. Objectives

In this laboratory, students will study:


- Understand the operation of Flip Flops.
- Use a Flip Flops and design/implement a circuit based on a function definition.
- Design a counter based on Flip Flops

II. Procedure

1. Investigate Flip Flops (FF)


Flip flops are one of the most fundamental electronic components. These are used as
one-bit storage elements, clock dividers and it can make counters, shift registers and
storing registers by connecting the flip flops in particular sequences.

a. JK- Flip Flops


Given the JK Flip Flop as shown in Figure 1. The J-K flip-flop is the most versatile of
the basic flip-flops. It has two inputs, traditionally labeled J and K. If J and K are
different then the output Q takes the value of J at the next clock edge.

Figure 1. JK Flip Flop

Digital Logic Design Laboratory 3-16


Built the truth table:
J K CLK Q+

0 0 ↑ 𝑄0 (no change)

0 1 ↑ 1
1 0 ↑ 0

1 1 ↑ 𝑄0(toggle)

What is the usage of and ?

(present) to set a state

(clear) input drives into reset state

Implement the circuit (Figure 1) via simulation software and paste the result in here

Digital Logic Design Laboratory 4-16


b. D- Flip Flops
The D flip-flop tracks the input, making transitions with match those of the input D.
The D stands for "data"; this flip-flop stores the value that is on the data line. It can be
thought of as a basic memory cell.

Digital Logic Design Laboratory 5-16


Figure 2. D Flip Flop

Built the truth table:


CL
D K Q+
0 ↑ 0
1 ↑ 1

What is the usage of and ?

Implement the circuit (Figure 2) via simulation software and paste the result in here

Digital Logic Design Laboratory 6-16


c. Convert JK-FF into D-FF
From the block diagram shown in figure 3, design the circuit to convert JK-FF to
D-FF:

Figure 3. Convert JK-FF into D-FF


Implement the circuit via simulation software and paste the result in here

Digital Logic Design Laboratory 7-16


Make comment on the results

2. Analyze and design asynchronous counters


a. Implement an asynchronous up counter having M = 8 using J-K Flip Flop

Implement the below circuit in Figure 4. Control (SW1) and (SW2) to make

the circuit operate.

Figure 4. Logic diagram

Digital Logic Design Laboratory 8-16


Implement the circuit via simulation software and paste the result in here

Make comment on the results

b. Design an asynchronous up counter having M = 6 by using J-K Flip Flop


Show the way to make it (step by step)

Digital Logic Design Laboratory 9-16


Implement the circuit via simulation software and paste the result in here

c. Implement an asynchronous 3-bit down counter having M = 8 by using J-K


Flip Flop

Implement the below circuit shown in Figure 5. The (SW1) and (SW2) inputs

are in the appropriate states to make the circuit operate:

Digital Logic Design Laboratory 10-16


Figure 5. Logic diagram

Implement the circuit via simulation software and paste the result in here

Make comment on the results

d. Implement an asynchronous 3-bit counter having M = 8, with a control for


up/down counting.

Implement the below circuit shown in Figure 6. The (SW1) and (SW2) inputs

are in the appropriate states to make the circuit operate:

Digital Logic Design Laboratory 11-16


Figure 6. Logic diagram

Implement the circuit via simulation software and paste the result in here

Make comment on the results

Digital Logic Design Laboratory 12-16


3. Analyze and design synchronous counters
a. Analyze the counter given schematic circuit

Implement the below circuit in Figure 7. Control (SW1) and (SW2) to make

the circuit operate.

Figure 7. Logic diagram


When the clock is active:
…………………………………………………………………………………………
………………………………………………………………………………………….
Write the excitation (trigger) input equations of all flip-flops:
'
J0 =𝑄2; K0 = 0

J1 = 𝑄0; K1 = 𝑄0

J2 = 𝑄0𝑄1; K2 = 0

Transition Table
Present State Next State
Q2 Q1 Q0 J2 K2 J1 K1 J0 K0 Q2 Q1 Q0
0 0 0 0 0 0 0 1 0 0 0 1
0 0 1 0 0 1 1 1 0 0 1 1
0 1 0 0 0 0 0 1 0 0 1 1
0 1 1 1 0 1 1 1 0 1 0 1
1 0 0 0 0 0 0 0 0 1 0 0
1 0 1 0 0 1 1 0 0 1 1 1

Digital Logic Design Laboratory 13-16


1 1 0 0 0 0 0 0 0 1 1 0
1 1 1 1 0 1 1 0 0 1 0 1

Implement the circuit via simulation software and paste the result in here
0

Draw the state diagram of the counter

Make comment on the results

Digital Logic Design Laboratory 14-16


b. Design and implement a synchronous counter by the given state diagram
Design and implement a synchronous 2-bit counter shown in the given diagram as
shown in Figure 8 using J-K Flip Flops

Figure 8. State diagram

Transition Table
Present State Next State
Q1 Q0 J1 K1 J0 K0 Q1 Q0
0 0 1 X 0 X 1 0
1 0 X 1 X 0 0 1
0 1 1 X 1 X 1 1
1 1 X 0 0 1 1 0

Write the excitation (trigger) input equations of all flip-flops:


J0 =𝑄'1𝑄0; K0 = 𝑄0
'
J1 =1; K1 =𝑄0

Implement the circuit via simulation software and paste the result in here

Make comment on the results

Digital Logic Design Laboratory 15-16


Digital Logic Design Laboratory 16-16

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