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Final Examination: Subject: Digital Logic Design Laboratory Date: Monday, May 30, 2022. Duration: 75 Minutes

The document is a final exam for a digital logic design laboratory course. It consists of 3 questions: 1. Logic gate combinational circuits worth 40 points, involving drawing truth tables, using K-maps to simplify logic functions, and simulating circuits. 2. A full adder circuit worth 40 points, involving drawing a truth table and writing logic functions for the sum and carry outputs, and simulating the circuit. 3. Designing an asynchronous 7-state up counter from given circuitry worth 20 points, involving simulating the circuit and building it with laboratory equipment.

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Trương Quang Tường
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204 views4 pages

Final Examination: Subject: Digital Logic Design Laboratory Date: Monday, May 30, 2022. Duration: 75 Minutes

The document is a final exam for a digital logic design laboratory course. It consists of 3 questions: 1. Logic gate combinational circuits worth 40 points, involving drawing truth tables, using K-maps to simplify logic functions, and simulating circuits. 2. A full adder circuit worth 40 points, involving drawing a truth table and writing logic functions for the sum and carry outputs, and simulating the circuit. 3. Designing an asynchronous 7-state up counter from given circuitry worth 20 points, involving simulating the circuit and building it with laboratory equipment.

Uploaded by

Trương Quang Tường
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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International University Digital Signal Processing Laboratory

School of Electrical Engineering EE093IU

FINAL EXAMINATION
Subject: Digital Logic Design Laboratory
Date: Monday, May 30th, 2022.
Duration: 75 minutes
Instructor Grade
Signature:

Full name: Nguyen Hoang An, M.Eng.

Student’s Name:

ID:

IMPORTANT INFORMATION
● The Final exam is conducted using SimuliDE software and the Laboratory
experiment kits. Any access to the Internet during the exam is PROHIBITED.
● After finishing your simulation, copy simulation circuit figures under each of the
Problems given in the Question sheet. Answer any questions available in the
Question sheet. If the question has the practical circuit build-up requirement,
kindly show the result to the instructor for achieving full marks of that respective
question.
● Convert the Question sheet with the answered questions into “pdf” file format

named “DLD_FinalExam_StudentName_StudentID.pdf”, alongside with all of the


simulation circuits, into a compressed file and submit it via Blackboard.
1 Logic gate combinational circuits /40pts
Given the following circuit:

a. Write down the function F ( A , B ,C )=¿ (10pts)

b. Fill in the truth table of the above circuit (10pts)

A B C F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

c. Using K-map to simplify function above, and implement the simplified circuit in the
simulation program with full notation. (You can use the created squares to your
simplification process and write down the simplified expression)

The simplified function F ( A , B ,C )=¿ (10pts)

A \ BC 00 01 11 10

0
1

1
Simulation circuit: (10pts)

2 Full Adder
/40pts
1

Three inputs are Cin, A, B. Two outputs are S and Cout:

a. Build the truth table (10pts)

A B Cin S Cout
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

b. Write down the function of

S=¿ (10pts)

C out =¿ (10pts)

c. Implement the circuit with full notation

Simulation circuit: (10pts)

2
3 Counters
/20 pts

Given the following circuit

Design an asynchronous up counter having M = 7 from the above circuit. Implement the
circuit via simulation software and paste the result in the bellow box.

Simulation circuit: (10pts)

Implement the circuit using the Laboratory experiment kit. Show the result to the instructor. (10pts)

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