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Cmos Vlsi Design - 2019 Syllabus, Course Outcomes

This document outlines a course on CMOS VLSI Design. The course objectives are to focus on CMOS technology basics, digital VLSI challenges, and combinational and sequential logic circuit design using CMOS. It will also cover subsystem design including adders, multipliers, and memory structures. The last unit covers basic physical design including partitioning, floorplanning, placement, and routing. The course aims to help students analyze and evaluate VLSI system design with constraints, and create significant design projects. It consists of 5 units covering MOS transistor theory, combinational logic, sequential logic, subsystem design, and basic construction over 45 hours. Student outcomes include remembering CMOS analysis models, recognizing different logic styles, applying sequential design tradeoffs,

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Dinesh Gaikoti
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134 views1 page

Cmos Vlsi Design - 2019 Syllabus, Course Outcomes

This document outlines a course on CMOS VLSI Design. The course objectives are to focus on CMOS technology basics, digital VLSI challenges, and combinational and sequential logic circuit design using CMOS. It will also cover subsystem design including adders, multipliers, and memory structures. The last unit covers basic physical design including partitioning, floorplanning, placement, and routing. The course aims to help students analyze and evaluate VLSI system design with constraints, and create significant design projects. It consists of 5 units covering MOS transistor theory, combinational logic, sequential logic, subsystem design, and basic construction over 45 hours. Student outcomes include remembering CMOS analysis models, recognizing different logic styles, applying sequential design tradeoffs,

Uploaded by

Dinesh Gaikoti
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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SATHYABAMA INSTITUTE OF SCIENCE AND TECHNOLOGY SCHOOL OF ELECTRICAL AND ELECTRONICS

L T P Credits Total Marks


SECA1503 CMOS VLSI DESIGN
3 0 0 3 100

COURSE OBJECTIVES
Ø To focus on basics of semiconductor physics, Predominant CMOS technology.
Ø To study challenges of digital VLSI design.
Ø To get an idea about combinational logic circuit using CMOS logic style.
Ø To acquire the knowledge about sequential logic circuit and subsystem design.
Ø To extract the backend VLSI algorithms for ASIC.

UNIT 1 MOS TRANSISTOR THEORY 9 Hrs.


The MOS transistor-Current Voltage Relations-Threshold Voltage-Second order effects-Capacitances in MOSFET - Scaling
of MOS circuits -Review of CMOS - DC characteristics - Dynamic behavior- Power consumption.

UNIT 2 COMBINATIONAL LOGIC DESIGN 9 Hrs.


nMOS depletion load and Static CMOS design - Determination of Pull-up and Pull-down ratio-Design of Logic gates- Sizing
of transistors -Stick diagrams-Lay out diagram for static CMOS - Pass transistor logic - Dynamic CMOS design - Noise
considerations - Domino logic, np CMOS logic - Power consumption in CMOS gates - Multiplexers - Transmission gates
design.

UNIT 3 SEQUENTIAL LOGIC DESIGN 9 Hrs.


Introduction - Static sequential circuits- CMOS static flip-flop - Dynamic sequential circuits -Pseudo static latch- Dynamic two
phase flip-flop - clocked CMOS logic - Pipelining - NORA CMOS logic -True single phase clocked logic - Realization of D-FF
in TSPC logic.

UNIT 4 SUBSYSTEM DESIGN 9 Hrs.


Introduction-Designing Static and Dynamic Adder circuits - The Array Multiplier - Multiplier structures-Baugh-Wooly - Booth
Multiplier - Barrel shifter - Memory structures - SRAM and DRAM design - Design approach of Programmable logic devices -
PLA,PAL and FPGA.

UNIT 5 BASIC CONSTRUCTION 9 Hrs.


Physical design - Goals and Objectives - Partitioning methods - Kernighan Lin algorithm - Hierarchical Floor planning - Floor
planning tools -input, output and power planning -Min-cut placement, Force directed placement algorithm -Placement using
simulated annealing - Greedy channel routing.
Max. 45 Hrs.
COURSE OUTCOMES
On completion of the course, students are able to
CO1 - Remember the mathematical methods and circuit analysis models in analysis of CMOS transistors and inverters.
CO2 - Recognize the different styles of CMOS logic for combinational logic circuit circuits.
CO3 - Apply the performance issues and the inherent trade-offs involved in sequential logic design.
CO4 - Analyze the design of CMOS subsystems, memory structures.
CO5 - Evaluate the design of programmable logic devices and FPGA.
CO6 - Create a significant VLSI system design project having a set of objectives criteria and design constraints of ASICs
along with algorithms of backend VLSI.

TEXT / REFERENCE BOOKS


1. Jan M.Rabaey ,“Digital Integrated Circuits” , 2nd Edition, September, PHl Ltd.2000.
2. M.J.S.Smith ,“Application Specific Integrated Circuits “, 1st Edition, Pearson education.1997.
3. Douglas A.Pucknell,”Basic VLSI design”, PHI Limited, 1998.
4. E.Fabricious, “Introduction to VLSI design”, McGraw Hill Limited, 1990.
5. Neil Weste , “Principles of CMOS VLSI design”, Addison Wesley 1998.
6. Wayne Wolf,”Modern VLSI design”, 2nd Edition, Pearson education.2003.
7. Sung-Mo Kang and Yusuf, ”CMOS Digital Integrated Circuits- Analysis and Design”, 2nd Edition, MGH.

END SEMESTER EXAMINATION QUESTION PAPER PATTERN


Max. Marks : 100 Exam Duration: 3 Hrs.
PART A: 10 Questions of 2 marks each-No choice 20 Marks
PART B: 2 Questions from each unit of internal choice; each carrying 12 marks 80 Marks

B.E. / B.Tech. - Regular 41 REGUALTIONS 2019

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