UNIT – 5

MSP 43O GPIO, TIMER AND ON-CHIP PERIPHERALS

NON-INTERRUPTIBLE AND INTERRUPTIBLE I/O

The MSP 430 I/O ports are 8 bit wide and controlled with memory mapped
registers. Along with the basic I/O functions, each port pin can be individually
configured as special function I/Os, such as USART, Comparator and ADC.

MSP 430 I/O ports can be classified into two types:

1. Non-interruptible I/O
2. Interruptible I/O

1)Non – Interruptible I/O

Non-Interruptible I/O logic diagram

Non-interruptible means the ports cannot be used to generate interrupts. I/O

ports 3, 4, 5 and 6 are non-interruptible ports. These ports are not
implemented on all devices. Use of non-interruptible I/O is simple and
straightforward. Each bit is individually controllable, so inputs, outputs and
dedicated function I/O can be mixed in a single port. Port pins are controlled
by four byte addressable registers: direction, input, output and function select.

▪ Direction registers: These read/write registers control the signal

direction for port pins. When a bit in the direction register is set, the
corresponding port pin is set as an output, and when the bit in direction
register is cleared, the port pin is set as an input.
▪ Input registers: These are read only registers which reflect the input
value on the port.
▪ Output registers: These registers are used to write to output ports and
can be read as well. When reading these registers, they reflect the last
value written to them.
▪ Function select registers: These read/write registers are used to select
function for individual port pins. When the bit in the function select
register is set, the port pin is used for module selection, and when the
bit is cleared, the port pin is used for general purpose I/O.

2) Interruptible I/O
Interruptible means the ports can be used to generate interrupts. I/O ports 1
and 2 (P1, P2) are interruptible ports. Interrupts on the each pin can be
provided on a rising edge or falling edge of an input signal. Interruptible ports
use all the control registers of non-interruptible ports along with three other
byte addressable registers. They are: interrupt enable register, interrupt edge
select register and interrupt flag register.

▪ Interrupt Enable register: This read/write register enables interrupts on

individual pins. Interrupts on the pins are enabled if their corresponding
bits in this register are set, or else disabled.
▪ Interrupt Edge select register: This read/write register selects the
transition on which an interrupt occurs. If set, an interrupt occurs on the
falling edge on the corresponding pin, if reset, an interrupt occurs on the
rising edge on the corresponding pin.
▪ Interrupt flag registers: The corresponding bit in this read/write register
is set automatically when valid interrupt is generated. When an interrupt
occurs, this flag needs to be cleared before the reti instruction.

CLASSIFICATION OF TIMERS

Most modern microcontrollers provide range of timers as listed below:

WATCHDOG TIMER

● Included in all devices

● It is used to protect the system against malfunction
● If protection is not needed, it can be used as an interval timer

BASIC TIMER 1

• Present in the MSP430x4xx family only

• It provides clock for LCD and acts as an interval timer

REAL TIMER CLOCK

• Present in the most recent MSP430x4xx family

• It provides real time clock.

TIMER – A

• Most versatile timer present in all the devices

• It can handle external inputs and outputs directly to measure frequency

• It can handle time-stamp inputs and drive outputs at specified times or

periodically

• It can even generate interrupts

TIMER – B

• Included in larger devices of all families

• It is similar to Timer – A with some extensions

• It is able to drive PWM outputs

HARDWARE MULTIPLIER WITH ITS REGISTERS

Some of the larger MSP 430 devices include hardware multiplier. It is a
memory mapped peripheral device and is not part of the MSP 430 CPU

SUMEXT register is used for signed multiply and multiply accumulate

operations. Fig shows the structure of hardware multiplier.

The following table shows the hardware multiplier registers with its addresses:

Register name description address type

MPY (OP1) Unsigned multiply 0x0130 Read/Write

MPYS (OP1) Signed multiply 0x0132 Read/Write

MAC (OP1) Unsigned multiply 0x0134 Read/Write

accumulate

MACS (OP1) Signed multiply 0x0136 Read/Write

accumulate

OP2 Operand 2 0x0138 Read/Write

RESLO Result LO 0x013A Read/Write

RESHO Result HI 0x013C Read/Write

SUMEXT Sum Extend 0x013E Read only

Advantages of hardware multiplier:

1. It is very straightforward to use

2. Its activities do not interfere with the CPU activities
 3. It supports unsigned multiply, unsigned multiply accumulate, signed
multiply and signed multiply accumulate operations
4. The result is ready in 3 MCLK cycles.

Applications:

Floating point multiplication, FFT operations, DSP systems, FIR filters and
portable battery powered devices.

WATCHDOG TIMER WITH ITS CONTROL REGISTER

The main function of the watchdog timer is to protect the system against
failure of the software, such as program being trapped in an unintended,
infinite loop. If this protection is not needed, it can be made to function as an
interval timer, in which it counts up and resets MSP 430 when it reaches its
maximum limit.

The operation of the watchdog timer is controlled by the 16-bit register

WDTCTL. It is protected against accidental writes by requiring the password,
WDTPW=0x5A in the upper byte of WDTCTL. A reset will occur when an
incorrect password is written. Reading WDTCTL returns 0x69 and writing back
the same thing in upper byte violates the password and causes system reset.

The lower byte of the watchdog timer control register is shown below:

The bit fields are described as below:

WDTHOLD =>stops the watchdog timer when the bit is 1.

WDTNMIES =>selects the triggering edge for the non maskable interrupt on
RST/NMI pin. 0 indicates a rising edge and a 1 represents a falling edge.

WDTNMI  =>Watchdog timer NMI select. This bit selects the function for the
RST/NMI pin. 0 : Reset function and 1 : NMI function. 

WDTTMSEL =>watchdog timer mode select.

0: watchdog mode

1: interval timer mode

WDTCNTCL => watchdog timer counter clear.When the bit is set the counter is
cleared to the value 0x0000.

WDTSSEL =>watchdog timer clock source select. 0 selects the SMCLK and 1
selects the ACLK.

WDTISx =>watchdog timer interval select. This bit is used to select the
watchdog timer period to generate WDT interrupt or WDT reset. When
WDTIS=00, it selects longest period of 1s at 32KHz ACLK.

LCD DRIVER FEATURES

• The 3XX And 4XX family includes built in LCD driver to directly control
LCD displays.

• LCD driver supports multiplexing rate up to 4

• Includes built in charge pump which provides higher regulated voltage to

the LCD

• LCD driver generates AC signals for the LCDs

• LCD driver generates biasing voltages to drive LCDs

• LCD driver provides contrast control

• LCD driver includes internal timing generators

• Supports blinking

• LCD driver works on ultra low power

• Can drive larger LCDs

LCD DRIVER CONTROL REGISTER

Fig shows the LCD driver control register whose bit fields are described as
below:
TIMER- A BLOCK DIAGRAM
 Fig: Simplified block diagram of Timer – A

Timer-A is the most versatile and general purpose timer in the MSP 430 and is
included in all devices. There are two main parts in the hardware: timer block
and capture/compare channels.

Timer block:

It is the core of timer-A whose operation depends on the 16 bit register TAR.
There is a choice of sources for the clock, whose frequency can be divided
down. The timer block has no output but a flag TAIFG is raised when the
counter returns to zero.

Capture/compare channels:

Most of the events occur in this, each of which is based on a register TACCRn.
They all work in the same way except TACCR0. Each channel can:

● Capture an input, which means recording the time at which an input

changes in TACCRn. The input can be either external from the peripheral
device or internal from the software.
 ● Comparethe current value of TAR with the value stored in TACCRn and
update an output when they match; the output can again be either
external orinternal.
● Request an interruptby setting its flag TACCRn CCIFG on either of these
events; this can be done even if no output signal is produced.
● Samplean input at a compare event; this special feature is particularly
useful ifTimer_A is used for serial communication in a device that lacks a
dedicatedinterface.

Timer_A is modular and the number of capture/compare channels varies

between devices. Most have three channels but the smallest members of the
MSP430F2xx family have only two.

TIMER A APPLICATIONS

● Measurement of time
● Measurement of frequency
● Generation of output in continuous mode: generates independent
periodic signals, single pulse, PWM output.

TIMER-A CAPTURE COMPARE CHANNELS

Timer_A has three channels in most MSP430s. Each channel is controlled by a

register TACCTLn.

Capture mode: The capture mode is selected when CAP=1. Capture mode is
used to record time events, for speed computations and time measurements.
The capture inputs CCIxA and CCIxB are connected to external pins or internal
signals and are selected with the CCISx bits. The CMx bits select the capture
edge (event) of the input signal which can be rising edge, falling edge or both
the edges. A capture occurs on the selected edge of the input signal.

If a capture occurs:

● The timer value (the value in TAR) is copied into the TACCRn register.
● The interrupt flag CCIFG is set.
Compare mode:Compare mode is selected when CAP=0. This mode is used to
generate PWM output signals and produce an interrupt at the time stored in
TACCRn. Several actions are triggered when TAR counts to the value in
TACCRn:

● Interrupt flag CCIFG is set.

● Internal signal EQUx=1
● EQUx affects the output according to the output mode.
● The input signal CCI is latched into SCCI.

Any mixture of capture and compare channels can be used and the mode can
be switched freely from one to another.

TIMER-A CAPTURE COMPARE CONTROL REGISTER (TACCTLn)

The bit fields indicated in the timer-A capture/compare control register are
described as below:

CCIFG: Capture Compare interrupt flag

0: interrupt pending

1: No interrupt pending

COV: Capture Overflow

COV bit is set if another capture occurs before TACCRn is read following the
previous event.
OUT: Output

For output mode 0,

If this bit is 0: Low output

1: High output

CCI: capture/compare input. This bit is used

to indicate the state of the selected input

CCIE: Capture compare interrupt enable

0: interrupt pending

1: no interrupt pending

OUTMODx: output modes for capture compare channel.

CAP: capture mode

0: compare mode, 1: capture mode

SCCI: Synchronized capture compare input

The selected CCI input is latched to the EQX signal

SCS: Synchronize capture source. This bit is used to synchronize the capture
input signal with the timer clock

0:Asynchronous capture

1: Synchronous capture

CCISx: Capture compare input select

00: CCIxA

01:CCIxB

10:GND

11:VCC

CMx: capture mode

00: no capture

01: capture on rising edge

10: capture on falling edge

11: capture both edges

TIMER-A INTERRUPTS

Interrupts can be generated by the timer block itself (flag TAIFG) and each
capture/compare channel (flag TACCRn CCIFG or CCIFGn for short). TACCR0 is
privileged and has its own interrupt vector, TIMERA0_VECTOR. Its priority is
higher than the other vector, TIMERA1_VECTOR, which is shared by the
remaining capture/compare channels and the timer block. The CCIFG0 flag is
cleared automatically when its interrupt is serviced but this does not happen
for the other interrupts because the interrupt service routine (ISR) must first
determine the source of the interrupt.

The MSP430 therefore provides an interrupt vector register TAIV to identify

the source of the interrupt rapidly. The possible values in TAIV for Timer_A3
are listed in the following table with their priorities.
Table: Interrupt vector register TAIV for Timer_A3

UNIT – 6

MSP 430: MIXED SIGNAL SYSTEMS

ARCHITECTURE OF COMPARATOR – A

An analog comparator compares the voltages on its two input terminals, V+

and V−. Its output is high if V+ >V− and low if V+ <V−. Fig shows the block
diagram of comparator-A which looks complicated because of the many
options provided. These are controlled with the two peripheral registers
CACTL1 and CACTL2.

The entire module is switched on and offwith the CAON bit. It is off by default
to save current.The non-inverting input V+ can be connected to external
signals CA0–CA2 or left without an external connection. This is selected using
bits P2CA4 and P2CA0.Similarly, the inverting input V− can be connected to
external signals CA1–CA7 or left unconnected, according to bits P2CA[3:1].The
internal reference voltage VCAREF can be chosen from ¼ VCC, ½ VCC or a
nominally fixed voltage from a transistor, Vdiode. This is selected with the
CAREFx bits. It can be applied to either input of the comparator according to
the CARSEL bit.

The output of the comparator can optionally be filtered through an RC circuit

to reduce oscillations in the signal, which may arise if the inputs vary slowly.
This is selected with the CAF bit. The filter is off by default. The output is
brought to an external pin CAOUT. It is also connected internally to capture
input CCI1B of Timer_A. The flag CAIFG is raised on either a rising or falling
edge of the comparator output. This can in turn request an interrupt if CAIE is
set.

OPERATION OF COMPARATOR- A

The comparator can be used to compare a variable input voltage with a

reference,which may be an internal reference or a second input. For example,
the variable input might be from a temperature sensor and the comparator
should detect when the equipment may freeze. A thermistor is a type of
temperature sensor that is often used with the comparator.

It can be useful to connect a noisy input signal to the comparator so that the
MSP430 detects when the input goes through a well-defined level, such as
0.5VCC.

We want an analog-to-digital converter rather than a plain comparator. This

goal can be achieved by adding a capacitor to form an RC circuit and using a
timer to measure its dynamic behavior. The operation can be performed in
many ways:

● A single transient of an RC circuit can be timed to determine R or C.

• Alternatively, the circuit can be made to oscillate and the frequency is

measured rather than the duration of a single transient.

• An external voltage can be measured by comparing it with an RC transient.

• Alternatively, the capacitor is repeatedly charged and discharged through the

resistor using rapid pulse-width modulation. The duty cycle is adjusted so that
the voltage on the capacitor matches the input. This acts as a sort of
integrating or sigma–delta ADC.

USE OF COMPARATOR FOR CAPACITIVE TOUCH SENSING

The sensor works by detecting the change in capacitance when a finger is
brought over it. Figure shows a simplified example. Here the capacitor is
formed by two conductingpads on the bottom of an insulating board, with the
board itself acting as an insulator (dielectric)between the plates of the
capacitor. One pad is connected to ground and the other acts as the sensor.

Anelectric field is created when a voltage is applied between the plates and the
field lines gofrom one plate to the other. Some of the lines remain in the
insulator but others emerge intothe air. When a finger is brought close to the
gap between the pads as in Figure (b), it distorts theelectric field and therefore
changes the capacitance. Any change in capacitance of the sensor corresponds
to a change in frequency which can be measured using the internal Timer_A
hardware of the MSP430.

APPLICATIONS OF COMPARATOR-A

1. Slope conversion of a resistance

2. Relaxation oscillator
3. Capacitive touch sensor

FEATURES OF ADC 10

The main features of ADC10 are as follows:

 ● Greater than 200 ksps maximum conversion rate
● Monotonic 10 bit converter with no missing codes
● Sample and hold with programmable sample periods
● Conversion initiation by software or timer-A
● Software selectable on-chip reference voltage generation
● Software selectable internal or external reference
● Up to eight external input channels
● Conversion channels for internal temperature sensor, VCC and external
references
● Selectable conversion clock source
● Single channel, repeat single channel, sequence and repeat sequence
conversion modes
● ADC core and reference voltage can be powered down separately
● Data transfer controller for automatic storage of conversion results

ARCHITECTURE OF ADC 10

Figure shows a simplified block diagram of the ADC10 in the F20x2; there are
more inputs in larger devices.The module looks more complicated because of
the wide range of options which are controlled by the registers ADC10CTL0 and
ADC10CTL1. The module is inactive when the ENC bit is clear.

The different blocks of the ADC10 module are described as below:

Core:At the heart of the ADC10 is a 10-bit, switched-capacitor, SAR core. It is

guaranteed monotonic with no missing codes. The ADC10ON bit enables the
core and a flagADC10BUSY is set while sampling and conversion is in progress.
The result iswritten to ADC10MEM in a choice of two formats, selected with
the ADC10DF bit:

• The default is straightforward, right-justified binary in the range 0x0000–

0x03FF.

• Alternatively, the result can be left-justified in twos complement format.

Clock:This can be taken from MCLK, SMCLK, ACLK, or the module’s internal
oscillatorADC10OSC, selected with the ADC10SSELx bits. It must lie within the
range0.45–6.3MHz for the F20x2.The frequency of the clock can be divided by
2, 3, . . . , 7, 8 by configuring the ADC10DIVx bits. The output of the divider is
labeled ADC10CLK and feeds both theSAR core and sample-and-hold blocks.

Sample and Hold circuit: This is shown separately in the block diagram but is
presumably integrated into the SAR network. The time is chosen with the
ADC10SHTx bits, which allow 4, 8, 16, or 64 cycles of ADC10CLK.

Input selection: A multiplexer selects the input from eight external pins A0–A7
and four internal connections. Two of the internal connections are for optional
and the other two internal connections are A10 to a temperaturesensor and
A11 to Vmid = ½ (VCC+VSS).

Conversion trigger: A conversion can be triggered in two ways provided that

the ENC bit is set. The first is by setting the ADC10SC bit from software. The
second method is by a rising edge on the input.

Voltage references and buffer: ADC 10 uses VR+ and VR- as the upper and
lower references.

The lower reference is selected with SREF2 bit. It can be ground VSS or an
external reference signal VeREF-. The upper reference is selected with SREF0
and SREF1 bits. It can be analog supply voltage AVCC, internal reference VREF+
or an external reference VeREF+.

A buffer is needed between the internal reference and the core of the ADC10.
This isenabled only when needed because it draws more current than any
other part of themodule.

Interrupts: The interrupt flag ADC10IFG is raised when the result is written to
ADC10MEM, except when the DTC (Data Transfer Control) is used.

BASIC OPERATION OF ADC10

Three steps are required to make a single conversion with the ADC10. They
are:

1. Configure the ADC10, including the ADC10ON bit to enable the module.
TheENC bit must be clear during this operation because most bits in
ADC10CTL0 andADC10CTL1 can be changed only when ENC = 0.

2. Set the ENC bit to enable a conversion. This cannot be done while the
module isbeing configured in the previous step.

3. Trigger the conversion, either by setting the ADC10SC bit or by an edge from
Timer_A.

The last two steps must be repeated for each conversion, which requires
clearing andsetting the ENC bit again.

USE OF ADC10 FOR TEMPERATURE SENSING

 ● We can use the on-chip temperature sensor by selecting the analog
input channel INCHx=1010
● Selecting the temperature sensor automatically turns on the on-chip
reference generator as a voltage source for the temperature sensor
● Temperature sensor gives a voltage that depends on temperature and
the data sheet gives a typical transfer function of
Vtemp = 3.55Θ+986 = 3.55(Θ+278) mV, where the temperature Θ is
measured in Celsius.
● Since there may be an offset of ±100mV, we may need to calibrate the
sensor
● The voltage from the sensor does not exceed 1.4V over the commercial
range oftemperature, so the 1.5V reference is appropriate.
● For 1.5 reference voltage, the output Ntemp of the ADC10 corresponding
to the sensor output voltage is,

● In terms of Θ we have,

● This can also be written as Θ ≈ 0.41Ntemp−278, which shows that a

change of one bitcorresponds to about 0.4◦C. In other words, this is the
LSB or resolution of the sensor.The extra two bits in the ADC12 reduce
LSB to roughly 0.1◦C.

FEATURES OF ADC 12
The main features of ADC12 are as follows:

● Greater than 200 ksps maximum conversion rate

● Monotonic 12 bit converter with no missing codes
● Sample and hold with programmable sampling periods controlled by
software or timers
● Conversion initiation by software, timer-A or timer-B
● Software selectable on-chip reference voltage generation
● Software selectable internal or external reference
● Eight individually configurable external input channels
● Conversion channels for internal temperature sensor, AVCC and external
references
● Independent channel selectable reference sources for both positive and
negative references
● Selectable conversion clock source
● Single channel, repeat single channel, sequence and repeat sequence
conversion modes
● ADC core and reference voltage can be powered down separately
● Interrupt vector register for fast decoding of 18 ADC interrupts
● 16 conversion result storage registers