ECEN 325 Lab 7: Characterization and DC Biasing of the BJT

Objectives
The purpose of this lab is to characterize NPN and PNP bipolar junction transistors (BJT), and to analyze and design
DC biasing circuits to set the DC operating point of BJTs.

Introduction
Figure 1 shows typical symbols for the NPN and PNP BJTs. Depending on the applied DC bias, BJT has three
regions of operation:

• Cutoff Region: If both base-emitter and base-collector junctions are reverse biased, the BJT enters the cutoff
region. All terminal currents are extremely small, and the transistor is off.
• Active Region: The base-emitter junction is forward biased, and the base-collector junction is reverse biased
to make a BJT operate in the active region. The active region is used to design a linear amplifier.

• Saturation Region: When both the base-emitter and base-collector junctions are forward biased, the BJT enters
the saturation region.

C E
IC IE
IB VEB
B VCE B VEC
VBE IB
IE IC
E C
(a) (b)

Figure 1: Bipolar junction transistor (BJT) (a) NPN (b) PNP

In the active region, the collector current (IC ) of NPN and PNP devices are exponential functions of base-emitter
voltage (VBE ) and emitter-base voltage (VEB ), respectively, given by

IC ,npn = IS e VBE /VT IC ,pnp = IS e VEB /VT (1)

where IS is the saturation current and VT is the thermal voltage, which is approximately 25mV at room temperature.
For both NPN and PNP, the base current IB is a small fraction of IC , given by

IC
IB = (2)
β

and the emitter current IE is the sum of the base and collector currents, given by

IC
IE = IC + IB = (β + 1)IB = (3)
α
where
β
α= (4)
β+1
β is known as the current gain of the transistor, which varies significantly with temperature, and it can be different
between two transistors of the same type. Typical value of β is around 100, resulting in α = 0.99.

© Department of Electrical and Computer Engineering, Texas A&M University

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BJT Characterization
Figure 2 shows a characterization circuit for an NPN BJT. To obtain IC as a function of VBE , V1 is swept while V2
is kept constant, resulting in the exponential function in Fig. 3(a). If V1 is kept constant and V2 is swept, IC can be
obtained as a function of VCE as shown in Fig. 3(b).

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Figure 2: NPN BJT characterization circuit

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✎✏✑ ✒✎✓ ✎✏✑ ✒✎✓

(a) (b)

Figure 3: Collector current (IC ) of an NPN BJT as a function of (a) VBE (b) VCE

Characterization circuit for a PNP BJT is shown in Fig. 4. Keeping V2 constant and sweeping V1 provides IC as an
exponential function of VEB as shown in Fig. 5(a). Sweeping V2 while V1 is kept constant provides the IC vs. VEC
characteristics as shown in 5(b).

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Figure 4: PNP BJT characterization circuit

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(a) (b)

Figure 5: Collector current (IC ) of a PNP BJT as a function of (a) VEB (b) VEC

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BJT DC Biasing - Resistive
Figures 6(a) and (b) show typical resistive biasing circuits for NPN and PNP transistors, respectively.

VCC VCC

RB1 RC RB2 V2 VRE RE

VC
IB 0.7
VCE VEC
0.7 IB
VC
RB2 V2 VRE RE RB1 RC

−VEE −VEE
(a) (b)

Figure 6: Resistive DC biasing circuit for (a) NPN (b) PNP

For each circuit in Figs. 6(a) and (b), assume that the transistor is active, and IB is negligible, which means RB1 and
RB2 form a voltage divider to set the V2 voltage. Therefore, IE and IC can be found as

RB2 V2 − 0.7
V2 ≈ (VCC + VEE ) ⇒ IE = ≈ IC (5)
RB1 + RB2 RE
All assumptions must be verified to complete the DC analysis. For the circuits in Figs. 6(a) and (b), IB is negligible
only if IB  IRB1 , which requires
IC VCC + VEE
IB =  IRB1 ≈ (6)
β RB1 + RB2
To verify that the NPN transistor is active, VCE ≥ VCE ,sat should be satisfied as follows

VCE = VCC + VEE − IC (RC + RE ) ≥ VCE ,sat (7)

For the PNP transistor, active operation requires VEC ≥ VEC ,sat as follows

VEC = VCC + VEE − IC RC + RE ≥ VEC ,sat (8)

where VCE ,sat ≈ VEC ,sat ≈ 0.2V

BJT DC Biasing - Current Source

An alternative method for BJT DC biasing is to use a current source connected to the emitter terminal, which directly
sets the IE current, and hence the IC current. Figure 7(a) shows the DC biasing of an NPN BJT using a current source,
which can be realized using the circuits in Fig. 7(b) or (c). Figure 8 shows the DC biasing circuit of a PNP BJT using
a current source, as well as current source and current mirror realizations.

VCC VCC
VCC
RB1 RC R4
VC Ix R1 Ix
IB
VCE
0.7

RB2 V2 Vx Ix R3 Vy R2 R6 R5

−VEE −VEE −VEE

(a) (b) (c)

Figure 7: (a) DC biasing circuit for an NPN BJT using a current source (b) Current source (c) Current mirror

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 VCC VCC VCC

RB1 V2 Vx Ix R3 Vy R2 R6 R5

0.7
VEC
IB Ix R1
VC Ix
RB2 RC R4
−VEE

−VEE −VEE

(a) (b) (c)

Figure 8: (a) DC biasing circuit for a PNP BJT using a current source (b) Current source (c) Current mirror

For the current sources in Figs. 7(b) and 8(b), Ix can be calculated as
R2 Vy − 0.7
Vy ≈ (VCC + VEE ) ⇒ Ix ≈ (9)
R1 + R2 R3
For the current mirrors in Figs. 7(c) and 8(c), assuming matching transistors and R5 = R6 , Ix can be calculated as
VCC + VEE − 0.7
Ix ≈ (10)
R4 + R5
All transistors in Figs. 7 and 8 are assumed to be active, and all IB currents are assumed to be negligible. These
assumptions need to be verified after finding the DC solution.

Calculations
1. Design the circuits in Figs. 6(a) and 6(b) with the following specifications:
NPN PNP
IC 1mA IC 1mA
VC 3.5V VC 1.5V
VCE ≥ 1V VEC ≥ 1V
VRE ≥ 1V VRE ≥ 1V
VCC 5V VCC 5V
VEE 0 VEE 0
β 100 β 100
VT 25mV VT 25mV
Isupply ≤ 2mA Isupply ≤ 2mA

For both circuits, DC biasing should be insensitive to variations in β and |VBE |, and IB currents should be
designed to be negligible.
2. Design the circuits in Figs. 7(a) and 8(a) using the current sources in Figs. 7(b) and 8(b), respectively, with the
following specifications:
NPN PNP
IC 2mA IC 2mA
VC 3.5V VC 1.5V
VCE ≥ 1V VEC ≥ 1V
Vx ≥ 1.5V Vx ≥ 1.5V
VCC 5V VCC 5V
VEE 0 VEE 0
β 100 β 100
VT 25mV VT 25mV
Isupply ≤ 5mA Isupply ≤ 5mA

For both circuits, DC biasing should be insensitive to variations in β and |VBE |, and IB currents should be
designed to be negligible.

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Simulations
For all simulations, provide screenshots showing the schematics and the plots with the simulated values prop-
erly labeled.

1. Draw the schematics for the NPN characterization circuit in Fig. 2 using the 2N3904 transistor
• Perform a DC sweep of V1 from 0 to 5V, while V2 = 5V . Export the simulation data to Excel, and plot IC
as a function of VBE .
• Perform a DC sweep of V2 from 0 to 5V, while V1 = 2V . Export the simulation data to Excel, and plot IC
as a function of VCE .
2. Draw the schematics for the PNP characterization circuit in Fig. 4 using the 2N3906 transistor
• Perform a DC sweep of V1 from -5V to 0, while V2 = −5V . Export the simulation data to Excel, and plot
IC as a function of VEB .
• Perform a DC sweep of V2 from -5V to 0, while V1 = −2V . Export the simulation data to Excel, and plot
IC as a function of VEC .
3. Draw the schematics in Figs. 6(a) and 6(b) using the calculated component values and 2N3904 and 2N3906
transistors. For both circuits, perform DC operating point or interactive simulation to obtain the DC solution
for IC , VC , VRE and V2 .

4. Draw the schematics in Figs. 7(a) and 8(a) using the current sources in Figs. 7(b) and 8(b), respectively, with the
calculated component values and 2N3904 and 2N3906 transistors. For both circuits, perform DC operating
point or interactive simulation to obtain the DC solution for IC , VC , V2 , Vx and Vy .

Measurements
For all measurements, provide screenshots showing the plots with the measured values properly labeled.

1. Build the NPN characterization circuit in Fig. 2 using the 2N3904 transistor

• Apply a ramp signal from 0 to 5V at 1Hz for V1 while V2 = 5V . Export the voltage measurements from
the scope to Excel, and plot IC as a function of VBE .
• Apply a ramp signal from 0 to 5V at 1Hz for V2 while V1 = 2V . Export the voltage measurements from
the scope to Excel, and plot IC as a function of VCE .
2. Build the PNP characterization circuit in Fig. 4 using the 2N3906 transistor

• Apply a ramp signal from -5V to 0 at 1Hz for V1 while V2 = −5V . Export the voltage measurements
from the scope to Excel, and plot IC as a function of VEB .
• Apply a ramp signal from -5V to 0 at 1Hz for V2 while V1 = −2V . Export the voltage measurements
from the scope to Excel, and plot IC as a function of VEC .

3. Build the circuits in Figs. 6(a) and 6(b) using the calculated component values and 2N3904 and 2N3906 tran-
sistors. For both circuits, measure the DC values for IC , VC , VRE and V2 using the voltmeter or scope.
4. Build the circuits in Figs. 7(a) and 8(a) using the current sources in Figs. 7(b) and 8(b), respectively, with the
calculated component values and 2N3904 and 2N3906 transistors. For both circuits, measure the DC values
for IC , VC , V2 , Vx and Vy using the voltmeter or scope.

Report
1. Include calculations, schematics, simulation plots, and measurement plots.

2. Prepare a table showing calculated, simulated and measured results.

3. Compare the results and comment on the differences.

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Demonstration
1. Build the circuits in Figs. 2, 4, 6(a), 6(b), 7(a)&(b) and 8(a)&(b) on your breadboard and bring it to your lab
session.
2. Your name and UIN must be written on the side of your breadboard.

3. Submit your report to your TA at the beginning of your lab session.

4. For the NPN characterization circuit in Fig. 2:
• Apply a ramp 0 to 5V at 1Hz for V1 while V2 = 5V , and export the measurements from scope to Excel.
• Plot IC as a function of VBE in Excel.
5. For the PNP characterization circuit in Fig. 4:
• Apply a ramp -5V to 0 at 1Hz for V2 while V1 = −2V , and export the measurements from scope to Excel.
• Plot IC as a function of VEC in Excel.

6. For the resistive NPN and PNP biasing circuits in Figs. 6(a) and 6(b):
• Measure the DC voltages VC , VB , VE .
• Calculate IC from the voltage measurements.
7. For the current-source NPN and PNP biasing circuits in Figs. 7(a)&(b) and 8(a)&(b):

• Measure the DC voltages VC , VB , VE for both transistors.

• Calculate IC from the voltage measurements.