Photomask

BACUS—The international technical group of SPIE dedicated to the advancement of photomask technology.
N • E • W • S
february 2022
Volume 38, Issue 2

SPIE Photomask Technology + EUV Lithography

2nd Place Winner - Zeiss Award for Talent in the Industry

iN5 EUV Single Expose Patterning

Evaluation for Via Layers
Argho Das, IMEC, Kapeldreef 75, 3001 Leuven, Belgium; Hochschule Furtwangen University
(HFU), Robert-Gerwig-Platz 1, 78120 Furtwangen, Germany
Victor Blanco, Sayantan Das, Sandip Halder, and Mircea Dusa, IMEC, Kapeldreef 75, 3001
Leuven, Belgium
Nicola Kissoon, ASML Technology Development Center, Kapeldreef 75, 3001 Leuven, Belgium
ABSTRACT
The continuous need to shrink dimensions using EUV lithography has posed challenges and opportunities
for patterning materials and processes. Scaling BEOL interconnect structured is a key element to perfor-
mance improvement of functional devices. In this paper, we investigate the impact of various factors on the
patterning of EUV single exposure vias, to find effective strategies to shrink critical dimension (CD) with
improved critical dimension uniformity (CDU), local critical dimension uniformity (LCDU) and decrease in
defectivity. This work is based on patterning a system on chip (SoC) random logic via layer at minimum
horizontal interconnect wire pitch of 28nm, which is the limit of single exposure interconnect with 0.33 NA
EUV tools. This design uses aggressive CPP/Mx gear ratio of 3/2 which is equivalent to 38nm to 34nm pitch
orthogonal via arrays, thus, examining the impact of the primary patterning parameter and illumination
source co-optimized with OPC treatment of rectangular vias. The via patterns are transferred to bottom
dielectrics to study the evolution of LCDU and defectivity through etch.

Take A Look
Inside:

Industry Briefs
—see page 10

Calendar
For a list of meetings
—see page 11
11854-23

Figure 1. Random logic structures (left) and SRAM memory structures (right) – via & metal layers.
Editorial
Looking forward, full steam ahead N • E • W • S
Romain Lallement, IBM BACUS News is published monthly by SPIE for
When I joined the semiconductor industry more than a decade ago as BACUS, the international technical group of SPIE
lithography process engineer, my day-to-day job was elusive to my family dedicated to the advancement of photomask
technology.
beyond the final goal of chip making. It will not come as a surprise to
anyone if I say it is still the case, but they are now aware of how prevalent
Managing Editor/Graphics Linda DeLano
our work is to society. For a long time, semiconductor devices were quietly
SPIE Sales Representative, Exhibitions, and Sponsorships
being introduced to our pockets, homes, cars, warehouses until suddenly Melissa Valum
there were not enough of them. One of the ripple effects of the pandemic BACUS Technical Group Manager Tim Lamkins
is an increased thirst for computing, automation, and data to make us ever
more interconnected. What makes me hopeful and even excited is the
amount of innovation that we see across our ecosystem to fill the gap and ■ 2022 BACUS Steering Committee ■
go beyond. President
Emily E. Gallagher, imec.
Gate All Around (GAA) technology has been embraced by integrated
device manufacturers (IDM) and foundries. The transition from FinFET Vice-President
to NanoSheet will continue to push device scaling and improve power Kent Nakagawa, Toppan Photomasks, Inc.

consumption for the next nodes. Secretary

Artificial Intelligence (AI) is moving down the stack from pure software Jed Rankin, GLOBALFOUNDERIES Inc.

application to dedicated hardware. Novel architectures and materials Newsletter Editor

in memory computing will significantly advance model training and Artur Balasinski, Infineon Technologies
inference. Bringing memory closer to the processor core will alleviate the
Von Neumann bottleneck, speeding up computing and the overall chip 2022 Photomask + Technology Conference Chairs
power consumption. Bryan S. Kasprowicz, HOYA
Ted Liang, Intel Corp.
Quantum computing is being pursued by large companies and start-
ups alike. It has the potential to shift the paradigm, making prohibitive Members at Large
Frank E. Abboud, Intel Corp.
computing problems of the past within the realm of possibility today.
Uwe F. W. Behringer, UBC Microelectronics
What does this all mean for the mask industry? I believe none of the Ingo Bork, Siemens EDA
Tom Cecil, Synopsys, Inc.
technologies listed above will replace the other. They will coexist and
Brian Cha, Entegris Korea
complement each other to create systems that are far more powerful Jonggul Doh, Samsung Electronics Co., Ltd.
than the individual units. In other words, the overall integrated circuit (IC) Aki Fujimura, D2S, Inc.
portfolio will grow in volume and variety. Mask making is already adapting Jon Haines, Micron Technology Inc.
Naoya Hayashi, Dai Nippon Printing Co., Ltd.
to it. The first straightforward evolution is the increased capacity. Aging
Henry Kamberian, Photronics, Inc.
tool replacement will hopefully offer efficiency benefits. The leading edge Romain J Lallement, IBM Research
is not shy of innovations either. The EUV community is on the lookout Khalid Makhamreh, Applied Materials, Inc.
for what comes after the Ta-based mask stack and exploring EUV phase Jan Hendrik Peters, bmbg consult
Douglas J. Resnick, Canon Nanotechnologies, Inc.
shifting masks. The MultiBeam writer improves the raw performance metric
Thomas Scheruebl, Carl Zeiss SMT GmbH
and opens the door for curvilinear design, leading to open discussions on Ray Shi, KLA Corp.
design file format. Thomas Struck, Infineon Technologies AG
Anthony Vacca, Automated Visual Inspection
It is indeed an exciting time as every aspect of the mask community is Vidya Vaenkatesan, ASML Netherlands BV
evolving and enabling the next revolutions in compute. The renewed Andy Wall, HOYA
interest is the icing on the cake to attract more talent. Michael Watt, Shin-Etsu MicroSi Inc.
Larry Zurbrick, Keysight Technologies, Inc.

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Volume 38 Issue 2 Page 3

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Figure 2. (a) Via patterning stack after lithography and vias of random logic structure-ADI (b) Via patterning stack after SiN etch and vias of random logic structure-AEI.

1. Introduction (via failures), massive data collection, statistical analysis with CDSEM
and e-beam data post lithography and etch has been done. Figure (3)
The limits of EUV single exposure, for such aggressive design rules to print illustrates random Logic place and route and SRAM via holes respectively
non-arrayed randomly distributed via holes, poses a patterning challenge that have been designed for patterning the SoC device layers.
due to the stochastic effects present in EUV imaging combined with small
vias CDs. In this work, the patterning transfer of via holes in SRAM and 2.1 EUV Exposure
random logic structures post lithography were evaluated from an ARM The exposure process was carried out on a ASML NXE3400 full field EUV
clip with metal 2 pitches ranging from 24 nm to 30 nm. The isolated vias scanner in the 300 mm cleanroom with an illumination that has been cus-
instances which have been highlighted in yellow in Fig.1, is 5 times in Field tomized and by a mask vehicle with optical proximity corrections (OPC).
of View (FoV); the vertical cluster of vias at 2 times of the minimum pitch OPC was applied on the via structures, but no bias was applied. When
which has been highlighted in white, is 1 time in FoV; the diagonal clusters aligning the wafers, phase grating alignment has been used to detect
at minimum design, center-to-center has been highlighted in blue and is targets. An UV-based level sensor contributed towards reducing the wafer
4 times in the FoV; the horizontal doublets as highlighted in red is 2 times film stack variation to the process-dependent height variations. Pattern-
in FoV; the diagonal doublets as highlighted in green is 5 times in FoV; ing with a CAR photoresist was done using the nitride stack as described
large rectangular vertical holes as highlighted in white is 11 times in the in figure (2), focusing mainly on pitch 28 nm with further exploration
FoV; triangular triplets as highlighted in green is 12 times in FoV as shown of pitches 30 nm, 26 nm, and 24 nm. The resist was coated on stacked
in Figure (1). An optimal and advanced chemically amplified resist (CAR) wafers with an underlayer of spin-on-glass (SOG) thickness of 10 nm.
and patterning stack was selected and etch optimization was performed
on TEL etch tool to shrink after development inspection (ADI) CD to final 2.2 Photoresist Screening
design CD. Figure 2(a) illustrates the stack details post EUV lithography The first Focus Energy Matrix (FEM) wafers had been exposed to ascertain
exposure. A continuous titanium layer at the bottom of the stack is used the best dose-focus conditions for future wafers exposure. Optimum
to enable voltage contrast (VC) metrology and defectivity investigation process windows were generated along with graphs for Bossung curve
post etch. The printing and pattern transfer capabilities at ADI and after and observe the quality of printing of the vias at certain dose, focus and
etch inspection (AEI) were investigated. Initial process window and CD CD conditions. Resist screening was done based on the process window
evaluation was done using Hitachi critical dimension scanning electron analysis at an optimum dose to size and we were already able to capture
microscope and contouring methods. a process window for our target pitch of 28 nm with the desired photo-
Patterned mask used with a reduction ratio of 4:1. In the reduction of resist based on the current FEM-lithography conditions. In figure (4), a
structure sizes, single patterning in place of multi patterning has been process window overlap (in black region) was generated between the
used. Figure 2(b) illustrates the stack details post etch and illustrates process windows of pitches 26nm (in orange), 28nm (in blue), 30 nm (in
the printing of the random logic via holes on silicon nitride hard mask. green) to check for the optimum dose and focus conditions that were
The minimum center-to-center dimension of the random logic struc- necessary for printing on the wafers across all the aforesaid pitches for
tures was around 48 nm and around 50 nm in SRAM structures. The Logic and SRAM structures. A process window overlap along with pitch
current focus is on further shrinkage of critical dimensions to meet the 24 nm (in yellow) was not derived because at a lower pitch, a higher
design CD target of less than 20 nm. dose to size ratio is being necessary for good printing whereas for the
2. Experimental remaining pitches, optimum dose-focus conditions could be already de-
termined for exposure. A stack comprising of silicon nitride was selected
EUV lithography was first used in high volume production at the 7 nm for lithography and etch processes’ development.
node. Its application includes contact and via layers; and due to dense
pattern density characteristics of single-exposure EUV imaging, defec- 2.3 Methodology
tivity probability increases. Dimensional & defect inspection metrology In this work, back-end-of-line processes involving metal and via layers
Page 4 Volume 38, Issue 2

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Figure 3. Random Logic Place & Route (P&R) Via structures, SRAM via structures, Metal 1 (M1) and Metal 2 (M2) layers.

Figure 4. Process windows overlap for determining optimum dose-focus conditions for SRAM and Logic structures.

were evaluated to assess 0.33 NA EUV single patterning limits. Wafer our major focus on Pitch 28 nm module. Furthermore, e-beam inspec-
maps were generated to analyze the die-to-die fingerprints to under- tion was done with eP5, large FoV SEM tool for large statistical data
stand the characteristics of printing such as local CD uniformity and collection.
CD uniformity on the dies post-lithography (ADI) and additionally, a
center-to-edge fingerprint in case of after etch inspection (AEI) enabling 3. Results and Discussions
viable observations for both Logic and SRAM structures on pitch 28 nm
as shown in Figure (5). 3.1 Etch DoE & Critical Dimension Scanning Electron
Small and slot vias in SRAM structures show center to edge fingerprint Microscopy
post-etch CDSEM inspection and random logic vias post-etch CDSEM The critical dimension is one the most critical variable in lithography
inspection also show considerable fingerprint. Through several etch which is the minimum distance measured within the boundaries of a via
design of experiment (DoE), large statistical data were collected from edges. The CD defines the width or height of a via, depending on the
CDSEM inspection initially focusing on all pitches but concluding with
Volume 38 Issue 2 Page 5

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Figure 5. Post lithography (ADI) and post etch (AEI) wafer maps and via printings for SRAM and Logic structures at pitch 28 nm.
Page 6 Volume 38, Issue 2

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Figure 6. Post lithography (ADI) CD, CDU, LCDU trend for SRAM and Logic structures through pitches.

Figure 7. Post etch DoE (AEI) CD, CDU, LCDU trend for SRAM small and slot vias studied separately (pitch 28nm).

measurement direction along x-direction or y-direction respectively. The SRAM modules, concluding metrology was focused on pitch size 28 nm
CDU determines the deviation of the CD per die from the wafer’s average SRAM module. CD and defectivity were also simultaneously monitored
CD. The LCDU is the deviation of the CD of each via within a SEM FoV with large FoV e-beam inspection on eP5 tool.
from the average die CD. Both CDU and LCDU are statistical calculations Certain CD shrinkage has been observed on SRAM slot vias after etch-
that refer to data within three standard deviations (3-sigma) from the ing on CD measured on wafers D10-D13 to around 30nm compared to
mean CD value. around 40nm on D03, D06 and D07 as shown in figure (7). Further DoE
In figure (6), on SRAM and logic structures, we achieved an average at specific etch steps and stack has helped to reduce LCDU to below 5
ADI CD, on pitch 28 nm of around 27 nm, on pitch 24 nm of around nm and CDU to less than 1.5 nm. Optimized Etch DoEs makes it possible
21nm, on pitch 26 nm of around 26 nm or lesser, on pitch 30 nm of to reduce CD after etching. On pitch 28nm SRAM module, post etch has
around 28 nm. The next challenge lies in shrinkage of CD post etch to enabled small via CD ~ 14.48nm with slot via CD ~ 19.55nm.
less than 20 nm. In the meantime, AEI CDU and LCDU should be less
than 1.5 nm and 5 nm respectively. Etch DoEs were done on TEL etch 3.2 Voltage Contrast Metrology & E-beam inspection with
tool, with several iterations and optimization with split in SOG thick- HMI eP5 metrology
nesses, etch deposition and trim steps, different gas chemistries, spin- While the physical inspection can reveal via holes anomalies on top layer
on- carbon (SOC) and silicon Nitride etch time, silicon nitride over-etch (at resist level ADI or hard mask AEI), the Voltage Contrast (VC) metrology
and descum among others. Every iteration was followed by thorough helps to check the bottom of the via layer. When Ruthenium is filled into
CDSEM inspection on random Logic and SRAM vias initially, however, the vias on wafers post etch, VC metrology shows if the bottom of the
keeping in mind the complexity of the SRAM structures over logic vias; vias is open or not as illustrated in figure (9). Physical voltage contrast
both small and slot vias were measured within the same FoV for the defect inspection is also possible because of the titanium layer at the
Volume 38 Issue 2 Page 7

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Figure 8. Post etch DoE (AEI) data for SRAM small and slot/large vias at pitch 28 nm demonstrating etch shrink to our target below 20 nm.

Figure 9. VC inspection metrology enabling detection of very small vias at pitch 24 nm.

bottom of the stack. 4. Conclusion

HMI-eP5 tool enabled us to collect large field of view images of 8μm x
8μm with default image condition settings. Over 7000 vias per die were Random logic and SRAM vias are studied for metal 2 to metal 1 layers.
measured on the logic clip. It was confirmed that SRAM vias are open Experimental results demonstrated AEI CD of less than 20nm on design
validating the etch optimization. Large scale data collected with eP5 target of Pitch 28 nm for both small and slot vias. AEI CD of around 15
included CD measurements that could be used to retrieve parameters nm & LCDU less than 5 nm was achieved with a combination of optimum
like CD, LCDU, defectivity, height, width, small vs slot vias, CoG shift SoG thickness and specific etch DoEs. E-beam inspection enabled larger
in X-direction, CoG shift in Y-direction, area in single file in a relatively FoV data collection on SRAM and Logic vias. From both pitch 28 nm and
short inspection time. As shown in figure (10), on aligning GDS to image pitch 26 nm, SRAM and logic structures images collected from e-beam
obtained from eP5, it is easy to find merged vias visually at the region shows high probability of smaller vias in the normal quantile tail. A larger
of aggressive design. FoV enabled initial assessment of via missing after metallization using
Further analysis of eP5 data by plotting quantile plots has enabled us VC measurement and to check the bottom of the vias.
to look for any via CD within the distribution. From figure (11), at the
bottom tail of the quantile plot, very small vias can be seen with the
5. Acknowledgement
smallest CDs. The plot also shows that small vias and slot via width We would like to extend our gratitude for the contribution of the Etch
were properly measured. In figure (12) and (13), for SRAM and Logic Team of Tokyo Electron Limited (TEL) in Leuven, Belgium.
vias respectively, learning is achieved through the pitches in terms of
CD shrinkage with the different Etch DoEs due to large number of vias
measured and data collected with eP5 inspection.
Page 8 Volume 38, Issue 2

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Figure 10. (Left & Center) Small area from a large FoV on SRAM and logic clip; (Right) Image collected post eP5 inspection shows GDS aligned to image.

Figure 11. Quantile plot showing small via on distribution lower tail location with high probability of via closure defect (dimension measured in x-direction on via).

6. Reference
[1] Simulation investigation of enabling technologies for EUV single
exposure of Via holes patterns in 3nm logic technology, W. Gao,
et al, doi.org/10.1117/12.2552888.
Volume 38 Issue 2 Page 9

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Figure 12. Post Etch (AEI) CD, CDU, LCDU data collected on two pitches from eP5 inspection on SRAM vias.

Figure 13. Post Etch (AEI) CD, CDU, LCDU data collected on two pitches from eP5 inspection on Logic vias.
Page 10 Volume 38, Issue 2

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Industry Briefs
■ Hitachi Launches E-beam Inspection System for EUV 3nm and
5nm Processes
N•E•W•S David Manners
Hitachi High-Tech Corporation today announced the Development of its Electron Beam
Area Inspection System. The device manufacturers are beginning to utilise EUV in the mass
Sponsorship Opportunities production of 5nm node devices and the development of 3nm node devices. GS1000 is an
advanced conventional Electron Beam Inspection  system. It is a fusion of a high-performance
Sign up now for the best sponsorship electron optical system and a high-speed, large-capacity data processing system, which
opportunities provides solutions to the challenges that arise when introducing EUV lithography to
semiconductor device mass-production.
Photomask Technology + https://www.electronicsweekly.com/news/business/hitachi-launches-euv-2021-12/
EUV Lithography 2022
Contact: Melissa Valum ■ Intel Mum on Ohio Fab Project
Tel: +1 360 685 5596; [email protected]
Alan Patterson
Advanced Lithography + Patterning Intel Corp. remains tight-lipped in response to a report that it will build a $20 billion fab in Ohio.
2022 The largest U.S. chip maker has chosen a site in Licking County, just east of the state capitol
Contact: Teresa Roles-Meier of Columbus. The proposed fab would directly employ 3,000 workers, helping to create an
ecosystem of material and equipment suppliers.
Tel: +1 360 685 5445; [email protected]
“We will decline to comment on this,” William Moss, Intel’s senior director for corporate
communications, said in an email reply to our query about the report. Intel launched two
new chip projects last year in Chandler, Ariz., to provide additional capacity for its foundry
Advertise in the customers. The $20 billion initiative is the largest private-sector investment in Arizona history.
BACUS News! Late last year, Samsung selected a Texas site for its latest fab project, which will cost $17 billion.
That facility will extend capacity at an existing Samsung fab in nearby Austin. TSMC said it will
The BACUS Newsletter is the premier spend as much as $44 billion in 2022 to maintain its manufacturing edge over foundry rivals
publication serving the photomask such as Samsung and Intel. Taiwan-based TSMC is currently building a 5-nm fab in the Phoenix
industry. For information on how to area. That process node is already in production in Taiwan. TSMC will be the world’s first to
advertise, contact: start production of 3-nm chips in late 2022. The new 5-nm TSMC fab in Arizona, announced
in 2020, will start production in 2024.
Responding to technology supply chain disruptions, proposed federal incentives are designed
Melissa Valum
to attract new U.S. foundry investments. The $52 billion CHIPS for America Act approved by
Tel: +1 360 685 5596 the U.S. Senate is aimed at reviving the domestic industry over the next decade. The bill must
[email protected] still be approved by the House.
https://www.eetimes.com/intel-mum-on-ohio-fab-project/#

BACUS ■ Reliability Concerns Shift Left Into Chip Design

Corporate Members Ann Steffora Mutschler
Acuphase Inc. Demand for lower defect rates and higher yields is increasing, in part because chips are now
American Coating Technologies LLC being used for safety- and mission-critical applications, and in part because it’s a way of
AMETEK Precitech, Inc. offsetting rising design and manufacturing costs. What’s changed is the new emphasis on
solving these problems in the initial design. In the past, defectivity and yield were considered
Berliner Glas KGaA Herbert Kubatz
problems for the fab. Restrictive design rules (RDRs) were implemented to ensure chips
GmbH & Co.
were designed in ways that could be successfully manufactured. But several things have
FUJIFILM Electronic Materials U.S.A., Inc. fundamentally changed since then:
Gudeng Precision Industrial Co., Ltd.
RDRs add too much margin into designs, particularly at advanced nodes. That negatively
Halocarbon Products impacts performance, power and area.
HamaTech APE GmbH & Co. KG
More chips are being customized for specific applications, utilizing advanced packaging,
Hitachi High Technologies America, Inc. different kinds of processors and memories, and unique architectures that have not been
JEOL USA Inc. produced in volume in the past.
Mentor Graphics Corp. Longer life expectancy for chips in some applications mean that latent defects can require
Molecular Imprints, Inc. costly recalls. As a result, design teams are starting to include sensors in designs to determine
Panavision Federal Systems, LLC how a chip is behaving until its anticipated end of life.
Profilocolore Srl A chip used in the drive train of an automobile, for example, has entirely different stresses and
Raytheon ELCAN Optical Technologies expectations than one produced for an IoT consumer device. Design teams need to understand
how these chips will behave over time, from environmental and use conditions, to aging,
XYALIS
electro-thermal, stress, and variation effects.
https://semiengineering.com/reliability-concerns-shift-left-into-chip-design/
Volume 38 Issue 2 Page 11

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